I/O Map - Intel D850MVSE Specification

Intel Desktop Board D850MD/D850MV Technical Product Specification

2.3 I/O Map

Table 14.

I/O Map

Address (hex)
0000 - 000F
0020 - 0021
0040 - 0043
0060
0061
0064
0070 - 0071
0072 - 0073
0080 - 008F
0092
00A0 - 00A1
00B2 - 00B3
00C0 - 00DF
00F0
0170 - 0177
01F0 - 01F7
One of these ranges:
0220 - 022F
0240 - 024F
(Note 1)
0228 - 022F
(Note 1)
0278 - 027F
(Note 1)
02E8 - 02EF
(Note 1)
02F8 - 02FF
0376
0377, bits 6:0
0378 - 037F
03B0 - 03BB
03C0 - 03DF
03E8 - 03EF
03F0 - 03F5
03F6
03F8 - 03FF
04D0 - 04D1
LPTn + 400
0CF8 - 0CFB (Note 2)
(Note 3)
0CF9
0CFC - 0CFF
FFA0 - FFA7
FFA8 - FFAF
48
Size Description
16 bytes DMA controller
2 bytes Programmable Interrupt Control (PIC)
4 bytes System timer
1 byte Keyboard controller byte—reset IRQ
1 byte System speaker
1 byte Keyboard controller, CMD / STAT byte
2 bytes System CMOS / Real-time clock
2 bytes System CMOS
16 bytes DMA controller
1 byte Fast A20 and PIC
2 bytes PIC
2 bytes APM control
32 bytes DMA
1 byte Numeric data processor
8 bytes Secondary IDE channel
8 bytes Primary IDE channel
16 bytes Audio
8 bytes LPT3
8 bytes LPT2
8 bytes COM4 / video (8514A)
8 bytes COM2
1 byte Secondary IDE channel command port
7 bits Secondary IDE channel status port
8 bytes LPT1
12 bytes Intel 82850 MCH
32 bytes Intel 82850 MCH
8 bytes COM3
6 bytes Diskette channel 1
1 byte Primary IDE channel command port
8 bytes COM1
2 bytes Edge / level triggered PIC
8 bytes ECP port, LPTn base address + 400h
4 bytes PCI configuration address register
1 byte Turbo and reset control register
4 bytes PCI configuration data register
8 bytes Primary bus master IDE registers
8 bytes Secondary bus master IDE registers
continued