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The contents of the command block registers related to addresses after the transfer of a data
block containing an erred sector are undefined. To obtain a valid error information, the host
should retry data transfer as an individual requests.
At command issuance (I/O registers setting contents)
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
At command completion (I/O registers contents to be read)
1F7
(ST)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(ER)
H
Note:
When the command terminates due to error, only the DV bit and the error information
field are valid.
(7)
WRITE DMA (X'CA' or X'CB')
This command operates similarly to the WRITE SECTOR(S) command except for following
events.
The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at completion of
the data transfer.
When an error, such as an unrecoverable medium error, that the command execution cannot be
continued is detected, the data transfer is stopped without transferring data of sectors after the
erred sector. The device generates an interrupt using the INTRQ signal and posts a status to
the host system. The format of the error information is the same as the WRITE SECTOR(S)
command.
A host system can be select the following transfer mode using the SET FEATURES
command.
5 - 24
1
1
0
0
L
DV
Start cylinder No. [MSB]/ LBA
Start cylinder No. [LSB] / LBA
Start sector No.
Transfer sector count
xx
Status information
L
DV
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No.
00
Error information
C141-E090-01EN
0
1
0
1
Start head No. /LBA [MSB]
/ LBA [LSB]
End head No. /LBA [MSB]
/ LBA [LSB]
H
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