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Convergence Processor
Figure 33
The Convergence data is stored in the EEPROM, 7000. The Microprocessor located on the ASC
module reads 1,971 bytes of data from 7000 and writes it to the Convergence Processor, 7002.
Horizontal sync is inverted by 7026, buffered by 7025, and fed to Pin 27 of 7002. Vertical sync is
inverted by 7027, buffered by 7028, and fed to Pin 28 of 7002. The data is processed to produce the
desired convergence correction waveforms which are output on six DACS. During the convergence
adjustment procedure, a 180 point alignment grid is output on Pins 16, 17, and 18. This signal is
mixed with the OSD to be displayed on the screen. In the 4x3 aspect ratio set, there are three sets of
convergence data. In sets with a 16x9 aspect ratio, there are two sets of convergence data. The set
will require convergence alignment for each set of convergence data. The correct mode must be
selected and the signal for that mode must be applied to the set during the convergence alignment.
The output of the DACS is fed to six op-amps before being fed to the Power Amplifiers located on the
SSM. When screen centering is being performed, it is necessary to disable the convergence drive
waveform. A High on Pin 77 turns transistor 7029 On, turning 7038 On, which turns transistors 7032,
7033, 7030, 7031, 7034, and 7035 On. This mutes the correction drive signal to the Power Amplifiers.
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