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Philips Semiconductors
Using the NE/SA5234 amplifier
configuration and its output is squared to swing approximately 5V,
the standard TTL level. Again common-mode biasing is passed
along from each of the stages up to the last in order minimize parts
and simplify circuit layout. The final stage is a simple buffer
amplifier to allow the receiver to drive a low impedance long wire
line of 600 to 900 resistance. Some rise time response
adjustment may be required. This is easily achieved following stage
three by using R
-C
to limit the rate of change of the signal voltage
T
T
prior to the buffer. Note that the last stage acts as a zero-crossing
detector. This maximizes noise immunity by allowing a transition
only after the third stage output voltage has risen above 2/3V
Phase inversion may be accomplished, if the logic level signals are
polarity reversed, by making stage 3 inverting and AC coupling the
input signal with a sufficiently large capacitor to reduce droop.
Stage 3 must then be biased by connecting its non-inverting node to
bias point 'A'. This provides a 2.5V threshold for the proper
C1
EXP
IN
+
10 F
RECT
EXP
CAP
+
2.2 F
C2
C3
+
EXP
10 F
OUT
C4
V
REF
+
10 F
R2*
PWRDN/
MUTE
*R1, R2 and R3 are 1% resistors.
1991 Oct
.
CC
10k
GAINCELL
10k
1
G
R1*
10k
RECT.
5k
2
IN
3
EXPANDOR
4
5
V
REF
BANDGAP
6
V
CC
I
REF
PWRDN
GND
MUTE
7
GND
8
Figure 24. Block Diagram of NE578 Test and Application Circuit
switching operation of the stage. However, care must be taken not
allow the network's time constant to become code dependent as to
the average low frequency signal components or errors will result in
the output signal.
The advantage of this particular circuit is that it has the simplicity of
single supply operation along with the capability of a large output
swing making it fully TTL compatible
REFERENCES:
Philips Semiconductors. Linear Data Manual, Volume 2 : Industrial.
Sunnyvale: 1988.
Wong, Alvin K. Companding with the NE577 and NE578..Philips
Semiconductors Applications Note AN1762 : September 1990.
16
15
30k
30k
10k
14
13
RECT.
10k
8.6k
12
10k
11
G
COMP.
GAINCELL
10
1nF
9
NE578
15
Application note
AN1651
V
CC
COMP
CAP2
C8
+
2.2 F
C7
+
COMP
IN
10 F
COMP
CAP1
+
C6
2.2 F
RECT
IN
R3*
GCELL
IN
+
C5
10 F
+
COMP
OUT
C9
10 F
C11
TO
PIN 4
+
SUM
IN
R4
C10
10 F
SL00652
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