Transmitter System - Vertex Standard VX-2200 Series Service Manual

Circuit Description

3. Transmitter System

3-1. Mic Amplifier
There are two micrphone inputs, J1004 (front) and J1006
(D-Sub). Each microphone inputs has it's own amplifier.
Which micrphone is selected is controlled by the CPU and
in addition, the amplified AF signal is selected with Flat-
AF selection switch Q1043 (LM2902PW). Mic Gain is
adjusted with Mic gain VR Q1014 (M62364PF) through
HPF-AMP Q1043 (LM2902PW), and Pre Enphasis and
Mic Mute Q1044 (SN74LV4066) are passed at FLAT-AF
OFF. And, the option use is selected with OPT selection
switch Q1044 (SN74LV4066) by the control from CPU.
The selected signal enters maximum deviation adjustment
volume Q1014 (M62364FP) after it goes out of Buffer Amp
Q1043 (LM2902PW) through limiter and splatter filter of
Q1040 (LM2902PW). The adjusted low frequency signal
ingredient is amplified by Q1047 (LM2902PW) added
modulation terminal of TCXO (X1002) the FM modula-
tion is made by reference oscillator. The high frequency
signal ingredient is amplified Q1043 (LM2902PW), and
the level is adjusted by volume control Q1014 (M62364FP)
to make frequency balance between low frequency. After
that, the signal is delievered to the tranmsit carrier by
modulator D1023 (HVC383B).
3-2. Drive and Final amplifier
The modulated signal from the VCO Q1031 (2SC3356) is
buffered by Q1027 (2SC5226) and amplified by Q1015
(2SC3357). The low-level transmit signal is then applied
to the Power Module Q1009 (S-AV32) for final amplifica-
tion up to 50 watts output power or Q1009 (S-AV33A) for
final amplification up to 25 watts output power. The trans-
mit signal then passes through a low-pass filter to sup-
press harmonic spurious radiation before delivery to the
antenna.
3-3. Automatic Transmit Power Control
The output power of Power Module is detected by CM
coupler, and is detected by D1008 and D1038 (both
HSM88AS) and is inputted to comparator Q1048
(LM2902PW). The comparetor compares two different
voltages and makes output power stable by controlling
the bias voltage of the power module. There are 3 levels
of output power (High, Low-Hi, and Low-Middle for 50
W model) or 4 levels of output power (High, Low-Hi, Low-
Middle, and E-Low for 25 W model) which is switched
by the voltage of Q1014-CH1 (M62364FP).
3-4. PLL Frequency Synthesizer
The frequency synthesizer consists of PLL IC Q1054
(ADF411BRU) VCO, TCXO (X1002) and buffer amplifier.
The output frequency from TCXO is 16.8 MHz and the
tolerance is ±2.5 ppm (in the temperature range –30 to
+60 degrees).
E-2
3-4-1. VCO
While the radio is receiving, the RX oscillator Q1029
(2SK508) in the VCO generates a programmed frequency
between 201.65 and 241.65 MHz as 1st local signal. While
the radio is transmitting the TX oscillator Q1031
(2SC3356) in the VCO generates a frequency between 134
and 174 MHz. The output from oscillator is amplified by
buffer amplifier Q1027 (2SC5226) and becomes the out-
put of the VCO. The output from VCO is divided one is
amplified by Q1024 (2SC5226) and feed back to pin 6 of
the PLL IC Q1054 (TRF3750IP). The other is amplified in
Q1023 (2SC5226) and in case of the reception it is put
into the mixer as the 1st local signal through D1020
(DAN222) in transmission it is amplified in Q1027
(2SC5226) and more amplified in Q1023 (2SC5226)
through D1022 (DA222) and it is put the input terminal
of the Power Module Q1009 (S-AV32 for 50 W model or
S-AV33A for 25 W model).
3-4-2. VCV CNTL
Tuning voltage (VCV) of the VCO expands the lock range
of VCO by controlling the of varactor diode voltage and
the control voltage from PLL IC Q1054 (ADF4111BRU).
Control voltage is added to the varactor diode after con-
verted to D/A converter Q1029 (M62364FP).
3-4-3. PLL
The PLL IC Q1054 (ADF4111BRU) consists of reference
divider, main divider, phase detector, charge pumps and
Pulse Swallow Frequency Synthesis. The reference fre-
quency from TCXO is inputted to pin 8 of PLL IC Q1054
(ADF4111BRU) and is divided by reference divider. This
IC is decimal point dividing PLL IC Q1054 (ADF4111BRU)
and the dividing ratio becomes 1/8 of usual PLL frequency
step. Therefore, the output of reference divider is 8 times
of frequencies of the channel step. For example when the
channel stepping is 5 kHz, the output of reference divider
becomes 40 kHz. On the other hand, inputted feed back
signal to pin 6 of PLL IC Q1054 (ADF4111BRU) from VCO
is divided with the dividing ratio which becomes same
frequency as the output of reference divider. These two
signals are compared by phase detector, a phase pulse is
generated. The phase difference pulse and the pulse from
fractional accumulator pass through the charge pumps
and LPF. This becomes the DC voltage (VCV) to control
the VCO. The oscillation frequency of VCO is locked by
the control of this DC voltage. The PLL serial data from
CPU Q1065 (CPU: LC87F5CC8A) is sent with three lines
of SDO (pin 12), SCK (pin 11) and PSTB (pin 13). The lock
condition of PLL is output from the UL (pin 14) terminal
and UL becomes "H" at the time of the lock condition
and becomes "L" at the time of the unlocked condition.
The CPU Q1065 (CPU: LC87F5CC8A) always watches
over the UL condition, and when it becomes "L" unlocked
condition, the CPU Q1065 (CPU: LC87F5CC8A) prohib-
its transmitting and receiving.