Character Length; Extended Signaling Rate (Esr); Accessing Internal Switches; Setting Internal Switches - Patton electronics 2011 User Manual

3.0 CONFIGURAT I O N
The Model 2011 is configured using internal DIP switches. Figure 1
shows the location of the Model 2011's configuration switches.
Figure 1. Switch locations on the Model 2011 PC board

3.1 ACCESSING INTERNAL SWITCHES

The Model 2011's DIP switches are mounted on the PC board. To
access the PC board, insert the blade of a small flathead screwdriver
into the slot on one side of the Model 2011's case, then pop the case
open by twisting the blade. Repeat on the other side of the case. You
should now be able to pull the case halves apart and access the DIP
switches on the PC board. Once you have set the switches properly,
align the case halves and snap them together.

3.2 SETTING INTERNAL SWITCHES

Three DIP switches are used to configure the Model 2011: two
switches set the character length and one switch matches the signaling
rates of the asynchronous and synchronous ports. Figure 2 shows the
orientation of the DIP switches.
ON ON
OFF OFF OFF
Figure 2. DIP switch orientation
3
Configuration
Switches
ON ON
OFF

3.2.1 CHARACTER LENGTH

Switches SW1-1 and SW1-2 operate jointly to set the
asynchronous character length. The asynchronous character length
setting is determined by combining the number of start, stop, data and
parity bits that make up each character generated by the asynchronous
DTE. The Model 2011 does not care about the composition of each
asynchronous character, only its length is significant. Below are the
combined switch settings that set the four possible asynchronous
character lengths:
SW 1-1
8 Bit OFF
9 Bit ON
10 Bit OFF*
11 Bit ON

3.2.2 EXTENDED SIGNALING RATE (ESR)

The position of switch SW1-3 ensures that the asynchronous input
data rate matches the synchronous output data rate. When switch
SW1-3 is set to OFF, the asynchronous bit rate must match the
synchronous clock rate to a tolerance of -2.5% to +1%. When switch
SW1-3 is set to ON, the asynchronous bit rate must match the
synchronous clock rate to a tolerance of -2.5% to +2.3%.
SW 1-3
-2.5% to +1% OFF*
-2.5% to +2.3% ON
* Default settings
Note: Switch SW1-4 is not used.
SW 1-2
ON
ON
OFF*
OFF
4