Protection Circuits; Turn-On/Clear Circuit; Input Power Stages - Agilent Technologies 6060B Service Manual

Protection Circuits

The load includes overvoltage (OV), overpower (OP), overcurrent (OC) and overtemperature (OT) protection.
The OV circuit takes control of the input power stages when an overload condition occurs. If the input voltage exceeds 75V,
the overload circuit will cause the input stages to increase current flow in order to limit the input voltage. The OV circuit
does not turn off the input power stages. An OV signal is sent back to the microprocessor to indicate the status of the circuit.
The OV circuit is reset by the microprocessor when a Reset or a Protection Clear command is executed or when power is
cycled.
The OP circuit limits the current drawn by the input power stages when an overpower condition occurs. Once the power has
been returned to a safe operating area, the circuit allows the current to rise again. An OP signal is sent back to the
microprocessor to indicate the status of the circuit. A thermistor, located near the input power heat sinks, provides the
temperature signal (OT) to the microprocessor via the readback DAC as previously described.
The OC circuit limits the load's input current to a value within its rating. The circuit is set at a value slightly above the
current rating of the supply. The circuit is also activated to limit input current when an overpower condition occurs and at
power turn on. In addition, the load allows the user to define a current protection limit in software (see Operating Manual).

Turn-On/Clear Circuit

This circuit ensures that the input stages are held off (non-conducting) when power is initially turned on. After the load's
circuits have stabilized, the input power stages are turned on. This circuit also generates the signal to clear the OV circuit as
described above.

Input Power Stages

There are eight input power stages connected in parallel. Each stage consists mainly of a power FET, an error amplifier, and
an input current monitor amplifier. Each FET is connected across the load's + and - INPUT terminals along with a 15A fuse
and current monitoring resistor. Depending upon the value of the IPROG signal from the CC/CV control circuits and the
value of the input current, the error amplifier in each stage produces an error signal which will cause each FET to increase
or decrease current flow.
The eight input power FET stages are controlled in accordance with the selected mode of operation. In the CC mode, the
input power stages will sink a current in accordance with the programmed value of current regardless of the input voltage. In
the CR mode, the input power stages will sink a current linearly proportional to the input voltage in accordance with the
programmed resistance value. In the CV mode, the input stages will attempt to sink enough current to control the source
voltage to the programmed voltage level.
The UNREG signal, which is sent back to the secondary processor, indicates if the power input stages are unregulated. The
TURN ON signal is held off (low) at power on to prevent the input stages from conducting as previously described.
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