Table of Contents
Advertisement
5790A
Service Manual
The cable from the motherboard to the binding posts consists of three insulated wires and
four shields.
J106 and J206
J110 and J210
J115 and J215
J116 and J216
J117 and J217
J118 and J218
2-10. Rear Panel I/O Assembly (A21)
The Rear Panel I/O assembly provides the RS-232-C and IEEE-488 interface
connections.
2-11. Rear Panel Power Supplies
Supplies 5 V LOGIC, 12 V, and -12 V are referenced to 5 V LOGIC COMMON and
are generated on the Digital Power Supply assembly (A19). Some ICs on the A21
assembly do not have power and ground pins shown on the schematic. This information
is included in the table on sheet 1 of the Rear Panel schematic.
2-12. Rear Panel Digital Control
The Rear Panel decodes address lines from the bus connected to the main CPU through
the connector J121. Decoding is accomplished with C22V10 PLD (U8).
2-13. Clock Regeneration Circuit
In order to minimize EMI (electro-magnetic interference) inside the 5790A chassis, the
rear panel accepts a low-level ( 200 mV p-p sine wave) 3.68 MHz clock from the CPU
assembly and conditions it to proper TTL clock levels.
This is done by a differential amplifier, U18, which amplifies the incoming signals
3.6864MHZCLK and 3.6864MHZCLK*. The output of U18 is a TTL level 3.68 MHz
clock called RP3.68 MHZ that is buffered by PLD U8 creating RPCLK for use by
DUART (dual universal asynchronous receiver/transmitter) U5, and IEEE interface IC
U2.
2-14. IEEE-488 (GPIB) Interface
The IEEE-488 (GPIB) interface circuit provides the interface between the IEEE-488
connector (J1) and the 5790A processor on the CPU (A20) assembly. The circuitry uses a
TMS9914 (U2) General Purpose Interface Bus (GPIB) adapter to meet the requirements
for talker/listener operation on the IEEE-488 bus. This circuit translates asynchronous
8 bit data and control information, under control of an external controller, and converts
this information to an acceptable format for the CPU.
The TMS9914 has internal circuitry which handshakes in the proper GPIB protocol and
stores data in an internal buffer. This IC also has the capability of interrupting the CPU.
The CPU can then handle the interrupt through its own handler routine. The data lines
between U2 and J1 are buffered by a 75160A (U3) data buffer, and the command lines
2-10
Table 2-1. Analog Motherboard Connectors
Motherboard Connector
Connected to Assembly
Wideband ( A6, Option -03)
Transfer (A10)
A/D Amplifier (A15)
DAC (A16)
Regulator/Guard Crossing (A17)
Filter (A18)
Advertisement
Table of Contents
