Sharp DV-SL700W Service Manual page 58

DV-SL700W
IC106, CMOS DRAM 143MHZ 16MB
Pin Configuration:
Pin Description:
PIN
CLK Clock
CKE Clock Enable
Chip Select
CS
Bank Address
BA
Address
A0 ~ A10
Row Address Strobe,
RAS, CAS, WE
Column Address Strobe, Write
Enable
LDQM, UDQM Date Input/Output Mask
DQ0 ~ DQ15 Date Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
NC No Connection
VDD 1
DQ0 2
DQ1 3
VSSQ 4
DQ2 5
DQ3 6
VDDQ 7
DQ4 8
DQ5 9
VSSQ 10
DQ6 11
DQ7 12
VDDQ 13
LDQM 14
/WE 15
/CAS 16
/RAS 17
/CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VDD 25
PIN NAME
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the
stales among power down, suspend or self refresh.
Command input enable or mask except CLK, CKE and DQM.
Select either one of banks during both RAS and CAS activity.
Row Address: RAD ~ RA10, Coiumn Address: CA0 ~ CA7
Auto-precharge flag: A10
RAS, CAS and WE define the operation.
Refer function truth table for details.
DQM control output buffer in read mode and mask input data in write mode.
Multiplexed data input/output pin.
Power supply for internal circuit and input buffer
Power supply for DQ
No connection
50
49
48
47
46
45
44
43
42
41
40
50pin TSOP ll
39
400mil x 825mil
38
0.8mm pin pitch
37
36
35
34
33
32
31
30
29
28
27
26
58
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
DESCRIPTION