Sharp DV-SL700W Service Manual page 55

Symbol
A_DATA[3]/GPIO
A_LRCK/GPIO
VSS_O6/VSS_K6
A_BCK/GPIO
A_BCK/GPIO
UA0_RX/GPIO
UA0_TX/GPIO
V_COMP
V_BIAS
V_FSADJ
V_REFOUT
Pin NO I/O
Serial audio data output for channel 7/6 or GPIO
176 I/O
sft_cfg3[4]=1'b1
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
PCM data output DR strobe
177 I/O
sft_cfg3[6]=1'b1
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
Kernel logic I/O power shard ground supply #6
178 S
PCM bit clock
179 I/O
sft_cfg3[0]=1'b1
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
Audio over-sampling clock
180 I/O
sft_cfg3[9]=1'b1
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
UART #0 data receive or GPIO
181 I/O
sft_cfg2[3:2]=2'b01
sft_cfg3[13:12]=2'b01
sft_cfg4[15:13]=3'b011
(other)
UART #0 data transmit or GPIO
182 I/O
sft_cfg2[3:2]=2'b01
sft_cfg3[13:12]=2'b01
sft_cfg4[15:13]=3'b011
(other)
183 A
(VDAC CBU) Compensation pin. Connect a 0.1pF ceramic capacitor to bypass this
pin to VSSA. The lead length must be kept as short as possible to avoid noise.
184
(VDAC CBL) Bias voltage. Connect a 0.1pF ceramic capacitor to bypass this pin to
VSSA. The lead length must be kept as short as possible to avoid noise.
185 A Full-Scale adjustment control pin. The full-scale current of D/A resistor (Pset)
between this pin and ground.
186 A
(VDAC VREF/bandgap output) Voltage reference output. It generates typical 1.2V
voltage reference and may be used to drive V_REFIN pin directly.
Description
Priority selection
Priority selection
Priority selection
Priority selection
Priority selection
Priority selection
55
Function
A_DATA[3] (default)
ADC_MONO_SPGA
DAG_TEST
GPIO[56]
Function
A_LRCK (default)
ADC_MONO_MODE1
DAC_UD
GPIO[57]
Function
A_BCK (default)
ADC_MONO_MODE1_1
DAC_BGPD
GPIO[58]
Function
A_XCK (default)
ADC_MONO_MODE2
DAC_CLK
GPIO[59]
Function
UART0_RX (default)
TV_HSYNC
HSYNC_PC
GPIO[60]
Function
UART0_TX (default)
TV_HSYNC
HSYNC_PC
GPIO[61]
DV-SL700W
Dir
O
I
I
I/O
Dir
I/O
I
I
I/O
Dir
I/O
I
I
I/O
Dir
I/O
I
I
I/O
Dir
I
I/O
O
I/O
Dir
O
I/O
O
I/O