Pin
I Signa,
Name
Ivol
90
FGREF
I
91
FGIN
I
92
PGREF
I
93
PGIN
I
77
76
84
81
EMU0
IIO/Z
EMU1
I/O/Z
TRST
I
TMS
I
78
TDO
O/Z
80
TDI
I
79
TCK
I/O
95
94
CLKOUT1
O
RS
I
Type
FG/PG counter
TTL
(Hysteresis)
65
66
31
16,55.
67,83
97
6,15,
54,64,
82,85-
87,961
X2/CLKIN
I
Xl
O
TESTA
O
DVcc
DGNO
TTL
(Hysteresis)
TTL
(Hysteresis)
TTL
(Hysteresis)
JTAG
TTL
(Internal pull-up)
TTL
(Internal pull-up)
TTL
(Internal
pull-up)
TTL
(Internal
pull-up)
TTL
TTL
(Internal pull-up)
TTL
(Internal pull-up)
Function
FG counter reference pulse signal input. The polarity
of the input can also be checked
by the host output
register (bit 10).
FG pulse signal input. The polarity
of the input can
also be checked
by the host output register (bit 9).
PG counter reference
pulse signal input.
PGpulse
signal input.
pin
Emulator pin 0
Emulator
pin 1
JTAG test reset pin
JTAG test mode select pin
JTAG test data output pin
JTAG test data input pin
JTAG test clock
Other signal pins
Master clock output signal
Reset input
COMS
TTL
(Internal pull-up)
Oscillator
Oscillator
Internal oscillator
input/clock
input
Internal oscillator
output
-
Reserved
pin. Use without connecting.
Power supply pin
-
+5V supply pin for digital circuit.
-
Ground pin for digital circuit.
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