Epson LQ-2550 Technical Manual page 96

8-bit Parallel Inteface Circuit
Figure 2-43 shows the 8-bit parallel interface circuit.
This circuit is controlled by the main CPU.
Address mapping for the M546 10P ( 11 B) is performed by the main CPU via the MMU (14A). General
purpose 8-bit parallel interface IC M546 10P ( 11 B) is employed to simplify the control required from
the main CPU.
The latch circuit ( 14C) converts the control data in the main CPU into an 8-bit parallel interface signal
(PE, ERROR, and BUSY) according to the select signal (MMI02) from the MMU.
The SLCTIN and AUTO FEED XT signals are fixed signals from the host computer, read into the sub
CPU as default values, and transferred to the main CPU.
Refer to Appendix A.1.l .10 for the details of the M546 10P.
EXTERNAL
,
INIT
B
U S Y
ACKNLG
I
DIN l-~
R126
STROBE
C51
ERROR
BO 1
PE
Figures 2-44 and 2-45 show the processing sequence for these signals and the interface signal timing.
Table 2-33 shows the control signals used between the printer and host computer.
M54610P(1 1 El)
— T
R R
I I iii
I
la la
\
Figure 2-43. 8-Bit Parellel Interface Circuit
R87
I
RDY
— .
BSYF
BSSL
ACKI
1
I 1
I
I
I I
I
\\
— IQ
Psw
2D u
30 3D 0
— 40 4D
CLK
I
2-49
CONTROL
READY LED pANEL
I
MAIN CPU
I
I l l
II JAI
DO- D 7
/
(1 4A)
'
PORTO