Epson LQ-2550 Technical Manual page 256

Memory Write Timing
c )
The memory write timing consists of three states, T1 to T3.
Timings for address output and the ALE signal are the same as those for the memory read machine
cycle, however, AD7 to O (PD7 to O) are not disabled after the memory address is output, and write
data is output on AD7 to O from the beginning of T2 to the end of T3. The WR signal is output from
the middle of T1 to the beginning of T3.
AB15 -8
NOTE: When PD7 to O and PF7 to O are output to the mautiplexed address/data bus (AD7 to O) and
address bus (AB 15 to 7), both the ~ and WR signals during the machine cycle are HIGH when
external memory is not being accessed.
CLOCK
x
ADDRESS
Figure A-9. Memory Write Timing
ADDRESS
x x
WRITE DATA
A-1 1
REV.-A
x
x