Epson LQ-2550 Technical Manual page 128

REV.-A
2.3.7 CR and PF Motors Control/Drive Circuit
Figure 2-77 shows the CR and PF motors controVdrive circuit block diagram. The CR and PF motors
are controlled by the sub CPU (7 B). The stepper motor control gate array IC (M CU:4B) is memory-mapped
into the address space of the sub CPU, allowing the stepper motor to be controlled by address selection
motor is generated by a timer in the sub CPU. The TM 1 clock is output to the MMU via the TM 1 clock
generation circuit, and the TM2 clock is directly output to the MMU (TM 1
PF motor phase switching pulse generation, respectively). Based on these clocks, the MCU
motorand
generates CR and PF motor phase switching pulses, drives stepper motor drivers IC S17304 (7C: CR
motor) and STK698 1 H (7D: PF
a reference voltage that corresponds to the motor speed for the constant current control drive IC. The
CR and PF motor constant current control is based on the reference voltage.
SURGE
VOLTAGE
CIRCUIT I
+5
t
1 1 + UH_l
SURGE
VOLTAGE
C I R C U I T ~ GH
P
SURGE
VOLTAGE
CIRCUIT
+ 5
t
PF MOTOR
PF
DRIVER
MOTOR
(7 D)
Figure 2-77. CR and PF Motors Control
motor), and rotates the
+35
4
PHASE PULSES
+ 3 5
A
PHASE PULSES
+5
I
REFERENCE
VOLTAGE
ENABLE
(
CR
and PF motors. These motor driver ICS input
I
AO1
1
DO1
1
2
ADO
1
3
TM 1
(4 B)
SCK
A 0 2 —
1 RCK
D02
Circuit Block Diagram
2-82
and TM2 are for the CR
RESET
CIRCUIT