Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz Specification
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Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz Specification

Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz Specification

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SAI2 Server Board
Technical Product Specification
Revision 1.0
November 2001
Enterprise Platforms and Services Marketing

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Summary of Contents for Intel SAI2 - Ss3/le Dual Fcpga Max-4GB Atx2pci-64 4pci-32 Vid Lan 133mhz

  • Page 1 SAI2 Server Board Technical Product Specification Revision 1.0 November 2001 Enterprise Platforms and Services Marketing...

  • Page 2: Revision History

    Revision History SAI2 Server Board TPS Revision History Date Revision Modifications Number November 2001 Initial Release. Revision 1.0...
  • Page 3 Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 4: Table Of Contents

    Audience ........................1 SAI2 Server Board Feature Overview................1 SAI2 Server Board Block Diagram ................2 2. SAI2 Server Board Architecture Overview ............... 3 Intel® Pentium® III Processor Subsystem..............3 2.1.1 Supported Processor Types ..................3 2.1.2 Dual Processor Operation..................3 2.1.3...
  • Page 5 SAI2 Server Board TPS Table of Contents BIOS Overview......................19 3.1.1 System BIOS ......................20 3.1.2 Flash Update Utility....................20 Setup Utility ......................... 21 3.2.1 Configuration Utilities Overview ................21 3.2.2 Setup Utility Operation ................... 21 CMOS Memory Definition.................... 32 CMOS Default Override....................
  • Page 6 Table of Contents SAI2 Server Board TPS 4.3.12 USB Connectors (J2) ................... 53 4.3.13 IDE Connectors (PRI_IDE, SEC_IDE) ..............53 4.3.14 32-Bit PCI Connectors ..................54 4.3.15 64-Bit PCI Connectors ..................55 4.3.16 Front Panel 24-pin Connector Pinout (FRONT_PANEL_HDR)......56 5.
  • Page 7 SAI2 Server Board TPS List of Figures List of Figures Figure 1. SAI2 Server Board Block Diagram ................2 Figure 2. Embedded NIC PCI Signals ..................7 Figure 3. Video Controller PCI Signals ..................9 Figure 4. SAI2 Baseboard Interrupt Routing Diagram (PIC Mode) ........... 15 Figure 5.
  • Page 8 List of Tables SAI2 Server Board TPS List of Tables Table 1. SAI2 Server Board Supported Processors ..............3 Table 2. Video Controller Supported PCI Commands ..............9 Table 3. Standard VGA Modes....................10 Table 4. SAI2 PCI IDs ......................17 Table 5.
  • Page 9 SAI2 Server Board TPS List of Tables Table 32. Jumper Block JP5 Settings..................47 Table 33. Main Power Connector Pinout .................. 49 Table 34. I C Connector Pinout ....................49 Table 35. Board Fan Connector Pinout ..................50 Table 36. Processor Fan Connector Pinout................50 Table 37.
  • Page 10 List of Tables SAI2 Server Board TPS < This page intentionally left blank. > Revision 1.0...

  • Page 11: Introduction

    The SAI2 server board provides the following features: Dual Intel® Pentium® III processor support Support for one or two identical Intel Pentium III processors for the PGA370 socket, which utilizes the Flip Chip Pin Grid Array (FC-PGA) package Two embedded Voltage Regulating Modules (VRM) for support of both primary and...

  • Page 12: Sai2 Server Board Block Diagram

    Introduction SAI2 Server Board TPS Compatibility bus segment with two embedded devices Super I/O Controller (PC87417) that provides all PC-compatible I/O (floppy, parallel, serial, keyboard, mouse, and Real-Time Clock) 4 megabit Flash device for system BIOS Dual Universal Serial Bus (USB) ports Two IDE connectors Flash BIOS support for all of the above ATX board form factor...

  • Page 13: Sai2 Server Board Architecture Overview

    Chipset support components Intel® Pentium® III Processor Subsystem The SAI2 server board is designed to accommodate one or two Intel Pentium III processors for the PGA370 socket. The Pentium III processor for the PGA370 socket uses the same core and offers the same performance as the Intel Pentium III processor for the SC242 connector, but utilizes a FC-PGA.

  • Page 14: Pga370 Socket

    APICs in each processor and the I/O APIC located in the CSB5 South Bridge component. 2.1.6 Boxed Processors The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from a server board and standard components. 2.1.6.1...

  • Page 15: Serverworks Serverset Iii Le Chipset

    Empty memory slots between DIMMs are not supported. Although the SAI2 server board architecture allows the user to mix various sizes of DIMMS, Intel recommends that module and DRAM vendors not be mixed in the same server system.

  • Page 16: Pci I/O Subsystem

    The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connectors: Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots ® Integrated Intel EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller (Intel® 82559) Integrated ATI Rage* XL video controller with 8 MB of on-board SGRAM CSB5 South Bridge I/O APIC, PCI-to- Industry Standard Architecture (ISA) bridge, IDE controller, USB controller, and power management.

  • Page 17: Figure 2. Embedded Nic Pci Signals

    2.4.2.1 Network Interface Controller (NIC) The SAI2 server board includes a 10Base-T / 100Base-TX network controller that is based on ® the Intel 82559 Fast Ethernet PCI Bus Controller. This device is similar in architecture to its ® predecessor (Intel 82558).
  • Page 18 SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.4.2.1.1 Supported Network Features The 82559 contains an IEEE MII compliant interface to the components necessary to implement an IEEE 802.3 100Base TX network connection. The SAI2 supports the following features of the 82559 controller: Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus Specification, revision 2.1 / 2.2 Chained memory structure, with improved dynamic transmit chaining for enhanced...

  • Page 19: Figure 3. Video Controller Pci Signals

    SAI2 Server Board TPS SAI2 Server Board Architecture Overview AD[31::0] C/BE[3::0]_L FRAME_L TRDY_L IRDY_L STOP_L DEVSEL_L Rage XL IDSEL PCI_CLK RST_L PERR_L SERR_L PCI_INT_L Figure 3. Video Controller PCI Signals 2.4.2.2.2 Video Controller PCI Commands The Rage XL supports the following PCI commands: Table 2.

  • Page 20: Table 3. Standard Vga Modes

    SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.4.2.2.3 Video Modes The Rage XL supports all standard IBM* VGA modes. The following tables show the standard resolutions that this implementation supports, including the number of colors and the refresh rate. Table 3.
  • Page 21 SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.4.2.3.1 PCI Interface The CSB5 South Bridge fully implements a 32-bit PCI master/slave interface, in accordance with Revision 2.2 of the PCI Local Bus Specification. On the SAI2 server board, the PCI interface operates at 33 MHz, using the 5V-signaling environment.

  • Page 22: Chipset Support Components

    SAI2 Server Board Architecture Overview SAI2 Server Board TPS Chipset Support Components 2.5.1 Legacy I/O (Super I/O) National* PC87417 The National* PC87417 Super I/O Plug-and-Play Compatible with ACPI-Compliant Controller/Extender is used on the SAI2 server board. This device provides the system with: Real-time Clock (RTC) Two serial ports One parallel port...

  • Page 23: Bios Flash

    SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.5.1.5 Real-time Clock The PC87417 contains an MC146818-compatible real-time clock with external battery backup. The device also contains 242 bytes of general purpose battery-backed CMOS RAM. The real- time clock provides system clock and calendar information stored in non-volatile memory. 2.5.1.6 Plug-and-Play Functions / ISA Data Transfers The PC87417 contains all signals for ISA compatible interrupts and DMA channels.

  • Page 24: Default I/O Apic

    SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.6.1 Default I/O APIC The CSB5 South Bridge integrates a 16-entry I/O APIC which is used to distribute 16 PCI interrupts. 2.6.2 Extended I/O APIC An additional 16-entry I/O APIC is integrated in the CSB5 South Bridge to distribute EISA/ISA interrupts.

  • Page 25: Figure 4. Sai2 Baseboard Interrupt Routing Diagram (Pic Mode)

    SAI2 Server Board TPS SAI2 Server Board Architecture Overview CSB5 PC87417 IRQ 0 (Super-I/O) Keyboard IRQ 1 IRQ 2 Serial Port2 IRQ 3 Serial Port1 IRQ 4 IRQ 5 IRQ 6 IRQ 7 Parallel Port IRQ #8 IRQ 9 IRQ 10 IRQ 11 Mouse IRQ 12...

  • Page 26: Figure 5. Sai2 Baseboard Interrupt Routing Diagram (Symmetric Mode)

    SAI2 Server Board Architecture Overview SAI2 Server Board TPS The SAI2 system interrupt routing is as follows: CSB5 Timer IRQ 0 Keyboard IRQ 1 Cascade IRQ 2 IRQ 3 Serial Port2 IRQ 4 Serial Port1 IRQ 5 IRQ 6 Parallel Port IRQ 7 IRQ #8 IRQ 9...

  • Page 27: Pci Ids

    Device Bus Number [23:16] Device Number [15:11] Slot ID Signal CNB30LE 0000 0b ATI* Rage XL 0001 0b P32_AD18 Intel 82559 0001 1b P32_AD19 PCI Slot 1 (32bit) 0011 0b P32_AD22 PCI Slot 2 (32bit) 0011 1b P32_AD23 PCI Slot 5 (32bit)

  • Page 28: Acpi

    SAI2 Server Board Architecture Overview SAI2 Server Board TPS ACPI The Advance Configuration and Power Interface (ACPI)-aware operating system can place the system into a state where the hard drives spin down, the system fans stop, and all processing is halted.

  • Page 29: Basic Input Output System (Bios)

    Basic Input Output System (BIOS) This section describes BIOS embedded software for the SAI2 board set. The BIOS contains ® standard PC-compatible basic input/output (I/O) services, standard Intel server features, plus the SAI2 system-specific hardware configuration routines and register default settings, embedded in Flash read-only memory (ROM).

  • Page 30: System Bios

    The flash ROM contains system initialization routines, BIOS strings, BIOS Setup, and run-time support routines. The exact layout is subject to change, as determined by Intel. A 16-KB user block is available for user ROM code and another 128-KB block is available for custom logos.

  • Page 31: Setup Utility

    SAI2 Server Board TPS Basic Input Output System (BIOS) Setup Utility This section describes the ROM resident setup utility that provides the means to configure the platform. The setup utility is part of the system BIOS and allows limited control over on-board resources such as the parallel port and mouse.
  • Page 32 Basic Input Output System (BIOS) SAI2 Server Board TPS After the F2 key is pressed, a few seconds might pass before Setup is entered while POST finishes test and initialization functions that must be completed before Setup can be entered. When Setup is entered, the Main Menu options page is displayed.

  • Page 33: Table 7. Main Menu Selections

    SAI2 Server Board TPS Basic Input Output System (BIOS) pressed, the user is returned to where s/he was before the F9 key was pressed, without affecting any existing values. Save and Exit Pressing F10 causes the following message to appear: Setup Confirmation Save Configuration changes and exit now? [Yes] [NO]...

  • Page 34: Table 8. Primary/Secondary Master And Slave Adapters Submenu Selections

    Basic Input Output System (BIOS) SAI2 Server Board TPS Feature Choices or Display Description User Only Setting System Date MM/DD/YYYY Sets the system date (month, day, year). Diskette A Not Installed Selects the diskette type. 1.2 MB 5 ¼” Note: 1.25-MB, 3.5-inch references a 1024-byte/sector Japanese media format.

  • Page 35: Table 9. Advanced Menu Selections

    SAI2 Server Board TPS Basic Input Output System (BIOS) Feature Choices or Display Only Description User Setting 32 Bit I/O Enable/Disable 32-Bit IDE data transfers Disabled Enabled Transfer Mode Select the method of moving data to and from the hard Standard drive.

  • Page 36: Table 11. Memory Reconfiguration Submenu Selections

    Basic Input Output System (BIOS) SAI2 Server Board TPS Table 11. Memory Reconfiguration Submenu Selections Feature Choices or Display Only Description User Setting DIMM Group #1 Status Display only: Normal None Error (DIMM Row Error) DIMM Group #2 Status Display only: Normal None Error (DIMM Row Error)

  • Page 37: Table 13. Peripheral Configuration Submenu Selections

    SAI2 Server Board TPS Basic Input Output System (BIOS) Table 13. Peripheral Configuration Submenu Selections Feature Choices or Description User Display Only Setting Serial Port 1: (COM 1) Disabled Disables serial port 1 or selects the base address and interrupt (IRQ) for serial port 1. 3F8, IRQ3 3F8, IRQ4 2F8, IRQ3...

  • Page 38: Table 14. Pci Device Submenu Selections

    Basic Input Output System (BIOS) SAI2 Server Board TPS Feature Choices or Description User Display Only Setting USB Controller Disabled Enables/Disables on-board USB controller. Enabled IDE Controller Disabled Enables the integrated local bus IDE adapter. Primary Secondary Both Table 14. PCI Device Submenu Selections Feature Choices or Display Description...

  • Page 39: Table 16. Numlock Submenu Selections

    SAI2 Server Board TPS Basic Input Output System (BIOS) Table 16. Numlock Submenu Selections Feature Choices or Description User Display Only Setting Numlock Auto Selects the power-on state for Numlock. Key Click Disabled Disables or enables keyclick. Enabled Keyboard Auto-repeat Rate 2-second Selects key repeat rate.

  • Page 40: Table 18. Secure Mode Submenu Selections

    Basic Input Output System (BIOS) SAI2 Server Board TPS Floppy Write Protect Write protects Floppy drive. Disabled Enabled Fixed Disk Boot Sector Normal Write protects boot sector on hard disk. Write Protect Secure Mode See the Secure Mode Submenu below. Submenu can only be entered if supervisor and user password is set.

  • Page 41: Table 20. Wake On Events Submenu Selections

    Attempts to boot from an ATAPI CD-ROM drive. Removable Devices Attempts to boot from a removable device. Hard Drive Attempts to boot from a hard drive device. Intel® Boot Agent Version 4.0.17 Attempts to boot from a PXE server. Table 22. Hard Drive Selections Boot Priority Device...

  • Page 42: Cmos Memory Definition

    Basic Input Output System (BIOS) SAI2 Server Board TPS Table 23. Removable Devices Selections Boot Priority Device Description User Setting Legacy Floppy Drives Select the order in which each removable device is attempted to be used as the boot device. 1 Note: These selections will change depending on the system configuration 3.2.2.9...

  • Page 43: Flash Update Utility

    SAI2 Server Board TPS Basic Input Output System (BIOS) Flash Update Utility The BIOS update utility (Phoenix* Phlash.exe) loads a fresh copy of the BIOS into flash ROM. The loaded code and data include the following: On-board video BIOS and network controller BIOS BIOS Setup utility User-definable flash area (user binary area) Splash screen...

  • Page 44: Customization

    At several points throughout POST, control is passed to this user binary. Intel provides tools and reference code to help dealers create a user binary. The user binary must adhere to...
  • Page 45 SAI2 Server Board TPS Basic Input Output System (BIOS) configuration). If user binary code is required at run time, it is copied into and executed from option ROM space (0C8000H – 0E7fffH). At each scan-point during POST, the system BIOS determines if the scan-point has a corresponding user binary entry point to transfer control to the user binary.

  • Page 46: Table 25. User Binary Area Scan Point Definitions

    Basic Input Output System (BIOS) SAI2 Server Board TPS ; 5 Bytes must be used for each Start ; JMP to maintain proper offset for ; each entry. Unused entry JMP’s ; should be filled with 5 byte ; filler or JMP to a RETF ErrRet ErrRet ErrRet...

  • Page 47: Language Area

    The alternative logo must fit within 640 X 480 size. If an alternative logo is flashed into the system, it will override the built in Intel logo. Intel supplies utilities that will compress and convert a 16 color bitmap file into a logo file suitable for Phoenix Phlash.

  • Page 48: Error Messages And Error Codes

    Basic Input Output System (BIOS) SAI2 Server Board TPS Error Messages and Error Codes The system BIOS displays error messages on the video screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS displays POST error codes on the video monitor.
  • Page 49 SAI2 Server Board TPS Basic Input Output System (BIOS) Beeps Reason Initialize caches to initial POST values Initialize I/O Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore processor control word during warm boot Initialize keyboard controller 1-2-2-3 BIOS ROM checksum...
  • Page 50 Basic Input Output System (BIOS) SAI2 Server Board TPS Beeps Reason Display prompt "Press F2 to enter SETUP" Test RAM between 512 and 640 k Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers Enable external and processor caches Display external cache size Load custom defaults if required...

  • Page 51: Table 29. Recovery Bios Port-80 Codes

    SAI2 Server Board TPS Basic Input Output System (BIOS) Beeps Reason One short beep before boot Display MultiBoot menu Check password, password is checked before option ROM scan ACPI initialization Clear global descriptor table Clear parity checkers Clear screen (optional) Check virus and backup reminders Try to boot with INT 19 Forced shutdown...

  • Page 52: Post Error Codes And Messages

    Basic Input Output System (BIOS) SAI2 Server Board TPS Boot mini DOS Boot full DOS 3.6.2 POST Error Codes and Messages The following table defines POST error codes and their associated messages. The BIOS prompts the user to press a key in case of a serious error. Some error messages are preceded by the string "Error”...

  • Page 53: Table 31. Post Error Conditions And Beep Codes

    SAI2 Server Board TPS Basic Input Output System (BIOS) Code Error Message Failure Description 0B61: DIMM #2 has been disabled Memory error, memory group #2 failed 0B62: DIMM #3 has been disabled Memory error, memory group #3 failed 0B63: DIMM #4 has been disabled Memory error, memory group #4 failed 0B6F: DIMM with error is enabled...

  • Page 54: Identifying Bios Revision Level

    Basic Input Output System (BIOS) SAI2 Server Board TPS Beeps Error Cause Recommended Action 2-3-1-3 All Memory Group Errors Memory address signal failure Change DIMM or M/B 3-3-1-4 Memory Not Detected — — Option ROM Initialization Error Failure to initialize Option ROM Change system board or option BIOS board...

  • Page 55: Jumpers And Connectors

    SAI2 Server Board TPS Jumpers and Connectors Jumpers and Connectors SAI2 Server Board Jumper and Connector Locations The following figure shows the location of the jumper blocks and connectors on the SAI2 Server board. OM13065 Figure 6. SAI2 Server Board Jumper and Connector Locations 33 MHz/32-bit PCI connectors Secondary processor heat sink fan connector (J9) 66 MHz/64-bit PCI connectors...

  • Page 56: Figure 7. I/O Back Panel Connectors

    Jumpers and Connectors SAI2 Server Board TPS The following diagram shows the location of the connectors on the SAI2 server board I/O panel. OM12377 Figure 7. I/O Back Panel Connectors Serial port 1 connector (COM1) Mouse connector Serial port 2 connector (COM2) SVGA connector NMI (Non Maskable Interrupt) switch Network connector...

  • Page 57: Jumper Blocks

    SAI2 Server Board TPS Jumpers and Connectors Jumper Blocks Jumpers on the JP5 jumper block of the SAI2 server board set the system configuration. The jumpers are small plastic-encased conductors (shorting plugs) that slip over two jumper pins on a jumper block. On the SAI2 server board, the following jumper blocks are user-configurable.
  • Page 58 Perfoming a BIOS Recovery Boot In the event of BIOS corruption, the following procedure may be used to perform a BIOS recovery. 1. Obtain the BIOS update file package from Intel’s http://support.intel.com web site. 2. A file called “crisis.zip” is one of the files included with each SAI2 BIOS release file package.

  • Page 59: Connectors

    SAI2 Server Board TPS Jumpers and Connectors 8. Insert the BIOS recovery floppy diskette into the diskette drive. 9. Reinstall the chassis panel, plug in the power cord(s), and power on the system. 10. The screen will remain blank while the BIOS recovery is performed. A number of beeps will occur during the BIOS update.

  • Page 60: System Fan Connectors (J8, J11, J7, J14)

    Jumpers and Connectors SAI2 Server Board TPS 4.3.3 System Fan Connectors (J8, J11, J7, J14) System Fan 3: Fan 3 (J8) System Fan 4: Fan 4 (J11) System Fan 5: Fan 5 (J7) System Fan 6: Fan 6 (J14) Table 35. Board Fan Connector Pinout Signal Fan Sense 4.3.4...

  • Page 61: Diskette Drive Connector (Fdd)

    SAI2 Server Board TPS Jumpers and Connectors 4.3.6 Diskette Drive Connector (FDD) Table 38. Diskette Drive Connector Pinout Signal Diskette Drive Connector Pin Diagram Signal FD_DENSEL No Connection Reserved Removed FD_INDEX_L FD_MON0_L FD_SEL1_L FD_SEL0_L FD_MON1_L FD_DIR_L FD_STEP_L FD_WDATA_L FD_WGATE_L FD_TRK0_L FD_WPT_L FD_RDATA_L FD_SIDE_L...

  • Page 62: Keyboard (Kb) And Mouse (Ms) Connectors

    Jumpers and Connectors SAI2 Server Board TPS 4.3.8 Keyboard (KB) and Mouse (MS) Connectors The keyboard and mouse connectors are functionally equivalent. Table 40. Keyboard and Mouse Connector Pinout Keyboard Signal Mouse Signal KEYDAT MSEDAT FUSED_VCC (+5 V) FUSED_VCC (+5 V) KEYCLK MSECLK 4.3.9...

  • Page 63: Lan Connector (J2)

    SAI2 Server Board TPS Jumpers and Connectors 4.3.11 RJ-45 LAN Connector (J2) Table 43. RJ-45 LAN Connector Signals Signal Description Transmit data plus—the positive signal for the TD differential pair contains the serial output data stream transmitted onto the network Transmit data minus—the negative signal for the TD differential pair contains the same output as pin 1 Receive data plus—the positive signal for the RD differential pair contains the serial input data...

  • Page 64: 32-Bit Pci Connectors

    Jumpers and Connectors SAI2 Server Board TPS DD15 Keyed IDEDRQ DIOW_L DIOR_L IORDY SPSYNC IDEDAK_L IDEIRQ No Connection IDESA1 P80_IDE IDESA0 IDESA2 IDECS0_L IDECS1_L HD_LED 4.3.14 32-Bit PCI Connectors Table 46. 32-Bit PCI Connector Pinout Signal Signal Signal Signal TRST_L -12 V AD16 AD17...

  • Page 65: 64-Bit Pci Connectors

    SAI2 Server Board TPS Jumpers and Connectors AD22 +3.3 V +3.3 V AD20 AD21 REQ64_L ACK64_L AD19 +5 V +5 V AD18 +3.3 V +5 V +5 V 4.3.15 64-Bit PCI Connectors Table 47. 64-Bit PCI Connctor Pinout Signal Signal Signal Signal TRST_L...

  • Page 66: Front Panel 24-Pin Connector Pinout (Front_Panel_Hdr)

    Jumpers and Connectors SAI2 Server Board TPS Signal Signal Signal Signal TRDY_L +3.3 V AD42 AD43 DEVSEL_L +3.3 V AD41 STOP_L AD40 +3.3 V LOCK_L AD38 AD39 SDONE PERR_L AD37 SBO_L +3.3 V AD36 +3.3 V SERR_L AD34 AD35 PARITY +3.3 V AD33 AD15...

  • Page 67: Hardware Monitoring

    Monitors chassis ambient temperature. Winbond Hardware Doctor software and a white paper that provides more information on using Winbond Hardware Doctor software are available on the Intel Server Board SAI2 Resource CD and are also available for download at: http://www.support.intel.com/support/motherboards/server/SAI2...
  • Page 68 Hardware Monitoring SAI2 Server Board TPS ® Below is a diagram explaining what the Winbond Heceta chip monitors on the Intel SAI2 server board and how the monitoring is accomplished. W83782D PKG Temperature Temperature Sensor (Index 27h) Temperature Sensor 2 High Byte (Index 50h, Bank 1)

  • Page 69: Baseboard Specifications

    SAI2 Server Board TPS Baseboard Specifications Baseboard Specifications This chapter specifies the operational parameters and physical characteristics for the SAI2 server board. This is a board-level specification only. System specifications are beyond the scope of this document. Estimated Baseboard MTBF The table below shows the estimated MTBF (Mean Time Between Failures) calculated numbers for the SAI2 server board and the SAI2 server board with the SC5100 chassis.

  • Page 70: Absolute Maximum Ratings

    Baseboard Specifications SAI2 Server Board TPS Absolute Maximum Ratings Operation of the SAI2 server board at conditions beyond those shown in the following table may cause permanent damage to the system (provided for stress testing only). Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 50.

  • Page 71: Measured Power Consumption

    SAI2 Server Board TPS Baseboard Specifications Device(s) 3.3 V +5 V +12 V -12 V 5-V Standby Total Fans (Four chassis and two 1.94 processor) 14.2 2.24 43.48 Total Current Total Power 46.86 26.88 213.64 The total power calculation assumes a system configuration containing dual Pentium® III 1.26GHz processors, four 1-GB DIMMs, all PCI slots containing 10-W cards, two USB devices, keyboard and mouse, four chassis fans, and two processor fan heat sinks.

  • Page 72: Regulatory And Integration Information

    The SAI2 server board has been tested and verified to comply with the following EMC regulations when installed in a compatible Intel host system. For information on Intel compatible host system(s), refer to Intel’s Server Builder website, or contact your local Intel representative.

  • Page 73: Installation Instructions

    UL Joint Recognition Mark: Consists of small c (for Canada) followed by a stylized backward UR and followed by a small US (USA) (on component side). Intel’s UL File Number E139761 (Component side). Battery “+” marking: located on the component side of the board in close proximity to the battery holder.

  • Page 74: Prevent Power Supply Overload

    Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum 5-Amp fuse or positive temperature coefficient (PTC) resistor. This Intel server board has PTCs on all external ports that provide DC power externally.

  • Page 75: Use Only For Intended Applications

    SAI2 Server Board TPS Regulatory and Integration Information 7.2.5 Use Only for Intended Applications This product was evaluated for use in ITE computers that will be installed in offices, schools, computer rooms and similar locations. The suitability of this product for other product categories other than ITE applications, (such as medical, industrial, alarm systems, and test equipment) may require further evaluation.
  • Page 76 Regulatory and Integration Information SAI2 Server Board TPS This page intentionally left blank Revision 1.0...

  • Page 77: Glossary

    Acronyms are then entered in their respective place, with non-acronyms following. Term Definition ACPI Advanced Configuration and Power Interface Advanced Programmable Interrupt APIC Intel Advanced Programmable Interrupt Controller Binary Data Area BIOS Basic Input Output System CMOS Complementary Metal-Oxide Semi-Conductor DIMM...
  • Page 78 Glossary SAI2 Server Board TPS Term Definition Original Equipment Manufacturer Operating System Peripheral Component Interconnect Programmable Interrupt Controller Programmed Input/Output Plug-and-Play POST Power On Self Test Positive Temperature Coefficient Preboot Execution Environment Random Access Memory RAMDAC Random Access Memory Digital-to-Analog Converter Read Only Memory Real Time Clock A communications abbreviation for receive.

  • Page 79: Reference Documents

    Advanced Configuration and Power Interface Specification, Revision 1.0 ATI Rage XL Technical Reference Manual. C Bus Specification.  Intel 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet. PCI Local Bus Specification, Revision 2.2. ServerWorks ServerSet* III LE North Bridge Specification. ServerWorks ServerSet* III LE South Bridge Specification.

  • Page 80: Index

    Index SAI2 Server Board TPS Index Boot Menu, 21, 23, 31 Bridge, 5 Burst transfers, 6 Bus speed, 6 32-bit PCI connector pinout, 54 Certification, 63 Chained memory structure, 8 64-bit PCI connctor pinout, 55 Checksum error, 37 CMOS, 12, 13, 19, 20, 21, 34, 35, 49 CMOS clear, 32, 47, 48 CMOS clear jumper, 21 CMOS map, 32...
  • Page 81 ® Intel 82559, 1, 6, 7, 8, 17 Parallel port connector pinout, 52 Intel® Celeron™ processor, 3 Password Intel® EtherExpress™ PRO100+, 1, 6 Change, 47 Interrupt Acknowledge, 9 Disable jumper, 47 Interrupt generation, 4 Password Clear, 47 Interrupt handling, 3, 11...
  • Page 82 Index SAI2 Server Board TPS Remote power-on, 18 RJ-45 LAN connector signals, 53 RTC, 12, 18, 35 termination circuitry, 4 Transfer Mode, 25 TX magnetics, 8 S0 sleep state, 18 S1 sleep state, 11, 18 S4 sleep state, 11, 18 Ultra DMA Mode, 11 S5 sleep state, 11, 18 Universal Serial Bus, 60...

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