Table of Contents
Advertisement
PowerEdge T710 Technical Guidebook
•
I2C access to SPD EEPROM for access to RDIMM thermal sensors
•
Single Bit Error Correction
•
SDDC (Single Device Data Correction – x4 or x8 devices)
•
Support for Closed Loop Thermal Management
•
Multi Bit Error Detection
•
Support for Memory Optimized Mode
•
Support for Memory Mirroring
•
Support for Independent channel mode
9.6
Memory Population
Across CPU sockets, DIMM populations can be different as long as the population rules for each socket
are followed. Additionally, both CPU sockets operate in the same RAS mode and are set up with the
same memory timing parameters.
•
If DIMMs of different speeds are mixed, all channels operate at the fastest common frequency.
•
RDIMMs and UDIMMs cannot be mixed.
•
The first DIMM slot in each channel is color-coded with white ejection tabs for ease of
identification.
•
The first DIMM slot in each channel is color-coded with white ejection tabs for ease of
installation.
•
The DIMM sockets are placed 450 mils (11.43 mm) apart, center-to-center in order to provide
enough space for sufficient airflow to cool stacked DIMMs.
•
The T710 memory subsystem supports up to 18 DIMMs. DIMMs must be installed in each
channel starting with the DIMM farthest from the processor. Population order will be identified by
the silkscreen designator and the System Information Label (SIL) located on the chassis cover.
See the figure below for DIMM naming and numbering.
Memory Optimized (Independent): {1, 2, 3}, {4, 5, 6}, {7, 8, 9}
o
Advanced ECC (Lockstep) or Mirrored: {2,3}, {5, 6}, {8, 9}
o
Quad Rank or UDIMM: {1, 2, 3}, {4, 5, 6}
o
9.7
Memory Speed Limitations
The memory frequency is determined by a variety of inputs:
•
Speed of the DIMMs
•
Speed supported by the CPU
•
Configuration of the DIMMs
Table 10
shows the memory populations and the maximum frequency achievable for that configuration.
For Quad Rank DIMMs mixed with Single or Dual Rank DIMMs, the QR DIMM needs
to be in the slot with the white ejection tabs (the first DIMM slot in each channel).
There is no requirement for the order of SR and DR DIMMs.
DELL
Note
26
Advertisement
Table of Contents
