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ARTERY AT32F415CCT6 Technical Manual

Arm-based 32-bit cortex-m4f mcu + fpu, with 256 kbyte-1024 kbyte internal flash memory, usb, can, 18 timers, 3 adcs, 16 communication interfaces

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®
ARM
-based 32-bit Cortex
Flash Memory, USB, CAN, 18 Timers, 3 ADCs, 16 Communication Interfaces
Function
®
Core: ARM
32-bit Cortex
− Operating rate up to 200 MHz, with
Memory Protection Unit (MPU),
embedded single cycle multiplication
and hardware division
− Embedded Floating Point Unit (FPU)
− DSP instruction set provided
Memory
− From 256 Kbyte to 1024 Kbyte internal
Flash program/data memory
− SPIM interface: Additional external SPI
Flash program/data memory interface up
to 16 Mbytes
− Up to 96 + 128 Kbyte SRAM
− W ith 4 chip-select external controllers
(XMC). Supports CF Card, SRAM,
PSRAM, NOR, and NAND memory
− Parallel LCD interface, compatible with
8080/6800 mode
Clock, Reset, and Power Management
− 2.6 V ~ 3.6 V and I/O pins
− Power-on/Power-down Reset (POR/PDR),
Programmable Voltage Detector (PVD)
− 4 to 16 MHz crystal oscillator
− Embedded 8 MHz RC oscillator calibrated
in factory (25 ° C 1% precision, overall
temperature 2.5% precision)
− Embedded 40 kHz RC oscillator with
calibration
− RTC function 32 kHz oscillator with
calibration
Low Power Consumption
− Sleep, Stop, and Standby mode
− VBAT support for RTC and backup
register
3 12-bit A/D converters, 0.5 μs converting
time (Up to 21 input channels)
− Converting range: 0 V ~ 3.6 V
− 3 sample and hold functions
− Temparature sensor
2 12-bit D/A Converters
DMA: DMA controller with 12 channels
− Peripherals supported: Timer, ADC,
DAC, SDIO, I
Debug Mode
− Serial Wire Debug (SWD) and JTAG interface
2020.06.28
®
-M4F MCU + FPU, with 256 Kbyte ~ 1024 Kbyte Internal
®
-M4F CPU with FPU
2
2
S, SPI, I
C, and USART
AT32F415 Series Technical Manual
− Cortex
®
-M4F Embedded Trace Macrocel (ETM
Up to 112 Fast I/O Interfaces
− 36/51/80/112 multifunctional and
bidirectional I/O ports, all of which can
be mapped to 16 external interrupts ;
almost every port is tolerant to 5 V input
signal.
Up to 18 Timers
− Up to 8 16-bit timers + 2 32-bit timers;
each timer has up to 4 channels used for
input capture/output compare/PW M or
pulse counting and incremental encoder
input.
− Up to 3 16-bit advanced-control timers
with dead-time control and emergency
break, PW M used for motor control
− 2 W atchdog timers (independent and
window)
− System timer: 24-bit decremental counter
− 2 16-bit basic timers driving DAC
Up to 16 Communication Interfaces
− Up to 3 I
2
C interfaces
(Support SMBus/PMBus)
− Up to 5 USART interfaces (Supports
ISO7816, LIN, IrDA interface, and modem
control)
− Up to 4 SPI interfaces (50 Mbit/sec.), all 4
interfaces can be muxed as I
− CAN interface (2.0B active)
− USB2.0 full-speed interface
− Up to 2 SDIO interfaces
CRC Calculation Unit, 96-bit Chip-only Code
Packaging
− LQFP144 20x20 mm
− LQFP100 14x14 mm
− LQFP64 10x10 mm
− LQFP48 7x7 mm
List of Models
Internal Flash
Memory
256 Kbytes
512 Kbytes
1024 Kbytes
Page 1
2
S interfaces.
Model
AT32F415CCT6, AT32F415RCT6,
AT32F415VCT6, AT32F415ZCT6
AT32F415CET6, AT32F415RET6,
AT32F415VET6, AT32F415ZET6
AT32F415CGT6, AT32F415RGT6,
AT32F415VGT6, AT32F415ZGT6
TM
)
Version 1.02

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Summary of Contents for ARTERY AT32F415CCT6

  • Page 1 List of Models − 3 sample and hold functions Internal Flash Model − Temparature sensor Memory  AT32F415CCT6, AT32F415RCT6, 2 12-bit D/A Converters 256 Kbytes AT32F415VCT6, AT32F415ZCT6  DMA: DMA controller with 12 channels AT32F415CET6, AT32F415RET6, − Peripherals supported: Timer, ADC,...
  • Page 2 AT32F415 Series Technical Manual Table of Contents System Architecture ................25 System Introduction .................... 25 1.1.1 Bus Architecture ..................27 ® 1.1.2 ARM Cortex -M4F Processer ................ 27 Address Map ....................... 28 1.2.1 Register Map ....................29 1.2.2 Bit Banding ....................31 1.2.3 On-chip SRAM ....................
  • Page 3 AT32F415 Series Technical Manual Clocks ......................... 48 3.2.1 HSE Clock ....................50 3.2.2 HSI Clock ....................51 3.2.3 PLL ......................51 3.2.4 LSE Clock ....................51 3.2.5 LSI Clock ....................51 3.2.6 System Clock (SYSCLK) Selection ..............52 3.2.7 Clock Failure Detection (CFD) ..............52 3.2.8 RTC Clock ....................
  • Page 4 AT32F415 Series Technical Manual 4.3.2.1 Key Value ....................77 4.3.2.2 Unlock the Flash Memory ................ 77 4.3.2.3 Main Flash Programming ................. 78 4.3.2.4 Flash Erase ..................... 78 4.3.2.5 Option Byte Programming ............... 80 4.3.3 Protection ....................81 4.3.3.1 Write Protection ..................81 4.3.3.2 Read Protection ..................
  • Page 5 AT32F415 Series Technical Manual CRC Function Overview ..................99 CRC Registers ..................... 100 5.4.1 Data Register (CRC_DR) ................100 5.4.2 Independent Data Register (CRC_IDR) ............100 5.4.3 Control Register (CRC_CTRL) ............... 101 General-purpose and Alternate-function I/Os (GPIOs and AFIOs) ....102 Introduction.......................
  • Page 6 AT32F415 Series Technical Manual 6.5.7 Port Configuration Lock Register (GPIOx_LOCK) (x = A...E) ......123 6.5.8 Alternate Event Control Register (AFIO_EVCTRL) .......... 124 6.5.9 AF Remap and Debug I/O Configuration Register (AFIO_MAP) ....... 124 6.5.10 Alternate External Interrupt Configurat ion Register 1 (AFIO_EXTIC1)..... 126 6.5.11 Alternate External Interrupt Configuration Register 2 (AFIO_EXTIC2) .....
  • Page 7 AT32F415 Series Technical Manual 8.3.2 Arbiter ...................... 146 8.3.3 DMA Channels ................... 146 8.3.4 Programmable Data Transfer Width, Alignment, and Endian ........147 8.3.5 Error Management ..................148 8.3.6 Interrupts ....................148 8.3.7 DMA Request Mapping ................149 DMA Registers ....................153 8.4.1 DMA Interrupt Status Register (DMA_ISTS) ..........
  • Page 8 AT32F415 Series Technical Manual 9.2.3.1 Time-base Unit ..................171 9.2.3.2 Counter Mode ..................172 9.2.3.3 Clock Selection ..................180 9.2.3.4 Capture/Compare Channel ..............183 9.2.3.5 Input Capture Mode ................186 9.2.3.6 PWM Input Mode .................. 186 9.2.3.7 Forced Output Mode ................187 9.2.3.8 Output Compare Mode................
  • Page 9 AT32F415 Series Technical Manual 9.3.2 TMRx Main Function .................. 220 9.3.2.1 TMR9 and TMR12 Main Function ............. 220 9.3.2.2 TMR10, TMR11, TMR13, and TMR14 Main Function ........221 9.3.3 TMRx Function Overview ................222 9.3.3.1 Time-base Unit ..................222 9.3.3.2 Counter Mode ..................
  • Page 10 AT32F415 Series Technical Manual 9.3.5.7 Counter (TMRx_CNT) ................254 9.3.5.8 Prescaler (TMRx_DIV) ................254 9.3.5.9 Auto-reload Register (TMRx_AR) ............. 254 9.3.5.10 Capture/Compare Register 1 (TMRx_CC1) ..........254 Advanced-control Timer (TMR1, TMR8, and TMR15) ..........256 9.4.1 TMR1, TMR8, and TMR15 Introduction ............256 9.4.2 TMR1, TMR8, and TMR15 Main Features .............
  • Page 11 AT32F415 Series Technical Manual 9.4.4.8 TMR1, TMR8, and TMR15 Capture/Compare Mode Register 2 (TMRx_CCM2) .. 302 9.4.4.9 TMR1, TMR8, and TMR15 Capture/Compare Enable Register (TMRx_CCE) .. 304 9.4.4.10 TMR1, TMR8, and TMR15 Counter (TMRx_CNT) ........306 9.4.4.11 TMR1, TMR8, and TMR15 Prescaler (TMRx_DIV) ........306 9.4.4.12 TMR1, TMR8, and TMR15 Auto -reload Register (TMRx_AR) .......
  • Page 12 AT32F415 Series Technical Manual 11.1 Introduction....................... 322 11.2 ERTC Main Features .................... 322 11.3 ERTC Function Overview ..................323 11.3.1 Clock and Prescaler ..................323 11.3.2 Real-time Clock and Calendar ..............324 11.3.3 Programmable Clock .................. 324 11.3.4 Periodic Auto-wakeup ................325 11.3.5 ERTC Initialization and Configuration ............
  • Page 13 AT32F415 Series Technical Manual 11.6.16 ERTC Calibration Register (ERTC_CCR) ............343 11.6.17 ERTC Tamper and Alternate Function Configuration Register (ERTC_TPAF) ..344 11.6.18 ERTC Alarm Clock A Sub-second Register (ERTC_ALASBS) ......345 11.6.19 ERTC Alarm Clock B Sub-second Register (ERTC_ALBSBS) ......346 11.6.20 ERTC Backup Register (ERTC_BKPxDT) ............
  • Page 14 AT32F415 Series Technical Manual 12.4 ADC Registers ....................366 12.4.1 ADC Status Register (ADC_STS) ..............369 12.4.2 ADC Control Register 1 (ADC_CTRL1) ............369 12.4.3 ADC Control Register 2 (ADC_CTRL2) ............371 12.4.4 ADC Sample Time Register 1 (ADC_SMPT1) ..........374 12.4.5 ADC Sample Time Register 2 (ADC_SMPT2) ..........
  • Page 15 AT32F415 Series Technical Manual 13.4.7 Status Register 2 (I C_STS2) ............... 405 13.4.8 Clock Control Register (I C_CLKCTRL) ............406 13.4.9 TMRISE Register (I C_TMRISE) ..............407 14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..408 14.1 USART Introduction .................... 408 14.2 USART Main Features ..................408 14.3 USART Function Overview ...................
  • Page 16 AT32F415 Series Technical Manual 14.3.13.1 Transmission Using DMA ................ 430 14.3.13.2 Reception Using DMA ................431 14.3.13.3 Error Flag and Interrupt Generation in Multi -buffer Communication ..432 14.3.14 Hardware Flow Control ................432 14.3.14.1 RTS Flow Control ................... 432 14.3.14.2 CTS Flow Control ...................
  • Page 17 AT32F415 Series Technical Manual 15.3.2.2 Supported Audio Protocol ..............465 15.3.2.3 Clock Generator ..................471 15.3.2.4 S Master Mode ..................473 15.3.2.5 S Slave Mode ..................474 15.3.2.6 Status Flag .................... 475 15.3.2.7 Error Flag ....................476 15.3.2.8 S Interrupt ..................476 15.3.2.9 DMA Function ..................
  • Page 18 AT32F415 Series Technical Manual 16.3.9 Message Storage ..................498 16.3.10 Error Management ..................500 16.3.11 Bit Timing ....................500 16.3.12 bxCAN Interrupt ..................503 16.4 CAN Registers ....................504 16.4.1 Register Access Protection ................. 506 16.4.2 CAN Control and Status Register ..............506 16.4.2.1 CAN Main Control Register (CAN_MCTRL) ..........
  • Page 19 AT32F415 Series Technical Manual 17.3.1.2 SDIO AHB Interface ................538 17.3.2 Card Function Overview ................539 17.3.2.1 Card Identification Mode ............... 539 17.3.2.2 Card Reset .................... 539 17.3.2.3 Operating Voltage Range Validation ............539 17.3.2.4 Card Identification Process ..............539 17.3.2.5 Block Write ...................
  • Page 20 AT32F415 Series Technical Manual 17.4.1 SDIO Power Control Register (SDIO_POWER)..........561 17.4.2 SDIO Clock Control Register (SDIO_CLKCTRL) ..........562 17.4.3 SDIO Argument Register (SDIO_ARG) ............563 17.4.4 SDIO Command Register (SDIO_CMD) ............563 17.4.5 SDIO Command Response Register (SDIO_RSPCMD) ........564 17.4.6 SDIO Response 1…4 Register (SDIO_RSPx) ............
  • Page 21 AT32F415 Series Technical Manual 19.4 COMP Interrupt ....................582 19.5 COMP Register ....................583 19.5.1 Comparator Control and Status Register 1 (COMP_CTRLSTS1) ......... 583 19.5.2 Comparator Control/Status Register 2 (COMP_CTRLSTS2) ..........585 19.5.3 Glitch Filter Enable Register (G_FILTER_EN) ........... 586 19.5.4 Interference Filter High Pulse (HIGH_PULSE) ..........
  • Page 22 AT32F415 Series Technical Manual 21.6.1 USB Host Status ................... 602 21.6.2 Host Channel ....................603 21.6.3 Host Regulator .................... 604 21.7 SOF Trigger ......................606 21.7.1 Host SOF ..................... 606 21.7.2 Device SOF ....................606 21.8 Power Supply Option ................... 606 21.9 USB Data FIFO .....................
  • Page 23 AT32F415 Series Technical Manual 21.14.17 Registers in Host Mode ................637 21.14.18 OTG_FS Host Mode Configuration Register (OTG_FS_HCFG) ........637 21.14.19 OTG_FS Host Frame Interval Register (OTG_FS_HFIR) ......... 637 21.14.20 OTG_FS Host Frame Number/Frame Time Remaining Register (OTG_FS_HFNUM) 21.14.21 OTG_FS Host Periodic TX FIFO/Request Queue Register (OTG_FS_HPTXSTS) 638 21.14.22 OTG_FS Host All Channel Interrupt Register (OTG_FS_HAINT) ........
  • Page 24 AT32F415 Series Technical Manual 21.14.43 OTG_FS Device Endpoint x Interrupt Register (OTG_FS_DOEPINTx)(where x is endpoint number, x = 0...3) ..................658 21.14.44 OTG_FS Device IN Endpoint 0 Transfer Size Register (OTG_FS_DIEPTSIZ0) ... 659 21.14.45 OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) 660 21.14.46 OTG_FS Device Endpoint x Transfer Size Register (OTG_FS_DIEPTSIZx)(where x is endpoint number, x = 1...3) ..................
  • Page 25 AT32F415 Series Technical Manual 1 System Architecture ® ® AT32F415 series microcontrollers consist of ARM Cortex -M4F processor core, bus architecture, ® peripherals, and memory. Cortex -M4F process is a stage-of-the-art core, featuring many advanced ® ® functions. Compared with Cortex -M3, Cortex -M4F processer supports strengthened high-performance DSP instruction set, including extended single cycle 16-bit/32-bit multiply accumulate (MAC), dual 16-...
  • Page 26 AT32F415 Series Technical Manual Figure 1-1 AT32F415 Series Microcontrollers System Architecture HSE 4~16MHz SWJTAG HSI 8MHz SDIO Fmax 200MHz Cortex-M4 1, 2 (Fmax 200MHz) FCLK HCLK PCLK1 NVIC PCLK2 DMA1 Flash @VDD Flash 7 Channel Controller POR/PDR DMA2 SRAM SRAM Controller 5Channel LDO 1.2V...
  • Page 27 AT32F415 Series Technical Manual 1.1.1 Bus Architecture I-Code bus ● This bus connects the Instruction bus of the Cortex ® -M4F core to the Flash memory instruction interface. Prefetching is performed on this bus. D-Code bus ● This bus connects the D-Code bus (literal load and debug access) of the ®...
  • Page 28 AT32F415 Series Technical Manual ® Figure 1-2 Internal Block Diagram of Cortex -M4F Cortex-M4F Interrupts and Cortex-M4 Power control NVIC Core Including FPU SW-DP or AHB-AP Bus Matrix TPIU SWJ-DP SW/JTAG ROM Table 1.2 Address Map Program memory, data memory, registers, and I/O ports are organized within the same linear 4-GB address space.
  • Page 29 AT32F415 Series Technical Manual Figure 1-3 AT32F415 Address Configuration 0xFFFF_FFFF Reserved 0xE010_0000 0x1FFF_FFFF 0xE00F_FFFF Cortex-M4 Internal Reserved Peripherals 0xE000_0000 0x1FFF_F81F 0xDFFF_FFFF Option Bytes 0x1FFF_F800 Reserved 0x1FFF_F7FF 0xA000_1000 System memory 0xA000_0FFF XMC Reg 0xA000_0000 0x1FFF_0000 0x9FFF_FFFF External SPI Flash External memory memory (XMC) 0x0840_0000...
  • Page 30 AT32F415 Series Technical Manual 0x4002 0400 - 0x4002 07FF DMA2 Refer to Section 9.4 0x4002 0000 - 0x4002 03FF DMA1 Refer to Section 9.4 0x4001 8400 - 0x4001 7FFF Reserved 0x4001 8000 - 0x4001 83FF SDIO Refer to Section 20.4 0x4001 4400 - 0x4001 7FFF Reserved 0x4001 4000 - 0x4001 43FF...
  • Page 31 AT32F415 Series Technical Manual 0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Refer to Section 11.2.4 Window watchdog (WWDG) 0x4000 2C00 - 0x4000 2FFF Refer to Section 11.1.6 0x4000 2800 - 0x4000 2BFF Refer to Section 12.4 0x4000 2400 - 0x4000 27FF Reserved Refer to Section 10.3.4...
  • Page 32 AT32F415 Series Technical Manual 1.2.4 On-chip Flash AT32F415 series provide up to 1024 KB of on-chip Flash memory, supporting zero wait state single cycle 32-bit read operation. The Flash memory is divided into main memory block and information block. The main memory block is used for storing application code; it can be accessed by bytes (8-bit aligned), half-words (16-bit aligned), or full words (32-bit aligned).
  • Page 33 AT32F415 Series Technical Manual FLASH_CTRL2 0x4002 2050 - 0x4002 2053 FLASH_ADDR2 0x4002 2054 - 0x4002 2057 Reserved 0x4002 2058 - 0x4002 2083 FLASH_FCKEY3 0x4002 2084 - 0x4002 2087 Reserved 0x4002 2088 - 0x4002 208B FLASH_STS3 0x4002 208C - 0x4002 208F FLASH_CTRL3 0x4002 2090 - 0x4002 2093 FLASH_ADDR3...
  • Page 34 AT32F415 Series Technical Manual 1.4 Device Characteristics Information 1.4.1 Description of Register Abbreviations The following abbreviations are used in the register descriptions of this manual: Table 1-4 List of for Register Abbreviations Software can read and write to these bits. read/write (rw) Software can only read these bits.
  • Page 35 AT32F415 Series Technical Manual Base address: 0x1FFF F7EC Reset value: 0xXXXX XXXX (Factory-programmed) U_ID[63:48] U_ID[47:32] Base address: 0x1FFF F7F0 Reset value: 0xXXXX XXXX (Factory-programmed) U_ID[95:80] U_ID[79:64] 2020.06.28 Page 35 Version 1.02...
  • Page 36 AT32F415 Series Technical Manual 2 Power Control (PWR) 2.1 Introduction Power consumption is one of the most important issue in AT32F415 series devices. The operating voltage supply is 2.6 V ~ 3.6 V, and it can function normally within -40℃ ~ +85℃. To reduce power consumption and to achieve the best tradeoff among the conflicting demands of CPU operating time, speed, and power consumption, the Power Management Unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep, and Standby mode.
  • Page 37 AT32F415 Series Technical Manual Figure 2-1 Block Diagram of Each Power Supply VDDA domain REF- A/D converter (From 2.4 V up to V REF+ Temp. sensor reset block VDD domain 1.2 V domain I/O Ring CPU core memories Standby circuitry embedded (Wakeup logic,IWDG)...
  • Page 38 AT32F415 Series Technical Manual Figure 2-2 Power-on Reset/Power-down Reset W aveform 180 mV hysteresis Temporization RESTTEMPO Reset AT32F415 provides a programmable voltage detector (PVD). Users can use this PVD to monitor VDD power supply by comparing it to the PVDS[2:0] bits in the power control register (PWR_CTRL), selecting the threshold for voltage monitor.
  • Page 39 AT32F415 Series Technical Manual 2.3.1.2 Core Power Domain Core power domain includes CPU core, memory, and embedded digital peripherals. This power domain is supplied by a voltage regulator. The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes. Run mode: The regulator supplies full power to the 1.2 V domain (core, memories, and digital peripherals).
  • Page 40 AT32F415 Series Technical Manual Effect on 1.2 V Effect on VDD Voltage Mode Entry Wakeup Domain Clocks Domain Clocks Regulator CPU clock OFF, Any interrupt Sleep no effect on (SLP-NOW or other clocks or None SLP-ON-EXIT) ADC clock Wakeup event sources ON or in Any EXTI line...
  • Page 41 AT32F415 Series Technical Manual  Enabling an interrupt in the peripheral control register instead of in the NV IC, ® and enabling the SEVONPEND bit in the Cortex -M4F system control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) need to be cleared.
  • Page 42 AT32F415 Series Technical Manual the backup domain control register (RCC_BDC ). In Stop mode, peripherals such as the ADC or DAC still consume power if they are not turned off before entering Stop mode. To disable them, the ADON bit in the ADC_CR2 register and the CHENx bit in the DAC_CTRL register must both be written to 0.
  • Page 43 AT32F415 Series Technical Manual (PWR_ CTRLSTS) (See Section 3.3.10). After waking up from Standby mode, the program executes the instruction code in the same way as after reset (boot pins sampling, vector reset is fetched, etc.). The power control/status register (PWR_ CTRLSTS) (See Section 3.3.10) will instruct the MCU to exit from the Standby mode.
  • Page 44 AT32F415 Series Technical Manual Table 2-4 Standby Mode Standby Mode Description Execute WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex ® -M4F system control register Entry – Set PDDS bit in power control register (PWR_CR) –...
  • Page 45 AT32F415 Series Technical Manual 2.4 PWR Registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Offset Register PWR_CTRL 0x00 Reserved Reset Value 0 0 0 0 0 0 0 0 0 PWR_CTRL 0x04 Reserved Reserved Reset Value 0 0 0 2.4.1 Power Control Register (PWR_CTRL)
  • Page 46 AT32F415 Series Technical Manual PDDS: Power down Deep-sleep Bit 1 0: Enter Stop mode when the CPU enters Deep-sleep. 1: Enter Standby mode when the CPU enters Deep-sleep. Bit 0 Reserved 2.4.2 Power Control/Status Register (PWR_CTRLST) Address offset: 0x004 Reset value: 0x0000 0000 (Not reset by waking up from Standby mode.) Additional APB cycles are needed to read this register versus a standard APB read.
  • Page 47 AT32F415 Series Technical Manual 3 Reset and Clock Control (RCC) 3.1 Reset AT32F415 provides three types of reset, including system reset, power-on reset, and backup domain reset. 3.1.1 System Reset Except for the reset flags in the RCC_CTRLSTS register of clock controller and the registers in the backup domain, a system reset sets all registers to their reset values (See Figure 2-1).
  • Page 48 AT32F415 Series Technical Manual Figure 3-1 Reset Circuit DD V DDA External Reset System Filter reset NRST WWDG reset Pulse IWDG reset generator Power reset (Min 20 µs) Software reset Low-power management reset 3.1.3 Backup Domain Reset The backup domain has two specific resets that affect only the backup domain (See Figure 2-1).
  • Page 49 AT32F415 Series Technical Manual Figure 3-2 Clock Tree prescaler USBCLK 48 MHz /1, 1.5, 2 To USB interface 2.5, 3, 3.5, I2S[1,2,3,4]CLK I2S[1,2,3,4] HSI RC Peripheral clock 8 MHz enable SDIOCLK Peripheral clock SDIO enable XMCCLK Peripheral clock enable Max 200MHz HCLK To AHB bus, core, Peripheral clock enable...
  • Page 50 AT32F415 Series Technical Manual 1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. Otherwise, they are set to double (×2) the frequency of the APB domain to which the timers are connected.
  • Page 51 AT32F415 Series Technical Manual 3.2.2 HSI Clock The HSI clock signal is generated from an internal 8 MHz RC oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator can provide the system a clock source without any external components. Its startup time is shorter than the HSE crystal oscillator;...
  • Page 52 AT32F415 Series Technical Manual (RCC_CLKINT). LSI calibration The frequency dispersion of the low-speed internal (LSI) oscillator can be calibrated to obtain RTC time base and IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration can be done by measuring the LSI clock frequency with TIM5 input clock (TIM5_CLK).
  • Page 53 AT32F415 Series Technical Manual ─ The AWU state is not guaranteed if the VDD supply is powered off. Please refer to Section 3.2.5 for more details on LSI calibration. ● If the HSE clock divided by 128 is used as RTC clock: ─...
  • Page 54 AT32F415 Series Technical Manual Reset Value RCC_APB 2RSTR 00Ch Reserved Reset Value RCC_APB 1RSTR 010h Reset Value RCC_AH 014h Reserved Reset Value RCC_APB 018h Reserved Reset Value RCC_APB 01Ch Reset Value RCC_BD 020h Reserved Reserved Reserved Reset Value RCC_ CTRLSTS 024h Reserved Reset...
  • Page 55 AT32F415 Series Technical Manual Reset value: 0x000 XX83, where X is undefined Access: No wait state. Word, half-word, and byte access. Reserved PLLEN Reserved CFDEN STBL BYPS STBL HSICAL[7:0] HSITWK[7:3] Reserved STBL Bit 30:26 Reserved. Always read as 0. PLLSTBL: PLL clock ready flag Set by hardware after PLL is locked.
  • Page 56 AT32F415 Series Technical Manual HSISTBL: Internal high-speed clock ready flag Set by hardware to indicate that the internal 8 MHz oscillators is stable. After the HSIEN bit is Bit 1 cleared, this bit is cleared after 6 internal 8 MHz oscillator cycles. 0: Internal 8 MHz oscillator is not ready.
  • Page 57 AT32F415 Series Technical Manual 3.3.2 Clock Configuration Register (RCC_CFG) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 to 2 wait state. Word, half-word, and byte access. 1 or 2 wait states are inserted only when the access occurs during a clock source switch. PLLMUL USBPSC PLLHSE...
  • Page 58 AT32F415 Series Technical Manual PLLSRC: PLL entry clock source Set and cleared by software to select PLL input clock source. This bit can be written only Bit 16 when PLL is disabled. 0: HSI oscillator clock divided by 2 to be PLL input clock. 1: HSE clock is used as PLL input clock ADCPSC[2:0]: ADC prescaler ADCPSC[2], Set by bit 28...
  • Page 59 AT32F415 Series Technical Manual 3.3.3 Clock Interrupt Register (RCC_CLKINT) Address offset: 0x08 Reset value: 0x0000 0000 Access: No wait state. Word, half-word, and byte access. PLLST HSES HSIS LSES LSIS Reserve CFDF Reserved TBLF BLFC BLFC BLFC PLLS HSES HSIS LSES LSIS Reserve...
  • Page 60 AT32F415 Series Technical Manual HSISTBLIE: HSI ready interrupt enable Set and cleared by software to enable/disable internal 8 MHz RC oscillator ready interrupt Bit 10 0: HSI ready interrupt is disabled. 1: HSI ready interrupt is enabled. LSESTBLIE: LSE ready interrupt enable Set and cleared by software to enable/disable external 32 kHz RC oscillator ready interrupt Bit 9 0: LSE ready interrupt is disabled.
  • Page 61 AT32F415 Series Technical Manual USAR GPIO GPIO GPIO GPIO GPIO GPIOD GPIOC Reserve AFIO T1RS Bit 31:22 Reserved. Always set to 0. TMR11RST: TMR11 timer reset Set and cleared by software. Bit 21 0: No effect 1: Reset TMR11 timer TMR10RST: TMR10 timer reset Set and cleared by software.
  • Page 62 AT32F415 Series Technical Manual GPIOFRST: IO port F reset Set and cleared by software. Bit 7 0: No effect 1: Reset IO port F GPIOERST: IO port E reset Set and cleared by software. Bit 6 0: No effect 1: Reset IO port E GPIODRST: IO port D reset Set and cleared by software.
  • Page 63 AT32F415 Series Technical Manual BKPRRST: Backup interface reset Set and cleared by software. Bit 27 0: No effect 1: Reset backup interface I2C3RST: I2C 3 reset Set and cleared by software. Bit 26 0: No effect 1: Reset I2C 3 CANRST: CCAN reset Set and cleared by software.
  • Page 64 AT32F415 Series Technical Manual WWDGRST: Window watchdog reset Set and cleared by software. Bit 11 0: No effect 1: Reset Window watchdog Bit 10:9 Reserved. Always read as 0. TMR14RST: Timer 14 reset Set and cleared by software. Bit 8 0: No effect 1: Reset TMR 14 timer TMR13RST: Timer 13 reset...
  • Page 65 AT32F415 Series Technical Manual SDIO2 SDIO1 FLAS SRAM DMA2 DMA1 Reserve Reserv erve erve Bit 31:12 Reserved. Always read as 0. SDIO2EN: SDIO2 clock enable Set and cleared by software. Bit 11 0: SDIO2 clock is disabled. 1: SDIO2 clock is enabled. SDIO1EN: SDIO1 clock enable Set and cleared by software.
  • Page 66 AT32F415 Series Technical Manual USART GPIO GPIO GPIO GPIO GPIO GPIO GPIOC Reserve AFIO Bit 31:22 Reserved. Always read as 0. TMR11EN: Timer 11 clock enable Set and cleared by software. Bit 21 0: TMR11 timer clock is disabled. 1: TMR11 timer clock is enabled. TMR10EN: Timer 10 clock enable Set and cleared by software.
  • Page 67 AT32F415 Series Technical Manual GPIOGEN: I/O port G clock enable Set and cleared by software. Bit 8 0: IO port G clock is disabled. 1: IO port G clock is enabled. GPIOFEN: I/O port F clock enable Set and cleared by software. Bit 7 0: IO port F clock is disabled.
  • Page 68 AT32F415 Series Technical Manual DACEN: DAC interface clock enable Set and cleared by software. Bit 29 0: DAC interface clock is disabled. 1: DAC interface clock is enabled. PWREN: Power interface clock enable Set and cleared by software. Bit 28 0: Power interface clock is disabled.
  • Page 69 AT32F415 Series Technical Manual SPI3EN: SPI 3 clock enable Set and cleared by software. Bit 15 0: SPI 3 clock is disabled. 1: SPI 3 clock is enabled. SPI2EN: SPI 2 clock enable Set and cleared by software. Bit 14 0: SPI 2 clock is disabled.
  • Page 70 AT32F415 Series Technical Manual RTCEN Reserved RTCSEL[1:0] Reserved LSEEN BYPS STBL Bit 31:17 Reserved. Always read as 0. BDRST: Backup domain software reset Set and cleared by software. Bit 16 0: Reset is not activated. 1: Reset the entire backup domain. RTCEN: RTC clock enable Set and cleared by software.
  • Page 71 AT32F415 Series Technical Manual LPRSTF: Low-power reset flag Set by hardware when a low-power management reset occurs. It is cleared by writing to the RSTFC bit. Bit 31 0: No low-power management reset occurs. 1: Low-power management reset occurs. For further information on low-power management reset, please refer to Section 3.1.1 “Low- Power Management Reset.”...
  • Page 72 AT32F415 Series Technical Manual Bit 31:13 Reserved. Return 0 after being read. USBRST: USB reset Set and cleared by software. Bit 12 0: No effect 1: Reset USB Bit 11:0 Reserved. Return 0 after being read. 3.3.12 PLL Configuration Register (RCC_PLL) Address offset: 0x2C Reset value: 0x0000 1F10 Access: 0 waiting state.
  • Page 73 AT32F415 Series Technical Manual 3.3.13 Additional Register (RCC_MISC) Address offset: 0x30 Reset value: 0x0000 0000 Reserved Reserved CLKOUT[3] 768B Reserved HSICAL_KEY[7:0] Bit 31:25 Reserved. Return 0 after being read. USB768B: USB buffer size Bit 24 0: The buffer is 512 byte. 1: The buffer is 768 byte.
  • Page 74 AT32F415 Series Technical Manual AUTO_STEP_EN: Auto step clock switch enable As for system clock switch to PLL or switch AHB divider from low frequency to high frequency, it is recommended to enable auto step clock switch function when switching system clock from low frequency to high frequency (greater than 108 MHz).
  • Page 75 Information block is divided into two parts: ● System memory is used for boot loader store d in the system memory bootstrapping mode. This area is reserved only for Artery, and the boot loader uses USART1; USART2 or OTG FS device mode (DFU) performs programming to the Flash memory;...
  • Page 76 AT32F415 Series Technical Manual Write to main memory and information block is controlled by embedded Flash program/erase controller (FPEC). High voltages of program and erase are generated internally. Flash memory provides two kinds of protection to avoid illegal access (read, write, and erase): Page write protection Read protection (Please refer to Section 4.3.3...
  • Page 77 AT32F415 Series Technical Manual D-Code interface includes simple AHB interface on CPU and logic circuit that requests access to the arbiter of Flash access controller. Access to D-code has higher priority than access to prefetch instruction. This interface uses access time regulator block of prefetch buffer. 4.3.1.3 Flash Access Controller This block is the arbiter of the instruction prefetch request on I-Code and read request on D-Code interface.
  • Page 78 AT32F415 Series Technical Manual 4.3.2.3 Main Flash Programming The Flash memory can be programmed with 32, 16, or 8 bits at a time. When the PRGM bit in FLASH_CTRL register is ‘1’, writing a half-word to a Flash address will activate one programming operation.
  • Page 79 AT32F415 Series Technical Manual main memory extension area actually erases the whole system memory area. If system memory is used as main memory extension area, then page erase includes the erase on main memory and system memory are. Any page in the Flash memory can be erased with the FPEC page erase function. Below should be followed during page erase: ...
  • Page 80 AT32F415 Series Technical Manual Figure 5-2 Process of Flash Memory Mass Erase Read the LOCK bit in FLASH_CR Execute Unlock LOCK bit = 1 Process Set MER = 1 in FLASH_CR; Set STRT = 1 in FLASH_CR BSY bit = 1 in FLASH_SR Read and verify data on all pages 4.3.2.5 Option Byte Programming...
  • Page 81 AT32F415 Series Technical Manual Process of erase The erase operation (OPTERASE) of option bytes is in the following order:  Check the BSY bit in the FLASH_STS register to confirm that there is no other programming operation in process;  Unlock the UOBWE bit in the FLASH_CTRL register;...
  • Page 82 AT32F415 Series Technical Manual Any value Opposite of non-RDP byte Protected Figure 4-4 Read Protection Level Switch Status Diagram Selection byte non-RDP bit change Level 1 (low-level protection) RDP is not 0x00A5. Erase selection RDP is 0x00CC. Erase selection byte byte;...
  • Page 83 AT32F415 Series Technical Manual  Reset (any reset) and reload option bytes (and new RDP code). Read protection will be disabled at this time. Note: Boot loader can also be used to disable the read protection (In this case, o ption bytes can be reloaded just by system reset).
  • Page 84 AT32F415 Series Technical Manual WDG_SW Bit 6 0: Hardware watchdog 1: Software watchdog WRPRTBMPx: Flash memory write protection option byte Every bit in the WRPRTBMPx option byte is used to protect the two memory pages (2K byte/page) in the main memory. However, Bit 7 in WRPRTBMP3 is used to protect page 62 ~ 10239: 0: Write protection is enabled.
  • Page 85 AT32F415 Series Technical Manual Only D Code bus is allowed to read data security library When writing or deleting security library code, a warning message will be issued in the FLASH_STS register, the WRPRTFLR bit. By default, security library configuration register cannot be read and it is write protected. To write in security library configuration register, security library should be unlocked first.
  • Page 86 AT32F415 Series Technical Manual ● Check the BSY bit in the FLASH_STS register to ensure that there is no other ongoing programming operations; ● Set the start code address to be calibrated in the FLASH_CRC_AR register; ● Set the code length to be calibrated in the FLASH_CRC_CR register bit[15:0] (by page);...
  • Page 87 AT32F415 Series Technical Manual 4.4 FMC Registers Table 5-5 Flash Memory Interface— Register Map and Reset Values Offset Register FLASH_ 0x00 Reserved Reset Value FLASH_ KEY[31:0] FCKEY 0x04 Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x FLASH_ OPTKEYR[31:0] OPTKEYR...
  • Page 88 AT32F415 Series Technical Manual FLASH_ CTRL2 0x50 Reserved Reset Value 0 0 0 FLASH_ TA[31:0] ADDR2 0x54 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ KEY [31:0] FCKEY3...
  • Page 89 AT32F415 Series Technical Manual HLFCYA: Flash memory half cycle access enable Bit 3 0: Half cycle access is disabled; 1: Half cycle access is enabled. Bit 2:0 Reserved. 4.4.2 FPEC Key Register (FLASH_FCKEY) Only used in Flash memory Bank 1. Address offset: 0x04 Reset value: xxxx xxxx KEY[31:16]...
  • Page 90 AT32F415 Series Technical Manual Reserved. Must be kept at reset value ‘0’. Bit 31:6 PRCDN: Process Done When Flash memory operation (program/erase) is completed, this bit is set by hardware. This Bit 5 bit is cleared by writing ‘1’. Note: Every successful program or erase will set PRCDN status. WRPRTFLR: Write protection error Bit 4 When programming write-protected Flash memory address, this bit is set by hardware.
  • Page 91 AT32F415 Series Technical Manual ERRIE: Error status interrupt enable This bit enables interrupt when FPEC errors occur. (When the PRGMFLR/WRPRTFLR in Bit 10 LASH_STS register is set.) 0: Interrupt is disabled; 1: Interrupt is enabled. UOBWE: Option bytes write enable Bit 9 When this bit is set, programming to option bytes is enabled.
  • Page 92 AT32F415 Series Technical Manual nSTDBY nSTP SYSCL RDPR USER_D0[5:0] Unused _RST _RST KSEL_WDG Reserved. Must be kept at reset value ‘0’. Bit 31:27 RDPRT_HL: Read protection high bit Read protection level is judged by {Bit26, Bit1} together. 0: Read protection is not enabled, and RDP value = 0x00A5 Bit 26 1: Lowe-level read protection is enabled, and RDP value is not 0xCC and 0xA5 2: Reserved...
  • Page 93 AT32F415 Series Technical Manual KEY[15:0] Note: All bits are write-only, and will return 0 after being read. KEY: FPEC key Bit 31:0 These bits are used for FPEC unlock key in Bank 2. 2020.06.28 Page 93 Version 1.02...
  • Page 94 AT32F415 Series Technical Manual 4.4.10 Flash Status Register 2 (FLASH_STS2) Only used in Flash memory Bank 2. Address offset: 0x4C Reset value: 0x0000 0000 Reserved WRPR PRGM Reserved Reserved Reserved TFLR Reserved. Must be kept at reset value ‘0’. Bit 31:6 PRCDN: Process Done When Flash memory operation (program/erase) is completed, this bit is set by Bit 5...
  • Page 95 AT32F415 Series Technical Manual ERRIE: Error status interrupt enable This bit enables interrupt when FPEC errors occur. (When the PRGMFLR/WRPRTFLR bit in FLASH_STS2 register is set.) Bit 10 0: Interrupt is disabled; 1: Interrupt is enabled. LOCK: Lock This bit can only be written ‘1’. When this bit is set, FPEC and FLASH_CTRL2 are Bit 7 locked.
  • Page 96 AT32F415 Series Technical Manual KEY[15:0] Note: All bits are write-only, and will return 0 after being read. KEY: FPEC key Bit 31:0 These bits are used for FPEC unlock key in Bank 3. 4.4.14 Flash Option Byte Register (FLASH_SELECT) Only used in Flash memory Bank 3. Address offset: 0x88 Reset value: 0x0000 0000 SELECT[31:16]...
  • Page 97 AT32F415 Series Technical Manual PRGMFLR: Programming error When programming address of which the content is not ‘0xFFFF’, this bit is set by Bit 2 hardware. This bit is cleared by writing ‘1’. Note: Before programming, the RSTR bit in FLASH_CTRL3 register must be cleared Reserved.
  • Page 98 AT32F415 Series Technical Manual 4.4.17 Flash Address Register 3 (FLASH_ADDR3) Only used in Flash memory Bank 3. Address offset: 0x94 Reset value: 0x0000 0000 TA[31:16] TA[15:0] These bits are modified by hardware as the current/last address being used. In page erase operation, this register must be modified by software to select the pages to be erased.
  • Page 99 AT32F415 Series Technical Manual CRC Calculation Unit (CRC) 5.1 CRC Introduction The Periodic Redundancy Check (CRC) calculation unit is used to calculate a 32-bit CRC code based on a fixed generator polynomial. In other applications, CRC-based techniques are applied to verify the correctness and integrity of data transmission or data storage.
  • Page 100 AT32F415 Series Technical Manual 5.4 CRC Registers CRC calculation unit includes two data registers and one control register. Table 6-1 lists CRC register map and reset values. Table 6-1 CRC Calculation Unit Register Map Offset Register 31~24 23~16 15~8 CRC_DR Data Register 0x00 0xFFFF FFFF...
  • Page 101 AT32F415 Series Technical Manual 5.4.3 Control Register (CRC_CTRL) Address offset: 0x08 Reset value: 0x0000 0000 Reserved Reserved RESET Bit 31:8 Reserved RESET bit Bit 7:0 Reset CRC calculation unit, set data register as 0xFFFF FFFF. This bit can only be written ‘1’, and is cleared by hardware automatically. 2020.06.28 Page 101 Version 1.02...
  • Page 102 AT32F415 Series Technical Manual 6 General-purpose and Alternate-function I/Os (GPIOs and AFIOs) 6.1 Introduction GPIO interface includes 7 sets of general-purpose I/O ports. Each GPIO set provides 16 general-purpose I/O pins. Each GPIO port has relevant control and configuration registers to fulfill specific functions. External interrupts on the GPIO pins also have relevant control and configuration registers in external interrupt controller.
  • Page 103 AT32F415 Series Technical Manual Figure 7-1 shows a basic structure of an I/O port bit. Figure 7-1 Basic Structure of an I/O Port Bit Analog Input Pull-up To on-chip switch peripheral Alternate Function Input Input Switch Read V DD TTL Schmitt trigger Protection Pull-down...
  • Page 104 AT32F415 Series Technical Manual Table 7-1 Port Bit Assignment PxOPTDT Configuration Mode CONF1 CONF0 MDE1 MDE0 Register Push-Pull 0 or 1 General-purpose Output Open-Drain 0 or 1 Push-Pull Unused Alternate Function Output Open-Drain Unused Analog Unused Floating Unused Input Pull-Down Pull-Up During and after reset, alternate function will not be enabled.
  • Page 105 AT32F415 Series Technical Manual Figure 7-3 Input Floating/Pull-up/Pull-down Configuration Pull-up switch Input ON Read (Note) DD or DD_FT Protection Pull-down diode switch V SS Input driver I/O pin Write Protection Output driver diode V SS Read/Write Output disabled Note: V is specific to 5-V tolerant I/Os, and is different from V D D _FT 6.3.4...
  • Page 106 AT32F415 Series Technical Manual Figure 7-4 High Impedance Analog Input Configuration To on-chip Analog Input peripheral Input OFF Read V DD or (Note) DD_FT TTL Schmitt trigger Protection diode Input driver I/O pin Write Protection Output driver diode V SS Read/Write Output Disabled...
  • Page 107 AT32F415 Series Technical Manual Figure 7-5 Output Configuration Input ON Read V DD or V DD_FT (Note) Protection Write diode Input driver I/O pin Protection Output driver V DD diode P-MOS V SS Output control Read/Write N-MOS V SS Push-pull or open-drain Note: V is specific to 5-V tolerant I/Os, and is different from V...
  • Page 108 AT32F415 Series Technical Manual  Weak pull-up and pull-down resistors are disabled.  If pins are configured as multiple -function output, please refer to the data sheet for the priority of each alternate function.  Data present on the I/O pin is sampled into the input data register every APB2 clock cycle.
  • Page 109 AT32F415 Series Technical Manual TMR1/8/15_ETR External trigger timer input Input floating 2020.06.28 Page 109 Version 1.02...
  • Page 110 AT32F415 Series Technical Manual Table 7-3 General-purpose Timer TMR2-5/TMR9-14 TMRx Pin Configuration GPIO Configuration Input capture channel x Input floating TMRx_CHx Output compare channel x Alternate function push-pull TMRx_ETR External trigger timer input Input floating Table 7-4 USART USART Pin Configuration GPIO Configuration Full duplex...
  • Page 111 AT32F415 Series Technical Manual Table 7-6 I S Pin Configuration GPIO Configuration Master Alternate function push-pull I2Sx_WS Slave Input floating Master Alternate function push-pull I2Sx_CK Slave Input floating Transmitter Alternate function push-pull I2Sx_SD Input floating/Input pull-up Receiver /Input pull-down Master Alternate function push-pull I2Sx_MCK Slave...
  • Page 112 AT32F415 Series Technical Manual Table 7-12 XMC Pin GPIO Configuration XMC_A[25:0] Alternate function push-pull XMC_D[15:0] XMC_CK Alternate function push-pull XMC_NOE Alternate function push-pull XMC_NWE XMC_NE[4:1] XMC_NCE[3:2] Alternate function push-pull XMC_NCE4_1 XMC_NCE4_2 XMC_NWAIT Input floating/Input pull-up XMC_CD XMC_NIOS16 XMC_INTR Input floating XMC_INT[3:2] XMC_NL Alternate function push-pull...
  • Page 113 AT32F415 Series Technical Manual 6.4.3 CAN Alternate Function Remapping CAN signal can be mapped to port A, port B, or port D, as shown in Table 7-14. For port D, there is no remapping function in 48-pin and 64-pin packages. Table 7-14 CA1 Alternate Function Remapping CAN_REMAP[1:0] = ‘00’...
  • Page 114 AT32F415 Series Technical Manual Note: I/O port can be used only when asynchronous trace is not used. 6.4.5 ADC Alternate Function Remapping Please refer to the AF remap and debug I/O configuration register (AFIO_MAP). 2020.06.28 Page 114 Version 1.02...
  • Page 115 AT32F415 Series Technical Manual Table 7-17 ADC1 External Trigger Injected Conversion Alternate Function Remapping Alternate Function ADC1_EXTRGINJ_REMAP = 0 ADC1_EXTRGINJ_REMAP = 1 ADC1 External Trigger Injected ADC1 External Trigger Injected ADC1 External Trigger Injected Conversion is connected to Conversion Conversion is connected to EXTINT15 TMR8_CH4 Table 7-18 External...
  • Page 116 AT32F415 Series Technical Manual TMR3_CH3 TMR3_CH4 Note: Remapping only applies to 64 -pin, 100-pin, and 144-pin packages. Table 7-24 TMR2 Alternate Function Remapping TMR2_REMAP[1:0] TMR2_REMAP[1:0] TMR2_REMAP[1:0] TMR2_REMAP[1:0] = 00 = 01 = 10 = 11 Alternate Function (No remapping) (Partial remapping) (Partial remapping) (Full remapping) TMR2_CH1_ETR...
  • Page 117 AT32F415 Series Technical Manual Table 7-30 TMR14 Alternate Function Remapping Alternate Function TMR14_REMAP = 0 TMR14_REMAP = 1 Mapping TMR14_CH1 Table 7-31 TMR15 Alternate Function Remapping Alternate Function TMR15_REMAP = 0 TMR15_REMAP = 1 Mapping TMR15_ETR PF14 TMR15_CH1 TMR15_CH2 TMR15_CH3 TMR15_CH4 PF13 TMR15_BKIN...
  • Page 118 AT32F415 Series Technical Manual Table 7-34 USART1 Remapping USART1_REMAP = 0 USART1_REMAP = 1 Alternate Function USART1_TX USART1_RX PA10 6.4.8 C Alternate Function Remapping Please refer to the AF remap and debug I/O configuration register (AFIO_MAP). Table 7-35 C1 Remapping Alternate Function I2C1_REMAP = 0 I2C1_REMAP = 1...
  • Page 119 AT32F415 Series Technical Manual 6.4.11 SDIO2 Alternate Function Remapping Please refer to the AF remap and debug I/O configuration register 2 (AFIO_MAP2). Table 7-39 SDIO2 Dx Alternate Function Remapping Alternate Function SDIO2_REMAP[0] = 0 SDIO2_REMAP[0] = 1 SDIO2_D0 SDIO2_D1 SDIO2_D2 SDIO2_D3 SDIO2_D4 SDIO2_D5...
  • Page 120 AT32F415 Series Technical Manual GPIOx_IPTD IPTDT[15:0] 008h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_OPT OPTDT[15:0] 00Ch Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BSR BRE[15:0] BST[15:0]...
  • Page 121 AT32F415 Series Technical Manual Reset value: 0x44444444 CONF7[1:0] MDE7[1:0] CONF6[1:0] MDE6[1:0] CONF5[1:0] MDE5[1:0] CONF4[1:0] MDE4[1:0] CONF3[1:0] MDE3[1:0] CONF2[1:0] MDE2[1:0] CONF1[1:0] MDE1[1:0] CONF0[1:0] MDE0[1:0] CONFy[1:0]: Portx configuration bit y (y = 0…7) Set by software to configure the corresponding I/O ports. Please refer to Table 7-1 for port bit configuration.
  • Page 122 AT32F415 Series Technical Manual Bit 29:28 MDEy[1:0]: Portx Mode bit y (y = 8…15) 25:24 Set by software to configure the corresponding I/O ports. Please refer to Table 7-1 for 21:20 port bit configuration. 17:16 00: Input mode (Reset state) 13:12 01: Output mode;...
  • Page 123 AT32F415 Series Technical Manual [15] [14] [13] [12] [11] [10] BREy: Portx Reset bit y (y = 0…15) These bits are write-only and are accessed only by word (16 bits). 0: No action to the corresponding OPTDTy bits. Bit 31:16 1: Reset the corresponding OPTDTy bit.
  • Page 124 AT32F415 Series Technical Manual LOCKK: Lock key This bit can be read anytime, and is modified only by writing the lock key sequence. 0: Port configuration lock key is not activated. 1: Port configuration lock key is activated, and the GPIOx_LOCK register is locked before the next reset.
  • Page 125 AT32F415 Series Technical Manual SPI1_REMAP[1]: SPI1 remapping Bit 31 Specify the reference bit 0 of SPI1_REMAP[1:0]. Bit 30:27 Reserved SWJTAG_CONF[2:0]: Serial wire JTAG configuration Only be written by software (reading these bits will return undefined values), and are used to configure SWJ and trace the I/O ports of alternate functions. SWJ ®...
  • Page 126 AT32F415 Series Technical Manual TMR2_REMAP[1:0]: TMR2 remapping Set and cleared by software. It controls the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. Bit 9:8 00: No remapping (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remapping (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remapping (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remapping (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) TMR1_REMAP[1:0]: TMR1 remapping...
  • Page 127 AT32F415 Series Technical Manual Bit 31:16 Reserved EXTINTx[3:0]: EXTINTx configuration (x = 0…3) Can be read and written by software. Used to select the input source for EXTINTx external interrupt. Bit 15:0 0000: PA[x] pin 0100: PE[x] pin 0001: PB[x] pin 0101: PF[x] pin 0010: PC[x] pin 0110: PG[x] pin...
  • Page 128 AT32F415 Series Technical Manual 6.5.12 Alternate External Interrupt Configuration Register 3 (AFIO_EXTIC3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTINT11[3:0] EXTINT10[3:0] EXTINT9[3:0] EXTINT8[3:0] Bit 31:16 Reserved EXTINTx[3:0]: EXTINTx configuration (x = 8…11) Can be read and written by software. Used to select the input source for EXTINTx external interrupt.
  • Page 129 AT32F415 Series Technical Manual Reser Reser Reser Reser Reser Reser Reser Reserved Reserved Bit 31:28 Reserved。 COMP_REMAP: COMP internal remap This bit can be set or cleared by software; it controls COMP internal mapping. When this field is set to ’00’, COMP1_OUT is connected to PA0, and COMP2_OUT is connected to PA2;...
  • Page 130 AT32F415 Series Technical Manual Reserved for future extension, please all write ‘0’. Bit 23:20 Reserved for future extension, please all write ‘0’. Bit 19:16 Reserved for future extension, please all write ‘0’. Bit 15:12 TMR11_GRMP: TMR11 remapping Bit 11:8 Please refer to TMR11 alternate function remapping. 0000 ~ 1111: If this bit is not used, please all write ‘0’.
  • Page 131 AT32F415 Series Technical Manual TMR1_GRMP: TMR1 remapping This field can be set or cleared by software; it controls TMR1 internal mapping. Bit 3:0 Please refer to timer alternate function remapping. 0000 ~ 1111: If this bit is not used, please all write ‘0’. 6.5.17 AF Remap and Debug I/O Configuration Register 5 (AFIO_MAP5) Address offset: 0x28...
  • Page 132 AT32F415 Series Technical Manual Reset value: 0x00000000 UART4_GRMP USART3_GRMP Reserved USART1_GRMP Reserved SDIO1_GRMP Reserved CAN1_GRMP UART4_GRMP: mUART4 remapping This field can be set or cleared by software; it controls alternate function, UART4_RX and UART_TX remapping. Bit 31:28 0000:UART4_RX maps to PC11, and UART4_TX maps to PC10; 0001:UART4_RX maps to PF5, and UART4_TX maps to PF4;...
  • Page 133 AT32F415 Series Technical Manual eflash bist controller enable This bit can be set or cleared by software. It controls eflash bist controller clock and Bit 28 reset bit 1: elfash bist controller is enabled. 0: elfash bist controller is disabled. Reserved for future extension, please all write ‘0’.
  • Page 134 AT32F415 Series Technical Manual TMR3_ TMR2_ TMR1_ TMR1_ CH1_ CH4_ CH1_ BK1_ Reserved COMP COMP COMP COMP [1:0] [1:0] [1:0] [1:0] Bit 31:8 Reserved TMR3_CH1_COMP[1:0]: TMR3 CH1 COMP output selection This bit can be set or cleared by software; it controls TMR3 channel 1 internal mapping. Bit 7:6 00, 01: TMR3_REMAP selected signal maps to TMR3 channel 1.
  • Page 135 AT32F415 Series Technical Manual 7 Interrupts and Events 7.1 Nested Vectored Interrupt Controller Features ● 68 maskable interrupt channels (not including 16 Cortex ® -M4F interrupt lines); ● 16 programmable priority levels (4-bit interrupt priority configuration); ● Low-latency processing of exceptions and interrupts; ●...
  • Page 136 AT32F415 Series Technical Manual Flash global interrupt FLASH 0x0000_0050 Configurable Reset and RCC interrupt 0x0000_0054 Configurable EXTINT0 EXTI Line0 interrupt 0x0000_0058 Configurable EXTINT1 EXTI Line1 interrupt 0x0000_005C Configurable EXTINT2 EXTI Line2 interrupt 0x0000_0060 Configurable EXTINT3 EXTI Line3 interrupt 0x0000_0064 Configurable EXTINT4 EXTI Line4 interrupt 0x0000_0068...
  • Page 137 AT32F415 Series Technical Manual USART3 USART3 global interrupt 0x0000_00DC Configurable EXTINT15_10 EXTI Line[15:10] interrupt 0x0000_00E0 Configurable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4 Configurable USB Wakeup through EXTI line interrupt USBWakeUp 0x0000_00E8 Configurable TMR8 Break interrupt and TMR12 global TMR8_BRK_TMR12 0x0000_00EC Configurable...
  • Page 138 AT32F415 Series Technical Manual 7.2.1 Main Features The main features of EXTI controller are as follows: ● Independent trigger and mask on each interrupt/event ● Dedicated status bit for each interrupt line ● Up to 20 software event/interrupt requests ● Detection of external signal with pulse width lower than APB2 clock period. Please refer to the electrical characteristics section of the data sheet for detail on this parameter.
  • Page 139 AT32F415 Series Technical Manual request by writing ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event request pulse is generated. The pending bit corresponding to the event line is not set. An interrupt/event request can also be generated by software when writing ‘1’...
  • Page 140 AT32F415 Series Technical Manual Figure 8-2 External Interrupt GPIO Mapping EXIT0[3:0] bit in AFIO_EXITCR1 register EXIT0 EXIT1[3:0] bit in AFIO_EXITCR1 register EXIT1 EXIT15[3:0] bit in AFIO_EXITCR4 register PA15 PB15 PC15 PD15 EXIT15 PE15 PF15 PG15 To configure the external interrupt/event on GPIO lines with AFIO_EXTICRx, the AFIO clock should first be enabled.
  • Page 141 AT32F415 Series Technical Manual Table 8-2 lists the EXTI register map and reset values. Bit 19 in all the registers only applies to connectivity line devices, and it is reserved in other devices. Table 8-2 External Interrupt/Event Controller Map and Reset Values Offset Register EXTI_INTEN...
  • Page 142 AT32F415 Series Technical Manual Reserved MR19 MR18 MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10 Reserved. Must be kept at reset value ‘0’. Bit 31:20 MRx: Event Mask on line x 0: Event request from Line x is masked. Bit 19:0 1: Event request from Line x is not masked.
  • Page 143 AT32F415 Series Technical Manual TRx: Falling trigger event configuration bit of line x 0: Falling trigger (event and interrupt) on input line x is disabled. Bit 19:0 1: Falling trigger (event and interrupt) on input line x is enabled. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. Note: The external wakeup lines are edge triggered, and no glitches are generated on these lines.
  • Page 144 AT32F415 Series Technical Manual DMA Controller (DMA) 8.1 DMA Introduction Direct memory access (DMA) provides high-speed data transfer between peripheral and memory, or between memory and memory. Without the intervention of CPU, data can be quickly transferred through DMA, keeping CPU resources free for other operations. There are 12 channels in the two DMA controllers (7 in DMA1, 5 in DMA2).
  • Page 145 AT32F415 Series Technical Manual Figure 9-1 DMA Block Diagram ICode Flash Flash Interface controller DCode Cortex®-M4F Core System SARM DMA1 request Reset and clock Channel 1 SDIO1,2 DMA2 control (RCC) Channel2 Channel7 Bridge 2 APB1 Bridge 1 Arbiter APB2 DMA request GPTM2 SPI4/I2S4 AHB Device...
  • Page 146 AT32F415 Series Technical Manual for the first transfer is the peripheral base address or memory unit programmed in the DMA_CPBAx or DMA_CMBAx register.  Execute a decrementing operation of the DMA_TCNTx register, which contains the number of unfinished transactions . 8.3.2 Arbiter The arbiter manages the channel requests based on their priorities to enable peripheral/memory...
  • Page 147 AT32F415 Series Technical Manual from/written to this address when there is peripheral data transfer request. Configure the amount of data to be transferred in the DMA_TCNTx register. After each data transfer, this value will be decremented. Configure channel priority using CHPL[1:0] bits DMA_CHCTRLx register.
  • Page 148 AT32F415 Series Technical Manual 0x0/B1B0 1: Read B1B0[15:0] at 0x0, then write B1B0[15:0] at 0x0 0x0/B1B0 0x2/B3B2 2: Read B3B2[15:0] at 0x2, then write B3B2[15:0] at 0x2 0x2/B3B2 0x4/B5B4 3: Read B5B4[15:0] at 0x4, then write B5B4[15:0] at 0x4 0x4/B5B4 0x6/B7B6 4: Read B7B6[15:0] at 0x6, then write B7B6[15:0] at 0x6 0x6/B7B6...
  • Page 149 AT32F415 Series Technical Manual Interrupt Event Event Flag Bit Enable Control Bit Half transfer HTIF HTIE Transfer completed TCIF TCIE Transfer error ERRIF ERRIE Note: DMA2 channel 4 and DMA2 channel 5 interrupts are mapped onto the same interrupt vector. 8.3.7 DMA Request Mapping DMA1 Controller...
  • Page 150 AT32F415 Series Technical Manual Figure 9-2 DMA1 Request Mapping Peripheral request signal Fixed software ADC1 priority TMR2_CH3 Hardware request 1 TMR4_CH1 Channel1 TMR15_CH3 TMR15_UP High priority Software trigger (MEM2MEM bit) Channel1 EN bit SPI1/I2S1_RX USART3_TX Hardware request 2 I2C3_TX TMR1_CH1 TMR2_UP Channel2 TMR3_CH3...
  • Page 151 AT32F415 Series Technical Manual Table 9-3 Summary of DMA1 Requests for Each Channel Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI1/I2S1_RX SPI1/I2S1_TX SPI2/I2S2_RX SPI2/I2S2_TX SPI/I USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C3_TX...
  • Page 152 AT32F415 Series Technical Manual Figure 9-3 DMA2 Request Mapping Peripheral request signals Fixed hardware SPI3/I2S3_RX Hardware priority TMR5_CH4 request 1 TMR5_TRIG Channel1 TMR8_CH3 High priority TMR8_UP Software trigger (MEM2MEM bit) SPI3/I2S3_TX Channel1 EN bit TMR5_CH3 Hardware TMR5_UP request 2 TMR8_CH4 TMR8_TRIG Channel2 TMR8_COM...
  • Page 153 AT32F415 Series Technical Manual 8.4 DMA Registers The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit). Note: In the following registers, all bits related to channel6 an d channel7 are not relevant for DMA2 since it has only 5 channels. Table 9-5 DMA Register Map and Reset Values Offset Register...
  • Page 154 AT32F415 Series Technical Manual DMA_ PA[31:0] CPBA3 038h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ MA[31:0] 03Ch...
  • Page 155 AT32F415 Series Technical Manual DMA_TCNT CNT[15:0] 084h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ PA[31:0] 088h CPBA7 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ MA[31:0] CMBA7...
  • Page 156 AT32F415 Series Technical Manual Bit 31:28 Reserved. Always read as 0. CERRIFx: Channel x transfer error clear (x = 1 … 7) Bit 27, 23, These bits are set and cleared by software. 19, 15, 0: No effect 11, 7, 3 1: Clear the corresponding ERRIF flag in the DMA_ISTS register CHTIFx: Channel x half transfer clear (x = 1 …...
  • Page 157 AT32F415 Series Technical Manual PWIDTH[1:0]: Peripheral size These bits are set and cleared by software. 00: 8 bits Bit 9:8 01: 16 bits 10: 32 bits 11: Reserved MINC: Memory increment mode This bit is set and cleared by software. Bit 7 0: Memory increment mode is disabled.
  • Page 158 AT32F415 Series Technical Manual CNT[15:0]: Number of data to transfer The number of data to be transferred is from 0 up to 65535. This register can only be written when the channel is disabled (CHEN = 0 in the DMA_CHCTRLx register). Once the channel is enabled, this register is read-only, indicating how many transfers remain.
  • Page 159 AT32F415 Series Technical Manual Timer AT32F415 timers include basic timers, general-purpose timers, and advanced-control timers. Please refer to Section 10.1 ~ Section 10.4 for the detailed function modes. All functions of different timers are shown in the following tables. Counter Count Prescaler Capture/compare...
  • Page 160 AT32F415 Series Technical Manual Basic Timer (TMR6 and TMR7) 9.1.1 TMR6 and TMR7 Introduction Basic timers TMR6 and TMR7 consist of a 16-bit auto-reload counter driven by their own programmable prescaler, respectively. They can be used as general-purpose timers to provide time base, and are especially used to provide clocks for the digital-to-analog converter (DAC).
  • Page 161 AT32F415 Series Technical Manual  Prescaler register (TMRx_DIV)  Auto-reload register (TMRx_AR) The auto-reload register is preloaded. Each read or write to the auto-reload register is achieved by writing or reading the preload register. The contents written to the preload register are transferred into its shadow register immediately or at each update event according to the auto-reload preload enable bit (ARPEN) in the TMRx_CTRL1 register.
  • Page 162 AT32F415 Series Technical Manual Figure 10-3 Counter Timing Diagram with Prescaler Division Changing from 1 to 4 CK_DIV CNT_EN Timer clock = CK_CNT Counter register Update event (UEV) Prescaler control register Write new values to the TMRx_DIV register Prescaler buffer Prescaler counter 9.1.3.3 Counting Mode The counter counts from 0 to the auto-reload value (TMRx_AR register), and restarts from 0 and...
  • Page 163 AT32F415 Series Technical Manual Figure 10-4 Counter Timing Diagram with Internal Clock Divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-5 Counter Timing Diagram with Internal Clock Divided by 2 CK_INT CNT_EN Timer clock = CK_CNT...
  • Page 164 AT32F415 Series Technical Manual Figure 10-7 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-8 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not Preloaded) CK_INT CNT_ EN...
  • Page 165 AT32F415 Series Technical Manual Preloaded) CK_DIV CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Auto-reload shadow register Writing new values to the TMRx_AR register 9.1.3.4 Clock Source The counter clock is provided by the internal clock (CK_INT) source. The CNTEN bit in the TMRx_CTRL1 register and the UEVG bit in the TMRx_EVEG register are the actual control bits, which can be changed only by software (except for the UEVG bit, which is cleared automatically).
  • Page 166 AT32F415 Series Technical Manual 9.1.4 TMR6 and TMR7 Registers These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 10-1, all the TMRx registers are mapped to a 16-bit addressable space. Table 10-1 TMR6 and TMR7– Register Table and Reset Values Offset Register TMRx_...
  • Page 167 AT32F415 Series Technical Manual OPMODE: One-pulse mode Bit 3 0: The counter is not stopped at update event. 1: The counter stops counting at the next update event (clearing the CNTEN bit). UEVRS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: If interrupt/DMA is enabled, any of the following events generates an update interrupt or DMA request: Bit 2...
  • Page 168 AT32F415 Series Technical Manual 9.1.4.3 TMR6 and TMR7 DMA/Interrupt Enable Register (TMRx_DIE) Address offset: 0x0C Reset value: 0x0000 UEVD Reserved Reserved Bit 15:9 Reserved. Always read as 0. UEVDE: Update DMA request enable Bit 8 0: Update DMA request is disabled. 1: Update DMA request is enabled.
  • Page 169 AT32F415 Series Technical Manual UEVG: Update generation This bit is set by software and is automatically cleared by hardware. Bit 0 0: No effect 1: Re-initialize the timer counter and generate an update to the registers Note: The prescaler is also cleared (but the prescaler ratio remains the same). 9.1.4.6 TMR6 and TMR7 Counter (TMRx_CNT) Address offset: 0x24 Reset value: 0x0000...
  • Page 170 AT32F415 Series Technical Manual General-purpose Timer (TMR2 to TMR5) 9.2.1 TMRx Introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
  • Page 171 AT32F415 Series Technical Manual Figure 10-11 General-purpose Timer Block Diagram Internal clock(CK_INT) To other timers Trigger TMRxCLK from RCC ETRF To DAC/ADC Polarity selection, control ETRP TMRX_ETR edge detector, and Input filter TRGO prescaler ITR0 Slave mode ITR1 TRGI controller ITR2 Reset, enable, ITR3...
  • Page 172 AT32F415 Series Technical Manual Prescaler The prescaler can divide the counter clock frequency by any factor between 1 ~ 65536, and this is achieved with a 16-bit counter controlled by a 16-bit register (in the TMRx_DIV register). Its value can be changed on the fly since the control register is buffered. The new prescaler ratio takes effect at the next update event.
  • Page 173 AT32F415 Series Technical Manual An update event can be generated at each counter overflow; setting the UEVG bit in the TMRx_EVEG register (by software or by using the slave mode controller) also generates the update events. Update events can be disabled by setting the UEVDIS bit in the TMRx_CTRL1 register. This avoids changing the shadow registers while writing new values to the preload registers.
  • Page 174 AT32F415 Series Technical Manual Figure 10-16 Counter Timing Diagram with Internal Clock Divided by 4 0035 0036 0000 0001 Figure 10-17 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-18 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not...
  • Page 175 AT32F415 Series Technical Manual Figure 10-19 Counter Timing Diagram with Update Event When ARPEN = 1 (TMRx_AR is Preloaded) CK_DIV CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Auto-reload shadow register Writing new values to the TMRx_AR register Downcounting mode...
  • Page 176 AT32F415 Series Technical Manual Figure 10-20 Counter Timing Diagram with Internal Clock Divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow (cnt_overflow) Update event (UEV) Update interrupt flag (UEVIF) Figure 10-21 Counter Timing Diagram with Internal Clock Divided by 2 CK_INT CNT_EN Timer clock = CK_CNT...
  • Page 177 AT32F415 Series Technical Manual Figure 10-23 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-24 Counter Timing Diagram with Update Event When ARPEN = 0 CK_INT CNT_EN Timer clock = CK_CNT...
  • Page 178 AT32F415 Series Technical Manual without setting the UEVIF flag (so no interrupt or DMA request is generated). This can avoid generating both update and capture interrupts when the capture event occurs and the counter is cleared. When an update event occurs, all the registers are updated, and the update flag bit (the UEVIF bit in the TMRx_STS register) is set (according to the UEVRS bit).
  • Page 179 AT32F415 Series Technical Manual CK_INT CNT_EN Timer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-27 Counter Timing Diagram with Internal Clock Divided by 4, TMRx_AR = 0x36 CK_INT CNT_EN...
  • Page 180 AT32F415 Series Technical Manual Figure 10-29 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Writing new values to the TMRx_AR register Active auto-reload register Figure 10-30 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter overflow)
  • Page 181 AT32F415 Series Technical Manual automatically). As soon as the CNTEN bit is written ‘1’, the prescaler is clocked by the internal clock CK_INT. Figure 10-31 shows the behavior of the control circuit and the up counter in normal mode, without prescaler.
  • Page 182 AT32F415 Series Technical Manual Figure 10-32 TI2 External Clock Connection Example TMRx_SMC TRGSEL[2:0] TI2F TI1F ITRx Encoder mode TI1_ED TRGI TI2F_Rising TI1FP1 External clock mode 1 TI2FP2 Edge Filter CK_DIV ETRF detector External clock TI2F_Falling ETRF mode 2 CK_INT Internal clock mode IC2DF[3:0] (Internal clock)...
  • Page 183 AT32F415 Series Technical Manual This mode is selected by writing ECLKEN = 1 in the TMRx_SMC register. The counter can count at each rising or falling edge on the external trigger ETR. Figure 10-34 shows the block diagram of the external trigger input. Figure 10-34 Block Diagram of External Trigger Input TI2F TI1F...
  • Page 184 AT32F415 Series Technical Manual an edge detector with polarity selection generates a signal (TIxFPx) which can be the trigger input for the slave mode controller, or be the capture command. This signal enters the capture register through the prescaler. Figure 10-36 Capture/Compare Channel (e.g. Channel 1 Input Stage) TI1F_ED To the salve mode controller...
  • Page 185 AT32F415 Series Technical Manual Figure 10-38 Capture/Compare Channel Output Stage (Channel 1) To the master mode controller Output enable ETRF circuit CNT>CC1 Output OC4REF TMR1_CCE mode CNT = CC1 controller C1EN TMR1_CCE OC1MODE[2:0] TMR1_CCM1 2020.06.28 Page 185 Version 1.02...
  • Page 186 AT32F415 Series Technical Manual The capture/compare block is made of one preload register and one shadow register. Write and read only access the preload register. In capture mode, captures are actually done in the shadow register, and then copied into the preload register.
  • Page 187 AT32F415 Series Technical Manual  One of the two TIxFP signals is used as trigger input signal and the slave mode controller is configured as reset mode. For example, if users need to measure the period (the TMRx_CC1 register) and the duty cycle (the TMRx_CC2 register) of the PWM signal input on TI1, the procedure is as follows (depending on CK_INT frequency and prescaler value): ...
  • Page 188 AT32F415 Series Technical Manual ongoing, and the corresponding flag is also modified. Accordingly, the corresponding interrupt and DMA requests are still generated. This will be described in the “Output Compare Mode” section. 9.2.3.8 Output Compare Mode This function is used to control an output waveform or to indicate that a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function proceeds as follows: ...
  • Page 189 AT32F415 Series Technical Manual Write B201h in the CC1 register TMR1_CNT 0039 003A 003B B200 B201 TMR1_CC1 003A B201 OC1REF = OC1 Match detected on CC1 Interrupt generated if enabled 9.2.3.9 PWM Mode Pulse width modulation mode can generate a signal with its frequency determined by the TMRx_AR register and its duty cycle determined by TMRx_CCx register.
  • Page 190 AT32F415 Series Technical Manual Figure 10-41 Edge-aligned PWM Waveforms (AR = 8) Downcounting configuration Downcounting is active when the DIR bit in the TMRx_CTRL1 register is high. Please refer to Section 10.2.3.2. In PWM mode 1, the reference signal, OCxREF, is low once MRx_CNT > TMRx_CCx; else, it becomes high.
  • Page 191 AT32F415 Series Technical Manual Figure 10-42 Center-aligned PWM Waveforms (AP = 8) Counter register OCxREF CMSEL = 01 CCx = 4 CCxIF CMSEL = 10 CMSEL = 11 OCxREF CCx = 7 CMSEL = 01 CMSEL = 10 CCxIF CMSEL = 11 ‘1’...
  • Page 192 AT32F415 Series Technical Manual 9.2.3.10One-pulse Mode One-pulse mode (OPM) is quite different from the above-mentioned modes. It allows the counter to respond to a stimulus and to generate a pulse with a programmable length after a programmable delay. The counter can be enabled through the slave mode controller, generating waveforms in output compare mode or PWM mode.
  • Page 193 AT32F415 Series Technical Manual one pulse is needed, '1’ must be written to the OPMODE bit in the TMRx_CTRL1 register to stop the counter at the next update event (when the counter rolls over to 0 from the auto-reload value). Special case: OCx fast enable In one-pulse mode, the counter is enabled by setting the CNTEN bit on the edge detection logic of TIx input pin.
  • Page 194 AT32F415 Series Technical Manual Users can program the input filter as well when it is needed. The two inputs, TI1 and TI2, are used as the interface of incremental encoder. Please refer to Table 10-2. If the counter is enabled (CNTEN = ‘1’ in the TMRx_CTRL1 register), it is clocked by each valid transition on TI1FP1 or TI2FP2.
  • Page 195 AT32F415 Series Technical Manual Figure 10-45 Example of Counter Operation in Encoder Interface Mode jitter jitter forward forward backward counter down Figure 10-46 is an example of counter behavior when IC1FP1 polarity is inverted (the same configuration as the above example, except for C1P = ‘1’). Figure 10-46 Example of Encoder Interface Mode with IC1FP1 Polarity Inverted The timer, when configured as encoder interface mode, provides information on the sensor’s current position.
  • Page 196 AT32F415 Series Technical Manual preloaded registers (TMRx_AR, TMRx_CCx) will be updated. In the following example, the up counter is cleared due to a rising edge on TI1 input:  Configure channel 1 to detect the rising edges on TI1. Configure the input filter duration (in this example, no filter is needed, so keep IC1DF = 0000).
  • Page 197 AT32F415 Series Technical Manual Figure 10-48 Control Circuit in Gated Mode Slave mode: Trigger mode The counter can be enabled according to the selected level of input. In the following example, the counter starts to count up at rising edge on TI2 input: ...
  • Page 198 AT32F415 Series Technical Manual In the following example, as soon as a rising edge of TI1 occurs, the counter counts up once at each rising edge of the ETR signal: 1. Configure the external trigger input circuit through the TMRx_SMC register: ─...
  • Page 199 AT32F415 Series Technical Manual For example, the user can configure Timer 1 to act as a prescaler for Timer 2. Please refer to Figure 10- 51, and use the following procedure:  Configure Timer 1 as master mode so that it can output a periodic trigger signal on each update event UEV.
  • Page 200 AT32F415 Series Technical Manual In the following example, Timer 1 and Timer 2 need to be synchronized. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers.
  • Page 201 AT32F415 Series Technical Manual  Set CNTEN = 1 in the TMR1_CTRL1 register to start Timer 1. Figure 10-54 Using Timer 1 Update to Trigger Timer 2 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN = CNT_EN TIMER2-TRGIF Write TRGIF = 0 As in the above example, both counters can be initialized before starting counting. Figure 10-55 shows the behavior with the same configuration as the above example, but using trigger mode instead of gated mode (SMSEL = 110 in the TMR2_SMC register).
  • Page 202 AT32F415 Series Technical Manual  Configure Timer 2 to use external clock mode (SMSEL = 111 in the TMR2_SMC register)  Set CNTEN = 1 in the TMR1_CTRL2 register to start Timer 2.  Set CNTEN = 1 in the TMR1_CTRL1 register to start Timer 1. Starting two timers synchronously by an external trigger In this example, when Timer 1 TI1 input rises, enable Timer 1, and at the same time Timer 2 is enabled.
  • Page 203 AT32F415 Series Technical Manual 9.2.4 TMRx Registers Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 10-3, all the TMRx registers are mapped to a 16-bit addressable space. TMRx – Register Table and Reset Values Table 10-3 Offset Register...
  • Page 204 AT32F415 Series Technical Manual TMRx_ CCM2 Input Reserved Capture mode Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_ Reser Reser Reser 0x20 Reserved Reset Value TMRx_CNT CNT[31:16] CNT[15:0] 0x24 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_DIV DIV[15:0]...
  • Page 205 AT32F415 Series Technical Manual CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency and sampling frequency used by the digital filters (ETR, TIx). 00: t Bit 9:8 ������ ����_������ 01: t = 2 x t ������ ����_������...
  • Page 206 AT32F415 Series Technical Manual 9.2.4.2 Control Register 2 (TMRx_CTRL2) Address offset: 0x04 Reset value: 0x0000 TI1S Reserved MMSEL[2:0] Reserved Bit 15:8 Reserved. Always read as 0. TI1SEL: TI1 selection 0: TMRx_CH1 pin is connected to TI1 input. Bit 7 1: TMRx_CH1, TMRx_CH2, and TMRx_CH3 pins are connected to the TI1 input after XORed.
  • Page 207 AT32F415 Series Technical Manual ECLKEN: External clock enable This bit enables external clock mode 2. 0: External clock mode 2 is disabled 1: External clock mode 2 is enabled. The counter is clocked by any active edge on the ETRF signal. Note 1: Setting the ECLKEN bit has the same effect as selecting external clock mode 1 Bit 14 with TRGI connected to ETRF (SMSEL = 111 and TRGSEL = 111).
  • Page 208 AT32F415 Series Technical Manual SMSEL[2:0]: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is relevant to the selected external input polarity (Please refer to input control register and control register description.) 000: Slave mode is disabled - If CNTEN = 1, the prescaler is clocked directly by the internal clock.
  • Page 209 AT32F415 Series Technical Manual C2DE: Capture/Compare 2 DMA request enable Bit 10 0: Capture/Compare 2 DMA request is disabled. 1: Capture/Compare 2 DMA request is enabled. C1DE: Capture/Compare 1 DMA request enable Bit 9 0: Capture/Compare 1 DMA request is disabled. 1: Capture/Compare 1 DMA request is enabled.
  • Page 210 AT32F415 Series Technical Manual TRGIF: Trigger interrupt flag This flag is set by hardware on trigger event (When the slave mode controller is in all modes except for gated mode, active edge is detected on TRGI input, or any edge in Bit 6 the gated mode).
  • Page 211 AT32F415 Series Technical Manual C3G: Capture/Compare 3 generation Bit 3 Please refer to C1G description. C2G: Capture/Compare 2 generation Bit 2 Please refer to C1G description. C1G: Capture/Compare 1 generation This bit is set by software to generate a capture/compare event. It is cleared automatically by hardware.
  • Page 212 AT32F415 Series Technical Manual OC1DIS: Output compare 1 clear enable Bit 7 0: OC1REF is not affected by ETRF input. 1: Once high level is detected on ETRF input, clear OC1REF = 0. OC1MODE[2:0]: Output compare 1 enable The bits define the behavior of the output reference signal OC1REF, and OC1REF determines OC1 value.
  • Page 213 AT32F415 Series Technical Manual C2SEL[1:0]: Capture/Compare 2 selection The bits define the channel direction (input/output), and input pin selection: 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. Bit 9:8 11: CC2 channel is configured as input, IC2 is mapped on TRC.
  • Page 214 AT32F415 Series Technical Manual C4SEL[1:0]: Capture/Compare 4 selection The bits define the channel direction (input/output), and input pin selection: 00: CC4 channel is configured as output. 01: CC4 channel is configured as input, IC4 is mapped on TI4. 10: CC4 channel is configured as input, IC4 is mapped on TI3. Bit 9:8 11: CC4 channel is configured as input, IC4 is mapped on TRC.
  • Page 215 AT32F415 Series Technical Manual 9.2.4.9 Capture/Compare Enable Register (TMRx_CCE) Address offset: 0x20 Reset value: 0x0000 Reserved Reserved Reserved Reserved Bit 15:14 Reserved. Always read as 0. C4P: Capture/Compare 4 output polarity Bit 13 Please refer to C1P description. C4EN: Capture/Compare 4 output enable Bit 12 Please refer to C1EN description.
  • Page 216 AT32F415 Series Technical Manual Note: The state of the external I/O pins connected to the standard OCx channels is determined by the OCx channel state and the GPIO and AFIO registers. 9.2.4.10Counter (TMRx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[31:16] CNT[15:0] CNT[31:16]: Counter value Bit 31:16...
  • Page 217 AT32F415 Series Technical Manual 9.2.4.13Capture/Compare Register 1 (TMRx_CC1) Address offset: 0x34 Reset value: 0x0000 CC1[31:16] CC1[15:0] CC1[31:16]: Capture/Compare 1 value Bit 31:16 When TMR2 or TMR5 enables plus mode (The PMEN bit in the TMR_CTRL1 register), CC1 is expanded to 32 bits. CC1[15:0]: Capture/Compare 1 value If CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value).
  • Page 218 AT32F415 Series Technical Manual 9.2.4.15Capture/Compare Register 3 (TMRx_CC3) Address offset: 0x3C Reset value: 0x0000 CC3[31:16] CC3[15:0] CC3[31:16]: Capture/Compare 3 value Bit 31:16 When TMR2 or TMR5 enables plus mode (The PMEN bit in the TMR_CTRL1 register), CC3 is expanded to 32 bits. CC3[15:0]: Capture/Compare 3 value If CC3 channel is configured as output: CC3 is the value to be loaded in the actual capture/compare 3 register (preload value).
  • Page 219 AT32F415 Series Technical Manual 9.2.4.17DMA Control Register (TMRx_DMAC) Address offset: 0x48 Reset value: 0x0000 Reserved DBLEN[4:0] Reserved ADDR[4:0] Bit 15:13 Reserved. Always read as 0. DBLEN[4:0]: DMA burst length The bits define the number of DMA transfers in burst mode (the timer recognizes a burst transfer when a read or a write access is done to the TMRx_DMABA address).
  • Page 220 AT32F415 Series Technical Manual General-purpose Timer (TMR9 to TMR14) 9.3.1 TMRx Introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
  • Page 221 AT32F415 Series Technical Manual Figure 10-57 Block Diagram of General-purpose Timer TMR9/12 Internal clock (CK_INT) TMRxCLK from RCC Trigger controller ITR0 ITR1 ITR2 Slave mode TRGI ITR3 controller TI1F_ED Reset, enable, TI1FP1 up counting TI2FP2 Auto-reload register Stop, clear CK_CNT CK_DIV +/- CNT counter prescaler...
  • Page 222 AT32F415 Series Technical Manual Figure 10-58 Block Diagram of General-purpose Timers TMR10/11/13/14 Internal clock (CK_INT) Trigger TMRxCLK from RCC controller Enable couting Auto-reload register Stop, clear CK_DIV CK_CNT +/- CNT Counter prescaler CC1I CC1I TI1FP1 Input filter and IC1PS OC1REF Output TMRX_CH1 prescaler...
  • Page 223 AT32F415 Series Technical Manual Figure 10-59 Counter Timing Diagram with Prescaler Division Changing from 1 to 2 CK_DIV CNT_EN Timer clock = CK_CNT Counter register Update event (UEV) Prescaler control register Write new values to the TMRx_DIV register Prescaler buffer Prescaler counter Figure 10-60 Counter Timing Diagram with Prescaler Division Changing from 1 to 4 CK_DIV...
  • Page 224 AT32F415 Series Technical Manual changing the shadow registers while writing new values to the preload registers. No update event occurs until the UEVDIS bit is cleared. However, when the update events are generated, the counter and the prescaler are still cleared (but the prescaler ratio does not change). In addition, if the UEVRS (update request selection) bit in the TMRx_CTRL1 register is set, setting the UEVG bit generates an update event UEV, but the UEVIF flag is not set by hardware (that is, no interrupt is sent).
  • Page 225 AT32F415 Series Technical Manual Figure 10-63 Counter Timing Diagram with Internal Clock Divided by 4 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Figure 10-64 Counter Timing Diagram with Internal Clock Divided by N CK_INT Timer clock = CK_CNT Counter register...
  • Page 226 AT32F415 Series Technical Manual Figure 10-66 Counter Timing Diagram with Update Event When ARPEN = 1 (TMRx_AR is Preloaded) CK_DIV CNT_EN Timer clock = CK_CNT Counter reigster Counter overflow Update event (UEV) Update interrupt flag (UEVIF) Auto-reload register Auto-reload shadow register Write new values to the TMRx_AR register 9.3.3.3...
  • Page 227 AT32F415 Series Technical Manual CK_INT CNTEN = CNT_EN UEVG CNT_INIT Counter clock = CK_CNT = CK_DIV Counter register External clock mode 1 (TMR9 and TMR12) This mode is selected when SMSEL = 111 in the TMRx_SMC register. The counter can count at each rising or falling edge on a selected input.
  • Page 228 AT32F415 Series Technical Manual Figure 10-69 Control Circuit in External Clock Mode 1 CNT_EN Counter clock = CK_CNT = CK_DIV Counter register TRGIF Write TRGIF = 0 9.3.3.4 Capture/Compare Channel Each capture/compare channel is built around a capture/compare register (including a shadow register), also an input stage for capture (digital filter, multiplexing, and prescaler) and an output stage (comparator and output control).
  • Page 229 AT32F415 Series Technical Manual Figure 10-71 Capture/Compare Channel 1 Main Circuit APB bus MCU peripheral interface high Write CC1H Read CC1H read_in_progress write_in_progress Capture/Compare preload register Read CC1L Write CC1L capture_transfer capture_transfer Input C1SEL mode C1SEL Input C1SEL mode Capture/Compare shadow register C1SEL OC1PEN OC1PEN...
  • Page 230 AT32F415 Series Technical Manual only.  Program the desired input filter duration according to the input signal (if the input is TIx, the control bit of the input filter is the ICxDF bit in the TMRx_CCMx register). If the input signal is not stable during five internal clock cycles at most, the filter duration should be configured longer than five clock cycles.
  • Page 231 AT32F415 Series Technical Manual Figure 10-73 PWM Input Mode Timing TMRx_CNT 0004 0000 0001 0002 0003 0004 0000 0004 TMRx_CC1 0002 TMRx_CC2 IC2 capture IC1 capture IC1 capture period pulse width IC2 capture measurement measurement Reset counter Since only TI1FP1 and TI2FP2 are connected to the slave mode controller, the PWM input mode can be used only with the TMRx_CH1/TMRx_CH2 signals.
  • Page 232 AT32F415 Series Technical Manual 1. Select the counter clock (internal, external, and prescaler). 2. Write the corresponding data to the TMRx_AR and the TMRx_CCx registers. 3. Set the CxIE and/or CxDE bits if an interrupt and/or DMA request is to be generated. 4.
  • Page 233 AT32F415 Series Technical Manual Figure 10-75 Edge-aligned PWM Waveforms (AR = 8) 9.3.3.10One-pulse Mode One-pulse mode (OPM) is quite different from the above-mentioned modes. It allows the counter to respond to a stimulus and to generate a pulse with a programmable length after a programmable delay.
  • Page 234 AT32F415 Series Technical Manual  Write SMSEL = ‘110’ in the TMRx_SMC register (trigger mode), and TI2FP2 is used to enable the counter. The OPM waveform is defined by the value written to the compare registers (the clock frequency and the counter prescaler should be taken into account). ...
  • Page 235 AT32F415 Series Technical Manual auto-reload register TMRx_AR = 0x36. The delay between the rising edge on TI1 and the actual reset of the counter is determined by the resynchronization circuit on TI1 input. Figure 10-77 Control Circuit in Reset Mode Slave mode: Gated mode The counter can be enabled according to the selected level of input.
  • Page 236 AT32F415 Series Technical Manual Slave mode: Trigger mode The counter can be enabled according to the selected level of input. In the following example, the counter starts to count up at rising edge on TI2 input:  Configure channel 2 to detect the rising edge on TI2. Configure the input filter duration (in this example, no filter is needed, so keep IC1DF = 0000).
  • Page 237 AT32F415 Series Technical Manual For more details, please refer to Section 22.2.2. 9.3.4 TMR9 and TMR12 Register Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 10-6, all the TMRx registers are mapped to a 16-bit addressable space. TMRx –...
  • Page 238 AT32F415 Series Technical Manual TMRx_DIV DIV[15:0] 0x28 Reserved 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_AR AR[15:0] 0x2C Reserved 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_CC1 CC1[15:0] 0x34...
  • Page 239 AT32F415 Series Technical Manual 9.3.4.1 Control Register 1 (TMRx_CTRL1) Address offset: 0x00 Reset value: 0x0000 ARPE UEVR UEVD CNTE Reserved Reserved CLKDIV [1:0] Bit 15:10 Reserved. Always read as 0. CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency and sampling frequency used by the digital filters (ETR, TIx).
  • Page 240 AT32F415 Series Technical Manual TRGSEL[2:0]: Trigger selection The bits select the trigger input used to synchronize the counter. 000: Internal trigger 0 (ITR0) 100: TI1 edge detector (TI1F_ED) 001: Internal trigger 1 (ITR1) 101: Filtered timer input 1 (TI1FP1) Bit 6:4 010: Internal trigger 2 (ITR2) 110: Filtered timer input 2 (TI2FP2) 011: Internal trigger 3 (ITR3) 111: Reserved Please refer to...
  • Page 241 AT32F415 Series Technical Manual C2IE: Capture/Compare 2 interrupt enable Bit 2 0: Capture/Compare 2 interrupt is disabled. 1: Capture/Compare 2 interrupt is enabled. C1IE: Capture/Compare 1 interrupt enable Bit 1 0: Capture/Compare 1 interrupt is disabled. 1: Capture/Compare 1 interrupt is enabled. UEVIE: Update interrupt enable Bit 0 0: Update interrupt is disabled.
  • Page 242 AT32F415 Series Technical Manual UEVIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update event occurs. 1: Update interrupt is pending. This bit is set by hardware when the registers are updated: −...
  • Page 243 AT32F415 Series Technical Manual Output compare mode: erve OC2MODE[2:0] C2SEL[1:0] erve OC1MODE[2:0] C1SEL[1:0] Bit 15 OC2DIS: Reserved. Bit 14:12 OC2MODE[2:0]: Output compare 2 mode Bit 11 OC2PEN: Output compare 2 preload enable OC2FEN: Output compare 2 fast enable Bit 10 C2SEL[1:0]: Capture/Compare 2 selection This bit defines the channel direction (input/output) and the selection of input pin: 00: CC2 channel is configured as output.
  • Page 244 AT32F415 Series Technical Manual C1SEL[1:0]: Capture/Compare 1 selection The bits define the channel direction (input/output), and input pin selection: 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. Bit 1:0 11: CC1 channel is configured as input, IC1 is mapped on TRC.
  • Page 245 AT32F415 Series Technical Manual 9.3.4.7 Capture/Compare Enable Register (TMRx_CCE) Address offset: 0x20 Reset value: 0x0000 Reserved erve erve Bit 15:8 Reserved. Always read as 0. C2NP: Capture/Compare 2 output polarity Bit 7 Please refer to C1NP description. Bit 6 Reserved. Always read as 0. C2P: Capture/Compare 2 output polarity Bit 5 Please refer to C1P description.
  • Page 246 AT32F415 Series Technical Manual Note: The state of the external I/O pins connected to the standard OCx channels is determined by the OCx channel state and the GPIO and AFIO registers. 9.3.4.8 Counter (TMRx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] CNT[15:0]: Counter value Bit 15:0...
  • Page 247 AT32F415 Series Technical Manual CC1[15:0]: Capture/Compare 1 value If CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value). The written value is loaded immediately to the active register if the preload feature is not selected in the TMRx_CCM1 register (the OC1PEN bit).
  • Page 248 AT32F415 Series Technical Manual TMRx_ CCM1 output Reserved compare mode Reset Value 0 0 0 0 0 0 0 0x18 TMRx_ CCM1 input IC1DF[3:0] Reserved capture mode Reset Value 0 0 0 0 0 0 0 0 TMRx_CCE 0x20 Reserved Reset Value TMRx_CNT CNT[15:0]...
  • Page 249 AT32F415 Series Technical Manual UEVRS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt request if update interrupt is enabled: Bit 2 −...
  • Page 250 AT32F415 Series Technical Manual C1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output mode: This flag is set by hardware when the counter value matches the compare value. It is cleared by software. 0: No match 1: The TMRx_CNT value matches the TMRx_CC1 value. C1F is only ‘1’ at counter Bit 1 overflow.
  • Page 251 AT32F415 Series Technical Manual 9.3.5.4 Event Generation Register (TMRx_EVEG) Address offset: 0x14 Reset value: 0x0000 Reserved Bit 15:2 Reserved. Always read as 0. C1G: Capture/Compare 1 generation This bit is set by software to generate a capture/compare event. It is cleared automatically by hardware.
  • Page 252 AT32F415 Series Technical Manual OC1MODE[2:0]: Output compare 1 enable The bits define the behavior of the output reference signal, OC1REF, and OC1REF determines the OC1 value. OC1REF is active high, while the active level of OC1 is determined by the C1P bit. 000: Frozen.
  • Page 253 AT32F415 Series Technical Manual IC1DF[3:0]: Input capture 1 filter The bits define the frequency used to sample TI1 input and the length of digital filter. The digital filter is an event counter which records N consecutive events that are needed to generate a transition on the output: 0000: No filter, sampling is done at f 1000: f...
  • Page 254 AT32F415 Series Technical Manual C1EN: Capture/Compare 1 output enable CC1 channel is configured as output: 0: OFF- OC1 output is disabled. 1: ON- OC1 is outputted on the corresponding output pin. Bit 0 CC1 channel is configured as input: This bit determines whether the counter value can be captured to TMRx_CC1 register. 0: Capture is disabled.
  • Page 255 AT32F415 Series Technical Manual CC1[15:0] CC1[15:0]: Capture/Compare 1 value If CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value). The written value is loaded immediately to the active register if the preload feature is not selected in the TMRx_CCM1 register (the OC1PEN bit).
  • Page 256 AT32F415 Series Technical Manual Advanced-control Timer (TMR1, TMR8, and TMR15) 9.4.1 TMR1, TMR8, and TMR15 Introduction The advanced-control timer (TMR1, TMR8, and TMR15) consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, embedded dead-time, and complementary PWM, and so on).
  • Page 257 AT32F415 Series Technical Manual Figure 10-80 Block Diagram of Advanced-control Timer Output control Internal clock(CK_INT) To other timers Trigger CK_TMR from RCC To DAC/ADC ETRF Polarity selection, controller ETRP TMRX_ETR edge detection, and Input filter TRGO prescaler ITR0 Slave mode TRGI ITR1 controller...
  • Page 258 AT32F415 Series Technical Manual enable bit (CNTEN) in the TMRx_CTRL1 register is set. (Please refer to the controller slave mode descriptions for more details on counter enable.) Please note that after the CNTEN bit in the TMRx_CTRL register is set, the counter starts counting after one clock cycle.
  • Page 259 AT32F415 Series Technical Manual In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TMRx_AR counter), and restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting reaches the programmed count in the repetition counter register (TMRx_RC).
  • Page 260 AT32F415 Series Technical Manual Figure 10-84 Counter Timing Diagram with Internal Clock Divided by 2 CK_DIV CNT_EN Timer clock = CK_CNT Counter register 0002 0034 0035 0036 0001 0003 0004 Counter overflow Update event Update interrupt flag (UEVIF) Figure 10-85 Counter Timing Diagram with Internal Clock Divided by 4 CK_INT CNT_EN Timer clock = CK_CNT...
  • Page 261 AT32F415 Series Technical Manual Figure 10-87 Counter Timing Diagram with Update Event When ARPEN = 0 (TMRx_AR Not Preloaded) CK_DIV CNTEN Timer clock = CK_CNT Counter register Counter overflow Update event Update interrupt flag (UEVIF) Auto-reload register Write new values to the TMRx_AR register Figure 10-88 Counter Timing Diagram with Update Event When ARPEN = 1 (TMRx_AR is Preloaded) CK_DIV CNTEN...
  • Page 262 AT32F415 Series Technical Manual event occurs until the UEVDIS bit is cleared. However, the counter still counts from the current auto- reload value, and the prescaler counter restarts from 0 (but the prescaler ratio does not change). In addition, if the UEVRS (update request selection) bit in the TMRx_CTRL1 register is set, setting the UEVG bit generates an update event UEV, but the UEVIF flag is not set (so no interrupt or DMA request is generated).
  • Page 263 AT32F415 Series Technical Manual Figure 10-91 Counter Timing Diagram with Internal Clock Divided by 4 0001 0000 0036 0035 Figure 10-92 Counter Timing Diagram with Internal Clock Divided by N CK_DIV Timer clock CK_CNT Counter register Counter overflow Update event Update interrupt flag (UEVIF) Figure 10-93 Counter Timing Diagram of Update Event without Auto-reload...
  • Page 264 AT32F415 Series Technical Manual register) – 1, generates a counter overflow event, and counts from the auto-reload value down to 1 and generates a counter underflow event. Then, it restarts counting from 0. In this mode, the DIR direction bit in the TMRx_CTRL1 register cannot be written. It is updated by hardware and indicates the current counting direction.
  • Page 265 AT32F415 Series Technical Manual Figure 10-95 Counter Timing Diagram with Internal Clock Divided by 2 CK_DIV CNT_EN Timer clock = CK_CNT Counter register 0001 0003 0002 0001 0000 0002 0003 Counter underflow Update event Update interrupt flag (UEVIF) Figure 10-96 Counter Timing Diagram with Internal Clock Divided by 4, TMRx_AR = 0x36 CK_INT CNT_EN...
  • Page 266 AT32F415 Series Technical Manual Figure 10-98 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter underflow) CK_DIV CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event Update interrupt flag (UEVIF) Auto-reload register Write new values to the TMRx_AR register Active auto-reload register value Figure 10-99 Counter Timing Diagram with Update Event When ARPEN = 1 (Counter overflow)
  • Page 267 AT32F415 Series Technical Manual register, also capture/compare registers (TMRx_CCx in compare mode), where N is the value in the TMRx_RC repetition counter register. The repetition counter is decremented under any of the following conditions:  At each counter overflow in upcounting mode ...
  • Page 268 AT32F415 Series Technical Manual For example, users can configure Timer 1 to act as the prescaler for Timer 2. Please refer to Section 10.4.3.20 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMSEL = 000), the CNTEN, DIR (in the TMRx_CTRL1 register), and UEVG bits (in the TMRx_EVEG register) are the actual control bits, and they can be changed only by software (except for the UEVG bit, which will be cleared automatically).
  • Page 269 AT32F415 Series Technical Manual 4. Select the timer external clock mode 1 by writing SMSEL = ‘111’ in the TMRx_SMC register. 5. Select TI2 as the trigger input source by writing TRGSEL = ‘110’ in the TMRx_SMC register. 6. Enable the counter by writing CNTEN = ‘1’ in the TMRx_CTRL1 register. Note: The capture prescaler is not used as trigger, so it does not need to be configured.
  • Page 270 AT32F415 Series Technical Manual The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter depends on the resynchronization circuit on the ETRP signal. Figure 10-105 Control Circuit in External Clock Mode 2 CK_INT CNT_EN ETRP...
  • Page 271 AT32F415 Series Technical Manual Figure 10-107 Capture/Compare Channel 1 Main Circuit APB bus MCU peripheral interface high Read CC1H read_in_progress Write CC1H write_in_progress Capture/Compare preload register Read CC1L Write CC1L Input capture_transfer capture_transfer mode C1SEL C1SEL Input mode C1SEL Capture/Compare shadow register C1SEL OC1PEN OC1PEN...
  • Page 272 AT32F415 Series Technical Manual In capture mode, captures are actually done in the shadow register, and then copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register, and then the content of the shadow register is compared with the counter. 9.4.3.6 Input Capture Mode In input capture mode, the capture/compare registers (TMRx_CCx) latch the current counter value...
  • Page 273 AT32F415 Series Technical Manual For example, if users need to measure the period (TMRx_CC1 register) and the duty cycle (TMRx_CC2 register) of the PWM signal input on TI1, the procedure is as follows (depending on CK_INT frequency and prescaler value): ...
  • Page 274 AT32F415 Series Technical Manual When a match is found between the capture/compare register and the counter, the output compare function proceeds as follows:  Output the value defined by the output compare mode (the OCxMODE bit in the TMRx_CCMx register) and the output polarity (the CxP bit in the TMRx_CCE register) to the corresponding pin.
  • Page 275 AT32F415 Series Technical Manual 9.4.3.10PWM Mode Pulse width modulation mode can generate a signal with its frequency determined by the TMRx_AR register and its duty cycle determined by TMRx_CCx register. Writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxMODE bit in the TMRx_CCMx register can independently configure each OCx output channel and generate single-channel PWM.
  • Page 276 AT32F415 Series Technical Manual other configurations have the same effect on the OCxREF/OCx signals). According to different CMSEL bit configurations, the compare flag is set when the counter counts up, counts down, or counts both up and down. The direction bit (DIR) in the TMRx_CTRL1 register is updated by hardware and must not be changed by software.
  • Page 277 AT32F415 Series Technical Manual 9.4.3.11 Complementary Output and Dead-time Insertion The advanced-control timers (TMR1, TMR8, and TMR15) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time. Users can adjust dead-time according to the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays resulted from power switches, etc.) Setting the CxP and CxNP bits in the TMRx_CCE register can select the polarity (main output OCx or complementary OCxN) for each output independently.
  • Page 278 AT32F415 Series Technical Manual Figure 10-116 Dead-time Waveform Delay W hich is Greater than Positive Pulse The dead-time delay is the same for each channel, and is programmable with the DTGS bits in the TMRx_BRKDT register. Please refer to Section 10.4.4.18 for delay calculation.
  • Page 279 AT32F415 Series Technical Manual enable output, else the enable output remains high .  When complementary outputs are used: ─ The outputs are first put at reset state, namely, inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.
  • Page 280 AT32F415 Series Technical Manual Figure 10-117 Outputs in Response to a Break Break (MOEN) OCxREF (OCxN not implemented, CxP = 0, OCxIS = 1) (OCxN not implemented, CxP = 0, OCxIS = 0) (OCxN not implemented, CxP = 0, OCxIS = 1) (OCxN not implemented, CxP = 0, OCxIS = 0) Delay OCxN...
  • Page 281 AT32F415 Series Technical Manual The external trigger polarity (ETRGP) and the external trigger filter (ETDF) can be configured according to users’ needs. Figure 10-118 shows how OCxREF signal behaves to respond to different OCxDIS values when the ETRF input becomes high. In this example, the timer TMRx is programmed in PWM mode. Figure 10-118 Clearing OCxREF in TMRx 9.4.3.146-step PWM Output Generation When complementary outputs are used on a channel, preload bits are the OCxMODE, CxEN, and...
  • Page 282 AT32F415 Series Technical Manual Figure 10-119 6-step PWM Generation, Example of Using HALL (OSIMR = 1) Counter (CNT) (CCx) OCxREF Write HALL = 1 HALL event Write CxEN = 1 CxNEN = 0 OCxMODE = 100 CxEN = 1 OCxMODE = 100 CxNEN = 0 (Forced inactive) OCxMODE = 100...
  • Page 283 AT32F415 Series Technical Manual Figure 10-120 One-pulse Mode Example OC1REF TMR1_AR Counter TMR1_CC1 DELAY PULSE For example, if users want to generate a positive pulse with a length of t on OC1 once a rising PULSE edge is detected on the TI2 input pin and after a delay t DELAY If TI2FP2 is used as trigger 1: ...
  • Page 284 AT32F415 Series Technical Manual delay. In this case, OCxREF (and OCx) are forced to respond to the stimulus, instead of relying on the comparison result. The waveform outputted is the same as the one being compared and matched. OCxFEN acts only if the channel is configured as PWM1 or PWM2 mode. 9.4.3.16Encoder Interface Mode To select the encoder interface mode, write SMSEL = 001 in the TMRx_SMC register if the counter is counting on TI2 edges only;...
  • Page 285 AT32F415 Series Technical Manual  SMSEL = ‘011’ (TMRx_SMC register, all inputs are active on both rising and falling edges.)  CNTEN = ‘1’ (TMRx_CTRL1 register, counter enabled) Figure 10-121 Example of Counter Operation in Encoder Interface Mode Figure 10-122 is an example of counter behavior when IC1FP1 polarity is inverted (the same configuration as the above example, except for C1P = ‘1’).
  • Page 286 AT32F415 Series Technical Manual When using the advanced-control timer (TMR1, TMR8, or TMR15) to generate PWM signal which drives the motor, another timer general-purpose timer TMRx (TMR2, TMR3, TMR4, orTMR5) can function as “interfacing timer” to connect Hall sensors. Please refer to Figure 10-123.
  • Page 287 AT32F415 Series Technical Manual Figure 10-123 Example of HALL Sensor Interface Counter (CNT) (CC2) C7A3 C7A8 C794 C7A5 C7AB C796 TRGO = OC2REF HALL OCIN OC2N OC3N Write CxEN, CxNEN, and OCxMODE for the next step 9.4.3.19TMRx Timer and External Trigger Synchronization The TMRx timer can be synchronized with an external trigger in several modes: reset mode, gated mode, and trigger mode.
  • Page 288 AT32F415 Series Technical Manual  Configure the timer as reset mode by writing SMSEL = 100 in the TMRx_SMC register. Select TI1 as the input source by writing TRGSEL = 101 in the TMRx_SMC register.  Start the counter by writing CNTEN = 1 in the TMRx_CTRL1 register. The counter starts counting on the internal clock, and runs normally until TI1 rising edge occurs;...
  • Page 289 AT32F415 Series Technical Manual Figure 10-125 Control Circuit in Gated Mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 35 36 37 38 TRGIF Write TRGIF = 0 Slave mode: Trigger mode The counter can be enabled according to the selected level of input. In the following example, the counter starts to count up at rising edge on TI2 input: ...
  • Page 290 AT32F415 Series Technical Manual In the following example, as soon as a rising edge of TI1 occurs, the counter counts up once at each rising edge of the ETR signal: 1. Configure the external trigger input circuit through the TMRx_SMC register: ─...
  • Page 291 AT32F415 Series Technical Manual 9.4.4 TMR1, TMR8, and TMR15 Registers Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In Table 10-12, TMR1, TMR8, and TMR15 registers are mapped to a 16-bit addressable space. TMR1, TMR8, and TMR15 –Register Table and Reset Values Table 10-12 Offset Register...
  • Page 292 AT32F415 Series Technical Manual Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_ CCM2 input Reserved compare mode Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRx_CCE 0x20 Reserved...
  • Page 293 AT32F415 Series Technical Manual Bit 15:10 Reserved. Always read as 0. CLKDIV[1:0]: Clock division Define the division ratio between the timer clock (CK_INT) frequency, dead-time, and sampling frequency used by the dead-time generator and digital filters (ETR, TIx). 00: �� = ��...
  • Page 294 AT32F415 Series Technical Manual Address offset: 0x04 Reset value: 0x0000 TI1S erve MMSEL[2:0] erve Bit 15 Reserved. Always read as 0. Bit 14 OC4IS: Output idle state 4 (OC4 output). Please refer to the OC1IS bit. Bit 13 OC3NIS: Output idle state 3 (OC3N output). Please refer to the OC1NIS bit. OC3IS: Output idle state 3 (OC3 output).
  • Page 295 AT32F415 Series Technical Manual CUSEL: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CPC = 1), they are updated only by setting the HALL bit. Bit 2 1: When capture/compare control bits are preloaded (CPC = 1), they are updated by setting the HALL bit or a rising edge on TRGI.
  • Page 296 AT32F415 Series Technical Manual ETDF[3:0]: External trigger filter The bits define the frequency used to sample TETRP signal and the length of ETRP digital filter. In fact, the digital filter is an event counter which records N consecutive events that are needed to generate a transition on the output: 0000: No filter, sampling is done at f 1000: f /8, N = 6...
  • Page 297 AT32F415 Series Technical Manual 9.4.4.4 TMR1, TMR8, and TMR15 DMA/Interrupt Enable Register (TMRx_DIE) Address offset: 0x0C Reset value: 0x0000 Rese BRKI TRGI HALL UEVI C4DE C4IE C3IE C2IE C1IE rved Bit 15 Reserved. Always read as 0. TRGDE: Trigger DMA request enable Bit 14 0: Trigger DMA request is disabled.
  • Page 298 AT32F415 Series Technical Manual UEVIE: Update interrupt enable Bit 0 0: Update interrupt is disabled. 1: Update interrupt is enabled. 9.4.4.5 TMR1, TMR8, and TMR15 Status Register (TMRx_STS) Address offset: 0x10 Reset value: 0x0000 Reserved erve Bit 15:13 Reserved. Always read as 0. C4OF: Capture/Compare 4 overcapture flag Bit 12 Please refer to C1OF description.
  • Page 299 AT32F415 Series Technical Manual C1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output mode: This flag is set by hardware when the counter value matches the compare value, but not in center-aligned mode (Please refer to the CMSEL bits in the TMRx_CTRL1). It is cleared by software.
  • Page 300 AT32F415 Series Technical Manual C3G: Capture/compare 3 generation Bit 3 Please refer to C1G description. C2G: Capture/compare 2 generation Bit 2 Please refer to C1G description. C1G: Capture/compare 1 generation This bit is set by software to generate a capture/compare event. It is cleared automatically by hardware.
  • Page 301 AT32F415 Series Technical Manual OC1DIS: Output compare 1 clear enable Bit 7 0: OC1REF is not affected by ETRF input. 1: Once high level is detected on ETRF input, clear OC1REF = 0. OC1MODE[2:0]: Output compare 1 mode The bits define the behavior of the output reference signal, OC1REF, and OC1REF determines the OC1 and OC1N values.
  • Page 302 AT32F415 Series Technical Manual IC2DF[3:0] IC2DIV[1:0] C2SEL[1:0] IC1DF[3:0] IC1DIV[1:0] C1SEL[1:0] Bit 15:12 IC2DF[3:0]: Input capture 2 filter Bit 11:10 IC2DIV[1:0]: Input capture 2 prescaler C2SEL[1:0]: Capture/Compare 2 selection The bits define the channel direction (input/output), and input pin selection: 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2.
  • Page 303 AT32F415 Series Technical Manual OC4DIS: Output compare 4 clear enable Bit 15 Bit 14:12 OC4MODE[2:0]: Output compare 4 mode Bit 11 OC4PEN: Output compare 4 preload enable Bit 10 OC4FEN: Output compare 4 fast enable C4SEL[1:0]: Capture/Compare 4 selection The bits define the channel direction (input/output), and input pin selection: 00: CC4 channel is configured as output.
  • Page 304 AT32F415 Series Technical Manual Bit 3:2 IC3DIV[1:0]: Input capture 3 prescaler C3SEL[1:0]: Capture/Compare 3 selection The bits define the channel direction (input/output), and input pin selection: 00: CC3 channel is configured as output. 01: CC3 channel is configured as input, IC3 is mapped on TI3. 10: CC3 channel is configured as input, IC3 is mapped on TI4.
  • Page 305 AT32F415 Series Technical Manual C1NP: Capture/Compare 1 complementary output polarity CC1 channel is configured as output: 0: OC1N is active high. 1: OC1N is active low. CC1 channel is configured as input: Bit 3 C1NP is combined with C1P to define TI1FP1/TI2FP1 polarity (Please refer to C1P description).
  • Page 306 AT32F415 Series Technical Manual OCxREF inverted + polarity OCxREF + polarity+ dead-time, + dead-time, OCx_EN = 1 OCxN_EN = 1 Output disabled Output disabled (not driven by the timer) (not driven by the timer) OCx = CxP, OCx_EN = 0 OCxN = CxNP, OCxN_EN = 0 Off-state OCxREF + polarity,...
  • Page 307 AT32F415 Series Technical Manual DIV[15:0]: Prescaler value The counter clock frequency CK_CNT is fCK_DIV/(DIV[15:0]+1). Bit 15:0 DIV contains the value loaded in the active prescaler register at each update event. Update events include the counter cleared by the UEVG bit in the TMR_EVEG register, or cleared by the slave controller working in reset mode.
  • Page 308 AT32F415 Series Technical Manual CC1[15:0]: Capture/Compare channel 1 value f CC1 channel is configured as output: CC1 is the value to be loaded in the actual capture/compare 1 register (preload value). The written value is loaded immediately to the active register if the preload feature is not selected in the TMRx_CCM1 register (the OC1PEN bit).
  • Page 309 AT32F415 Series Technical Manual CC4[15:0] CC4[15:0]: Capture/Compare channel 4 value If CC4 channel is configured as output: CC4 is the value to be loaded in the actual capture/compare 4 register (preload value). The written value is loaded immediately to the active register if the preload feature is not selected in the TMRx_CCM4 register (the OC4PEN bit).
  • Page 310 AT32F415 Series Technical Manual BRKEN: Break enable 0: Break inputs (BRK and CCS clock failure event) is disabled. 1; Break inputs (BRK and CCS clock failure event) is enabled. Note 1: This bit cannot be modified once LOCK level is set as ‘1’ (the LOCKC bits in Bit 12 the TMRx_BRKDT register).
  • Page 311 AT32F415 Series Technical Manual Reset value: 0x0000 Reserved DBLEN[4:0] Reserved ADDR[4:0] Bit 15:13 Reserved. Always read as 0. DBLEN[4:0]: DMA burst length The bits define the number of DMA transfers in burst mode (the timer recognizes a burst transfer when a read or a write access is done to the TMRx_DMABA register). Namely, defining the number of transfer, and the transfer can be half-word (two-byte) or byte: 00000: 1 transfer 00001: 2 transfers...
  • Page 312 AT32F415 Series Technical Manual 10 Watchdog 10.1 Window Watchdog (WWDG) 10.1.1 WWDG Introduction The window watchdog is normally used to detect software malfunctions generated by external interference or by unforeseen logical conditions, which cause the program to abandon its normal sequence.
  • Page 313 AT32F415 Series Technical Manual WWDG_CTRL register can enable the watchdog. Afterwards, it cannot be disabled unless a reset occurs.  Control the downcounter. The downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the CNTR6 bit must be set to prevent an immediate reset.
  • Page 314 AT32F415 Series Technical Manual Figure 11-2 W indow W atchdog Timing Diagram CNTR[6:0] CNT downcounter WCNTR [6:0] Time Refresh not Refresh the allowed window CNTR6 bit Reset The formula to calculate the timeout: PSC[1:0] x 4096 x 2 x (CNTR[5:0] + 1); (ms) WWDG PCLK1 where:...
  • Page 315 AT32F415 Series Technical Manual 10.1.6 Register Description These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Table 11-1 WW DG Register Map and Reset Values Offset Register WWDG_CT CNTR[6:0] 0x00 Reserved Reset Value 0 1 1 1 1 1 1 1 WWDG_CF WCNTR[6:0] 0x04...
  • Page 316 AT32F415 Series Technical Manual 10.1.6.2 Configuration Register (WWDG_CFG) Address offset: 0x04 Reset value: 0x7F Reserved Reserved EWIEN PSC[1:0] WCNTR[6:0] Bit 31:8 Reserved. EWIEN: Early wakeup interrupt Bit 9 If this bit is set, an interrupt will be generated when the counter value reaches 40h. The interrupt can only be cleared by hardware after reset.
  • Page 317 AT32F415 Series Technical Manual 10.2 Independent Watchdog (IWDG) 10.2.1 Introduction AT32F415 devices have two embedded watchdogs which provide a higher safety level, timing accuracy, and flexibilities. Both watchdog peripherals (independent watchdog and window watchdog) can detect and resolve malfunctions caused by software failures. When the counter reaches a given timeout value, they can trigger an interrupt (window watchdog only) or system reset.
  • Page 318 AT32F415 Series Technical Manual Figure 11-3 Block Diagram of Independent W atchdog 1.8 V power domain Prescaler register Status register Reload register Key register IWDG_PR IWDG_STS IWDG_RLD IWDG_KEY 12-bit reload value 8-bit prescaler 40 KHz 12-bit downcounter power domain IWDG reset Note: The watchdog is implemented in VDD power domain, which means that it can work normally in Stop mode and Standby mode.
  • Page 319 AT32F415 Series Technical Manual 10.2.4 IWDG Register Description About the abbreviations used on the register descriptions, please refer to Table 1-4. These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Offset Register IWDG_KEY KEY[15:0] 0x00 Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDG_PR PR[2:0]...
  • Page 320 AT32F415 Series Technical Manual 10.2.4.2 Prescaler Register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Reserved Reserved PR[2:0] Bit 31:3 Reserved. Always read as 0. PR[2:0]: Prescaler divider These bits are write-protected, please refer to Section 11.2.3.2. Users can select the prescaler divider for the counter clock by setting these bits.
  • Page 321 AT32F415 Series Technical Manual 10.2.4.4 Status Register (IWDG_STS) Address offset: 0x0C Reset value: 0x0000 0000 (Not reset by Standby mode) Reserved Reserved RLDF PSCF Bit 31:2 Reserved. RLDF: Watchdog counter reload value update This bit is set by hardware to indicate that the reload value update is in process. Bit 1 When the reload update is done in VDD domain, this bit is cleared by hardware (five 40 kHz RC cycles are needed at most).
  • Page 322 AT32F415 Series Technical Manual 11 Real-time Clock (ERTC) 11.1 Introduction Real-time clock (ERTC) is an independent BCD timer/counter. ERTC provides one calendar clock, two programmable clock interrupt, and a periodic programmable wakeup flag with interrupt function. ERTC also contains automatic wakeup unit for low-power mode management. Two 32-bit register include Binary-Coded Decimal (BCD) seconds, minutes, hours (12-hour clock or 24-hour clock), days, dates, months, and years.
  • Page 323 AT32F415 Series Technical Manual This output can map to device ERTC_AF1 function.  ERTC_ALARM (alarm clock A, alarm clock B, or wakeup); this output can be selected by setting the ERTC_CTRL register, OSEL[1:0]. This output can map to device ERTC_AF1 function. ●...
  • Page 324 AT32F415 Series Technical Manual To obtain internal clock (ck_spre) with frequency of 1 Hz by using LSE with frequency of 32.768 kHz, the asynchronous prescaler ratio should be set to 128, and the synchronous prescaler ratio should be set to 256. The maximum ratio is 222, while the minimum is 1.
  • Page 325 AT32F415 Series Technical Manual the ERTC_CTRL register. Note: If second field is selected (the MASK1 bit in the ERTC_ALA or ERTC_ALB is reset), then the synchronous prescaler ratio set in the ERTC_PSC register must be 3 at least, to ensure that the alarm clock correctly operates.
  • Page 326 AT32F415 Series Technical Manual 1. Set the INITM bit in the ERTC_STS register to enter initialization mode. In this mode, calendar counter will stop working, and its value can be updated. 2. Poll the INITF bit in the ERTC_STS register. Enter initialization stage mode when the INITF bit is set.
  • Page 327 AT32F415 Series Technical Manual frequency, which can ensure the safety of synchronous mechanism. If the APB1 clock frequency is lower than 7 times of the ERTC clock frequency, then software should read the calendar time register and date register respectively, 2 times in total. When the two reads of ERTC_TIME show the same result, it is ensured that the data is correct.
  • Page 328 AT32F415 Series Technical Manual (ERTC_SBSR or ERTC_TSSBS), the accurate deviation between remote-clock time and ERTC can be calculated. Afterwards, ERTC_SFCTR can be used to “shift” ERTC clock by seconds; deviation can be eliminated after adjustment. ERTC_SBSR includes the value of synchronization prescaler counter. In this way, the ERTC accurate time with resolution low to 1/(PRDIV_S + 1) can be calculated.
  • Page 329 AT32F415 Series Technical Manual ● PREVID_S = 0x00FF Note: Reference clock detection is unavailable in Stand-by mode. Note: Reference clock detection function cannot be used simultaneously with coarse digital calibration: When RFCKON = 1, the ERTC_CAL register must be kept as 0x0000 0000. 11.3.10 ERTC Coarse Digital Calibration Two digital calibration methods are available: Coarse calibration and fine calibration.
  • Page 330 AT32F415 Series Technical Manual seconds. Fine digital calibration register (ERTC_CCR) can define the ERTCCLK clock cycles to be decreased within 32-second cycle: ● When CALM[0] is set, only 1 pulse is decreased in the 32-second cycle. ● W hen CALM[1] is set, two cycles are decreased. ●...
  • Page 331 AT32F415 Series Technical Manual ● The CAL16 bit in the ERTC_CCR register can be set to force 16 -second calibration cycle. At this time, ERTC reso lution can be measured within 16 seconds, the maximum generated deviation is 0.954 ppm (0.5 ERTCCLK cycle within 16 seconds) However, since the calibration resolution is decreased, the long-term ERTC resolution also decreases to 0.954 ppm;...
  • Page 332 AT32F415 Series Technical Manual Tamper Detection Initialization Tamper detection input is related to the TPF flag in the ERTC_STS register. Each input can be enabled by setting the corresponding TM1E bit in the ERTC_TPAF register. Tamper detection events will reset all backup registers (ERTC_BKPxDT). By setting the TMIE bit in the ERTC_TPAF register, interrupt can be generated when tamper detection event occurs.
  • Page 333 AT32F415 Series Technical Manual calibration output when ERTCCLK frequency is 32.768 kHz, where the prescaler is default value (PRDIV_A = Ox7F and PRDIV_S = 0xFF). Calibration alternate function output When the CALOE bit is set in the ERTC_CTRL register, calibration alternate function (ERTC_CAL) will be enabled in the ERTC_AF1.
  • Page 334 AT32F415 Series Technical Manual 1. Set the EXTI line 21 to interrupt mode, then enable the interrupt, and select rising edge effective. 2. Configure and enable the TAMP_STAMP IRQ channel in the NVIC. 3. Configure ERTC to detect ERTC time stamp event. Figure 11-4 Interrupt Control Bit Interrupt Event Time flag...
  • Page 335 AT32F415 Series Technical Manual WK[2:0] MU[3:0] DT[1:0] DU[3:0] Bit 31:24 Reserved Bit 23:20 YT[3:0]: Tens of years Bit 19:16 YU[3:0]: Ones of years Bit 15:13 WK[2:0]: Ones of week days 000: Forbidden 001: Monday … 111: Sunday Bit 12 MT: Tens of months (BCD format) Bit 11:8 MU: Ones of months (BCD) Bit 7:6...
  • Page 336 AT32F415 Series Technical Manual Bit 17 SUB1H: Subtract 1 hour (Winter time) When this bit is set in the mode other than initialization mode, if the current hour is not 0, then the calendar time will be subtracted from 1 hour. This bit is always read as 0. When the current hour is 0, setting this bit has no effect.
  • Page 337 AT32F415 Series Technical Manual Write access to the Bit 7, 6, and 4 of this register can only be done in initialization mode (ERTC_STS/INITF = 1). Write access to the bits 2 to 0 in this register can only be done when the ERTC_CTRL WATE bit = 0, and the ERTC_STS WATWF bit = 1.
  • Page 338 AT32F415 Series Technical Manual Bit 5 RSF: Register synchronization flag Every time when the value of calendar register is copied to the shadow register (ERTC_SBSRx, ERTC_TIMEx, and ERTC_DATEx), this flag will be set by hardware. In initialization mode, shift operation pending (SFP = 1), or bypass shadow register mode (BYPSHDW = 1), this flag will be cleared by hardware.
  • Page 339 AT32F415 Series Technical Manual 11.6.6 ERTC Wakeup Timer Register (ERTC_WATR) Offset: 0x14 Power-on reset value: 0x0000 FFFF System reset: Not affected WAREV[15:0] Bit 31:16 Reserved Bit 15:0 WAREV[15:0]: Wakeup auto-reload value bit When enabling wakeup timer (WATE is set), every (WAREV[15:0] + 1) ck_WAREV cycle set the WATF flag once.
  • Page 340 AT32F415 Series Technical Manual 11.6.8 ERTC Alarm Clock A Register (ERTC_ALA) Offset: 0x1C Power-on reset value: 0x0000 0000 System reset: Not affected MASK4 WKSEL DT[1:0] DU[3:0] MASK3 AMPM HT[1:0] HU[3:0] MASK2 MT[2:0] MU[3:0] MSK1 ST[2:0] SU[3:0] Bit 31 MASK4: alarm clock A DATE mask 0: If date matches day, alarm clock A is set.
  • Page 341 AT32F415 Series Technical Manual 0: DU[3:0] is the ones of date. 1: DU[3:0] is week day. DT[1:0] are “don’t care.” Bit 29:28 DT[1:0]: Tens of date (BCD format) Bit 27:24 DU[3:0]: Ones of date or day (BCD format) Bit 23 MASK3: Alarm clock A hour mask 0: If hour matches, alarm clock A is set.
  • Page 342 AT32F415 Series Technical Manual Bit 31:16 Reserved Bit 15:0 SBS: Sub-second value SBS[15:0] is the value of synchronous prescaler counter. This sub-second value can be calculated by the following equation: sub-second value = ( PRDIV_S - SBS ) / ( PRDIV_S + 1 ) Note: Only after shift operation can SBS be >...
  • Page 343 AT32F415 Series Technical Manual Bit 15 Reserved; must be kept as reset value. Bit 14:12 MT[2:0]: Tens of minute (BCD format) Bit 11:8 MU[3:0]: Ones of minute (BCD format) Bit 7 Reserved; must be kept as reset value. Bit 6:4 ST[2:0]: Tens of second (BCD format) Bit 3:0 SU[3:0]: Ones of second (BCD format)
  • Page 344 AT32F415 Series Technical Manual System reset: Not affected CALAD CAL8 CAL16 CALM[8:0] Bit 31:16 Reserved Bit 15 CALAD: Increase ERTC frequency with 488.5 ppm 0: ERTCCLK pulse is not inserted. 1: ERTCCLK pulse is effectively inserted every 211 pulses (increase frequency with 488.5 ppm). This function should be used with CALM, the latter will decrease calendar frequency at high-resolution.
  • Page 345 AT32F415 Series Technical Manual Bit 14:13 TMPRCH[1:0]: TAMPER precharge lasting time These bits determine the lasting time of pull-up activated before each sampling. TMPRCH is effective to every tamper input. 0x0: 1 ERTCCLK cycle 0x1: 2 ERTCCLK cycles 0x2: 4 ERTCCLK cycles 0x3: 8 ERTCCLK cycles Bit 12:11 TMFLT[1:0]: Tamper filter count...
  • Page 346 AT32F415 Series Technical Manual 2: Compare in alarm clock A, SBS [14:2] are “don’t care”, only SBS [1:0] is compared. 3: Compare in alarm clock A, SBS [14:3] are “don’t care”, only SBS [2:0] is compared. 12: Compare in alarm clock A, SBS [14:12] are “don’t care”, only SBS [11:0] is compared. 13: Compare in alarm clock A, SBS [14:13] are “don’t care”, only SBS [12:0] is compared.
  • Page 347 AT32F415 Series Technical Manual D[31:16] D[15:0] Bit 31:0 D[31:0] Application can write/read data to/from these registers. When VDD is disabled, these registers are powered by VBAT, so they will not be reset at system reset; also, when the device works in low-power mode, content of the registers are still effective.
  • Page 348 AT32F415 Series Technical Manual 12 Analog-to-Digital Converter (ADC) 12.1 ADC Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has 23 channels to measure the 21 external and 2 internal signal sources. The analog signal of each channel can be converted by the ADC in single, continuous, scan, or discontinuous mode.
  • Page 349 AT32F415 Series Technical Manual 12.3 ADC Function Overview Figure 13-1 is the block diagram of an ADC module, and Table 13-1 lists the description of ADC pins. Figure 13-1 Single ADC Block Diagram Interrupt enable bits End of conversion Flag bits ECIEN ADC interrupt to NVIC End of injected conversion...
  • Page 350 AT32F415 Series Technical Manual Table 13-1 ADC Pins Name Signal Type Description Input, analog reference The higher/positive reference voltage for the ADC, REF+ 2.6 V ≤ V ≤ V positive REF+ Analog power supply equal to V and: (Note) Input, analog supply ≤...
  • Page 351 AT32F415 Series Technical Manual ● If a regular channel is converted: ― The converted data is stored in the 16-bit ADC_RDOR register. ― The EC (End of Conversion) flag is set. ― An interrupt is generated if the ECIEN bit is set. ●...
  • Page 352 AT32F415 Series Technical Manual 12.3.7 Analog Watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below the low threshold or above the high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_WHTR and ADC_WLTR registers.
  • Page 353 AT32F415 Series Technical Manual 12.3.9 Injected Channel Management Triggered injection Triggered injection is enabled by clearing the JAUT bit in the ADC_CTRL1 register and setting the SCN bit. 1. Start the conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_ CTRL2 register.
  • Page 354 AT32F415 Series Technical Manual 12.3.10 Discontinuous Mode Regular group This mode is enabled by setting the RDISEN bit in the ADC_CTRL1 register. It can be used to convert n (n <= 8) conversions of a short sequence, and this conversion is a part of the conversion sequence selected by the ADC_RSQx registers.
  • Page 355 AT32F415 Series Technical Manual 2. Before starting a calibration, the ADC must be at power-off state (ADON bit = ‘0’) for at least two ADC clock cycles. Figure 13-5 Calibration Timing Diagram Calibration flag cleared by Calibration ongoing hardware Normal ADC conversion conversion 12.3.12 Data Alignment...
  • Page 356 AT32F415 Series Technical Manual conversion for the regular and injected groups. Note: When an external trigger signal is selected for ADC regular or injected conversion, only its rising edge can start the conversion. Table 13-3 ADC1 and ADC2 Used in External Trigger for Regular Channels Source Type EXSEL[3:0]...
  • Page 357 AT32F415 Series Technical Manual TMR15_CC3 event 1010 TMR15_CC4 event 1011 TMR15_TRGO event 1100 TMR1_CC1 event 1101 TMR8_CC1 event 1110 TMR8_TRGO event 1111 Note: For injected channels, the selection of the EXTI line 15 or TMR8_ CC4 as external trigger event done through configuration...
  • Page 358 AT32F415 Series Technical Manual TMR5_CC4 event 0110 JSWSTR Software control bit 0111 TMR15_CC1 event 1000 TMR15_CC2 event 1001 TMR15_CC3 event 1010 TMR15_CC4 event 1011 Internal signal from on-chip timers TMR15_TRGO event 1100 TMR1_CC1 event 1101 TMR1_CC2 event 1110 TMR8_TRGO event 1111 Software trigger events can be generated by setting the SWSTR or JSWSTR bit in the ADC_CTRL2 register.
  • Page 359 AT32F415 Series Technical Manual Note: In dual ADC mode, to read the slave-converted data on the master data register, the DMAEN bit must be enabled, even if DMA is not used to transfer regular channel data. ( N o t e ) Figure 13-8 Dual ADC Block Diagram Regular channel data register...
  • Page 360 AT32F415 Series Technical Manual ● A JEC interrupt is generated (if enabled on any of the ADC interfaces) when the ADC1/ADC2 injected channels are all converted. Note: In simultaneous mode, users must convert sequences with exactly the same sampling time, or ensure that the trigger interval is longer than the longer sequence within the two sequences.
  • Page 361 AT32F415 Series Technical Manual ● ADC2 starts immediately and, ● ADC1 starts after a delay of 7 ADC clock cycles. If the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs are continuously converted. After an EC interrupt is generated by ADC1 (enabled through the ECIEN bit), a 32-bit DMA transfer request is generated (if the DMAEN bit is set).
  • Page 362 AT32F415 Series Technical Manual Figure 13-12 Slow Interleaved Mode on 1 Channel Sampling End of conversion on ADC2 Conversion ADC2 Channel 0 Channel 0 Channel 0 Channel 0 ADC1 Trigger End of conversion on ADC1 14 ADCCLK cycles 28 ADCCLK cycles 12.3.16.5 Alternate Trigger Mode This mode only applies to injected channel group.
  • Page 363 AT32F415 Series Technical Manual Figure 13-14 Alternate Trigger: 4 Injected Channels of Each ADC in Discontinuous Mode Sampling Conversion Third trigger Fifth trigger Seventh trigger Frist trigger JEC on ADC1 ADC1 ADC2 JEC on ADC2 Fourth trigger Sixth trigger Eighth trigger Second trigger 12.3.16.6 Independent mode In this mode, the dual ADC synchronization is bypassed, and each ADC interface works...
  • Page 364 AT32F415 Series Technical Manual 12.3.16.7 Combined Regular/Injected Simultaneous Mode Simultaneous conversion of regular group can be interrupted to start simultaneous conversion of injected group. Note: In combined regular/injected simultaneous mode, users must convert sequences with exactly the same sampling time, or ensure that the trigger interval is longer than the longer sequence within the two sequences.
  • Page 365 AT32F415 Series Technical Manual 12.3.16.9 Combined Injected Simultaneous + Interleaved mode An injected event can interrupt an interleaved conversion. In this case, the interleaved conversion is interrupted, and the injected conversion is started. The interleaved conversion is resumed at the end of the injected sequence.
  • Page 366 AT32F415 Series Technical Manual Select a sample time of 8.6 μs. Set the TSREF bit in the ADC control register 2 (ADC_CTRL2), to wake up the temperature sensor from power-down mode. Start the ADC conversion by setting the ADON bit (or by external trigger). Read the V data result in the ADC data register.
  • Page 367 AT32F415 Series Technical Manual ADC_CTRL2 008h Reserved Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Offset register ADC_SMPT1 00Ch Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPT2 010h Reset Value...
  • Page 368 AT32F415 Series Technical Manual ADC_JDOR4 JD[15:0] 048h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_RDOR AD2D[15:0] D[15:0] 04Ch Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2020.06.28 Page 368 Version 1.02...
  • Page 369 AT32F415 Series Technical Manual 12.4.1 ADC Status Register (ADC_STS) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved RSTR JSTR rc w0 rc w0 rc w0 rc w0 rc w0 Bit 31:15 Reserved. Must be kept as 0. RSTR: Regular channel Start flag This bit is set by hardware at the start of regular channel conversion, and it is Bit 4 cleared by software.
  • Page 370 AT32F415 Series Technical Manual AWDEN: Analog watchdog enable on regular channels This bit is set and cleared by software. Bit 23 0: Analog watchdog is disabled on regular channel. 1: Analog watchdog is enabled on regular channel. JAWDEN: Analog watchdog enable on injected channels This bit is set and cleared by software.
  • Page 371 AT32F415 Series Technical Manual SCN: Scan mode This bit is set and cleared by software to enable or disable scan mode. In scan mode, channels selected by the ADC_RSQx or ADC_JSQx register are converted. Bit 8 0: Scan mode is disabled. 1: Scan mode is enabled.
  • Page 372 AT32F415 Series Technical Manual TSREF: Temperature sensor and V enable REFINT This bit is set and cleared by software, to enable or disable the temperature sensor and V channel. In devices with more than one ADC, this bit is REFINT Bit 23 present only in ADC1.
  • Page 373 AT32F415 Series Technical Manual JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable or disable external trigger event Bit 15 which starts injected channel group conversion. 0: Conversion on external event is disabled. 1: Conversion on external event is enabled.
  • Page 374 AT32F415 Series Technical Manual CAL: A/D Calibration This bit is set by software to start calibration and cleared by hardware when the Bit 2 calibration is completed. 0: Calibration is completed. 1: Start calibration CON: Continuous conversion This bit is set and cleared by software. If this bit is set, conversion will be Bit 1 continuously performed until this bit is cleared.
  • Page 375 AT32F415 Series Technical Manual Bit 31:30 Reserved. Must be kept as 0. SMPx[2:0]: Channel x Sample time selection These bits select the sample time for each channel individually. During sample cycles, channel selection bits must remain unchanged. 000: 1.5 cycles 100: 41.5 cycles Bit 29:0 001: 7.5 cycles...
  • Page 376 AT32F415 Series Technical Manual Reserved AWLT[11:0] Bit 31:12 Reserved. Must be kept as 0. AWLT[11:0]: Analog watchdog low threshold Bit 11:0 These bits define the low threshold for analog watchdog. 12.4.9 ADC Regular Sequence Register 1 (ADC_RSQ1) Address offset: 0x2C Reset value: 0x0000 0000 Reserved LEN[3:0]...
  • Page 377 AT32F415 Series Technical Manual SQ12[4:0]: 12th conversion in regular sequence Bit 29:25 These bits are set by software to define the channel number (0 ~ 17) of the 12th conversion in the sequence. Bit 24:20 SQ11[4:0]: 11th conversion in regular sequence Bit 19:15 SQ10[4:0]: 10th conversion in regular sequence Bit 14:10...
  • Page 378 AT32F415 Series Technical Manual JLEN[1:0]: Injected sequence length These bits are set by software to define the total number of conversions in the injected channel conversion sequence. Bit 21:20 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions JSQ4[4:0]: 4th conversion in injected sequence These bits are set by software to define the channel number (0 ~ 17) of the 4th conversion in the sequence.
  • Page 379 AT32F415 Series Technical Manual ADC2D[15:0]: ADC2 data - In ADC1: In dual mode, these bits contain the channel data of ADC2. Please Bit 31:16 refer to Section 13.3.16. - In ADC2 and ADC3: these bits are not used. D[15:0]: Regular data These bits are read only.
  • Page 380 AT32F415 Series Technical Manual 2020.06.28 Page 380 Version 1.02...
  • Page 381 AT32F415 Series Technical Manual 13 I C Interface 13.1 I C Introduction C (inter-integrated circuit) bus interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability and controls all I C bus-specific sequencing, protocol, arbitration, and timing.
  • Page 382 AT32F415 Series Technical Manual 13.3 I C Function Overview C module receives and transmits data, and converts data from serial to parallel format, and vice versa. Interrupts can be enabled or disabled. The interface is connected to the I C bus through a data pin (SDA) and a clock pin (SCL).
  • Page 383 AT32F415 Series Technical Manual Figure 15-2 Block Diagram of I C Function Data register Data control Data shift register Comparator PEC calculation Own address register Dual address register PEC register Clock control Clock control register (CLKCTRL) Control registers (CTRL1&CTRL2) Control logic circuit Status register (STS1&STS2) SMBALERT...
  • Page 384 AT32F415 Series Technical Manual Header matched (10-bit mode only): If the ACKEN bit is set, the I C interface generates an acknowledge pulse and waits for the 8-bit slave address. Address matched: The I C interface generates the following sequence: ●...
  • Page 385 AT32F415 Series Technical Manual Figure 15-4 Transfer Sequence Diagram of Slave Receiver 7-bit slave receiver Address Data 1 Data 2 Data N …… 10-bit slave receiver Header Address Data 1 Data N …… Description:S = Start (Start condition), Sr = Repeated start condition, P = Stop (Stop condition), A = Acknowledge, NA = Non acknowledge, Evx = Event (Interrupt generated when EVTITEN = 1) EV1: ADDRF = 1, read STS1 and then STS2 to clear the event.
  • Page 386 AT32F415 Series Technical Manual set. Then, the master waits for a read to the STS1 register, followed by writing the slave address into the DT register (Please refer to EV5 in Figure 15-5 Figure 15-6). Slave address transmission The slave address is sent to the SDA line via the internal shift register. ●...
  • Page 387 AT32F415 Series Technical Manual (the MSF bit is cleared). Note: Stop condition should be programmed during EV8_2 event whe n either the TDE bit or the BTFF bit is set. Figure 15-5 Transfer Sequence Diagram of Master Transmitter 7-bit master transmitter Address Data 1 Data 2...
  • Page 388 AT32F415 Series Technical Manual Figure 15-6 Transfer Sequence Diagram of Master Receiver 7-bit master receiver Address Data 1 Data 2 Data N ⑴ …… EV6 EV6_1 EV7_1 10-bit master receiver Header Address Address Data 1 Data 2 Data N ⑴ ……...
  • Page 389 AT32F415 Series Technical Manual ● Data N received, and respond to NACK ● Set the STARTGEN/STOPGEN bit ● RDNE = 1 ● Read data N Case 3: I C interrupt is not set as the highest priority, and the total number of bytes received is 2 or 1, N = 2 or N = 1 ●...
  • Page 390 AT32F415 Series Technical Manual Figure 15-9 Transfer Sequence Diagram for Master Receiver when N = 1 7-bit master receiver Address Data 1 EV6_3 10-bit master receiver Header Address header Data 1 EV6_3 Description:S = Start (Start condition), Sr = Repeated start condition, P = Stop (Stop condition), A = Acknowledge, NA = Non acknowledge, Evx = Event (Interrupt generated when EVTITEN = 1) EV5:STARTF = 1, read STS1 and then write the address to the DT register to clear the event.
  • Page 391 AT32F415 Series Technical Manual transmit the last received byte. In slave mode, an underrun error occurs if clock stretching is disabled, the I C interface is transmitting data, but before the clock of the next byte arrives, new data is not yet written into the DT register (TDE = 1).
  • Page 392 AT32F415 Series Technical Manual 35 ms clock low timeout No clock timeout Fixed logic levels -dependent logic levels Different address types (reserved, dynamic, etc.) 7-bit, 10-bit, and general call slave address types Different bus protocols (quick command, process call, etc.) No bus protocols SMBus applications With System Management Bus, devices can provide manufacturer information, tell the system its...
  • Page 393 AT32F415 Series Technical Manual A host which does not implement the SMBALERT signal can periodically access ARA. For more details on SMBus Alert mode, please refer to SMBus specification version 2.0. standard http://smbus.org/specs/ Timeout error In the timing specifications, there are several differences between I C and SMBus.
  • Page 394 AT32F415 Series Technical Manual When the number of data transfers, programmed in the DMA controller, is reached, the DMA controller sends an End of Transfer signal, EOT/EOT_1, to the I C interface. A DMA interrupt will be generated if enabled. Note: Do not set the BUFITEN bit in the I2C_CTRL2 register if DMA is used for transmission.
  • Page 395 AT32F415 Series Technical Manual 13.3.9 I C Interrupt Request Table 15-2 lists all the I C interrupt request. Table 15-2 C Interrupt Request Interrupt Event Event Flag Enable Control Bit Start bit sent (Master) STARTF Address sent (Master) or Address matched (Slave) ADDRF 10-bit header sent (Master) ADDR10F...
  • Page 396 AT32F415 Series Technical Manual EVTITEN STARTF ADDRF ADD10F STOPF it_event BTFF Event interrupt BUFITEN RDNE ERRITEN BUSERR ARLOST ACKFAIL it_error OVRUN Error interrupt PECERR TIMOUT SMBALERTF 13.3.10 I C Debug Mode ® When the microcontroller enters debug mode (Cortex -M4F core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module.
  • Page 397 AT32F415 Series Technical Manual 13.4 C Registers These peripheral registers can be accessed by half-word (16-bit) or word (32-bit). Table 15-3 I² C Register Map and Reset Value Offset Register I2C_CTRL1 000h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 I2C_CTRL2 CLKFREQ[7:0] 004h...
  • Page 398 AT32F415 Series Technical Manual 13.4.1 Control Register 1 (I C_CTRL1) Address offset: 0x00 Reset value: 0x0000 STAR Reserve Reserve RESE ALER SWRESET: Software reset When set, I C is under reset state. Before resetting this bit, ensure that I C pins are released, and the bus is free.
  • Page 399 AT32F415 Series Technical Manual STOPGEN: Stop generation This bit is set or cleared by software. It is cleared by hardware when a Stop condition is detected. It is set by hardware when a timeout error is detected. In master mode: 0: No Stop condition is generated.
  • Page 400 AT32F415 Series Technical Manual 13.4.2 Control Register 2 (I C_CTRL2) Address offset: 0x04 Reset value: 0x0000 Reserved CLKFREQ[7:0] LAST ITEN ITEN ITEN Reserved. Forced to be ‘0’ by hardware. Bit 15:13 DMALAST: DMA last transfer 0: The next DMA EOT is not the last transfer. Bit 12 1: The next DMA EOT is the last transfer.
  • Page 401 AT32F415 Series Technical Manual ADDRMODE Reserved Reserved ADDR[9:8] ADDR[7:1] ADDR0 ADDRMODE: Addressing mode (Slave mode) Bit 15 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Reserved. Forced to be ‘0’ by hardware. Bit 14:10 ADDR[9:8]: Interface address Bit 9:8...
  • Page 402 AT32F415 Series Technical Manual DT[7:0]: 8-bit data register Used to store data received or to be transmitted to the bus. Transmitter mode: Data transmission starts automatically when a byte is written in the DT register. Once the transmission starts (TDE = 1), I C will maintain a continuous transmit stream if the next data to be transmitted is written to the DT register in time.
  • Page 403 AT32F415 Series Technical Manual 13.4.6 Status Register 1 (I C_STS1) Address offset: 0x14 Reset value: 0x0000 Rese ALER erve FAIL rved R10F rcw0 rcw0 rcw0 rcw0 SMBALERTF: SMBus alert In SMBus host mode: 0: No SMBus alert 1: SMBALERTF event occurs on the pin. Bit 15 In SMBus slave mode: 0: No SMBAlert response address header.
  • Page 404 AT32F415 Series Technical Manual BUSERR: Bus error 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition occurs. – Bit 8 Set by hardware when the interface detects a misplaced Start or Stop condition. – Cleared by software, or by hardware when PEN = 0. When BUSERR error occurs, this flag should be cleared by software in time to ensure that normal communication is resumed.
  • Page 405 AT32F415 Series Technical Manual ADDRF: Address sent (Master mode)/matched (Slave mode) This bit is cleared by read access to the STS2 register after software reads the STS1 register. Address matched (Slave mode) 0: Address is mismatched or not received. 1: Received address is matched. –...
  • Page 406 AT32F415 Series Technical Manual TRF: Transmitter/receiver 0: Data is received. 1: Data is transmitted. At the end of the whole address transmission phase, this bit is Bit 2 set depending on the R/W bit of the address byte. It is cleared by hardware after detection of Stop condition (STOPF = 1), repeated Start condition, bus arbitration lost (ARLOST = 1), or when PEN = 0.
  • Page 407 AT32F415 Series Technical Manual CLKCTRL[11:0] : Clock control register in Fast/Standard mode (Master mode) The divider ratio sets the SCL clock in master mode. In slave mode, it does not need to be configured, or is the same as the one in master mode according to the equation. In I C standard mode or SMBus mode: = CLKCTRL ×...
  • Page 408 AT32F415 Series Technical Manual 14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 14.1 USART Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means to realize full-duplex data exchange with external devices which require industry standard NRZ asynchronous serial data format. With a fractional baud rate generator, the USART offers a very wide range of baud rates.
  • Page 409 AT32F415 Series Technical Manual ─ Noise error ─ Framing error ─ Parity error ● 10 interrupt sources with flags ─ CTSF changes ─ LIN break detection ─ Transmit data register empty ─ Transmission completed ─ Receive data register full ─ Idle line detected ─...
  • Page 410 AT32F415 Series Technical Manual The following pins are required in hardware flow control mode: ● CTS: Cleared after reception. If it is low level, the next data transmission will occur after the current transmission ends. If it is high level, the next data transmission will be stopped by the end of current data transmission.
  • Page 411 AT32F415 Series Technical Manual Figure 16-2 W ord Length Programming 9-bit word length (The LEN bit is set), 1 stop bit Next data frame Possible Data frame Next parity bit Start start Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Clock Start Idle frame...
  • Page 412 AT32F415 Series Technical Manual 2. After the TEN bit is enabled, the USART will automatically send an idle frame. 14.3.2.2 Configurable Stop Bit The number of stop bits transmitted by each character can be programmed by the bits 13 and 12 in the control register 2 (USART_CTRL2).
  • Page 413 AT32F415 Series Technical Manual automatically send an idle frame as the first data transmission. 7. Write the data to be sent in the USART_DT register (which clears the TDE bit). Repeat this step to each data to be transmitted in single buffer cases. 8.
  • Page 414 AT32F415 Series Technical Manual (See Figure 16-2). If the SBRK = 1, a break frame is sent on the Tx line after completing the current data transmission. The SBRK bit is reset by hardware when the break character transmission is completed (during the stop bit of the break frame).
  • Page 415 AT32F415 Series Technical Manual bits are received, and it will abort the start bit detection and return to idle state waiting for a falling edge. 14.3.3.2 Character Reception During a USART transmission, the least significant bits of data are shifted in first from the Rx pin. In this mode, the USART_DT register includes a buffer between the internal APB bus and the receive shift register.
  • Page 416 AT32F415 Series Technical Manual ● An interrupt is generated if either the RDNEIEN bit is set or both the ERRIEN and DMAREN bits are set. ● The ORERR bit is reset by reading the USART_STS and then the USART_DT registers in order.
  • Page 417 AT32F415 Series Technical Manual sequence. 14.3.3.6 Framing Error A framing error is detected when: The stop bit is not recognized on reception at the expected time because of data desynchronization or excessive noise. When a framing error is detected: ● The FERR bit is set by hardware. ●...
  • Page 418 AT32F415 Series Technical Manual 14.3.4.1 How to Derive USARTDIV from USART_ BAUDR Register Values Example 1: If DIV_Integer = 27, DIV_Decimal = 12 (USART_BAUDR = 0x1BC), then DIV_Integer (USARTDIV) = 27 DIV_Decimal (USARTDIV) = 12/16 = 0.75 Therefore, USARTDIV = 27.75 Example 2: To program USARTDIV = 25.62, it leads to: DIV_Decimal = 16*0.62 = 9.92...
  • Page 419 AT32F415 Series Technical Manual 14.3.5 USART Receiver’s Tolerance to Clock Deviation The USART asynchronous receiver can work normally only if the whole clock system deviation is within the range of the USART receiver tolerance. The factors that contribute to the deviation include: ●...
  • Page 420 AT32F415 Series Technical Manual 14.3.6.1 Idle Line Detection (WUMODE = 0) The USART enters mute mode when the RECMUTE bit is written to 1. It wakes up when an idle frame is detected. Then, the RECMUTE bit is cleared by hardware, but the IDLEF bit is not set in the USART_STS register.
  • Page 421 AT32F415 Series Technical Manual 14.3.6.2 Address Mark Detection (WUMODE = 1) In this mode, bytes are recognized as addresses if MSB is ‘1’; else, they are considered data. In an address byte, the address of the target receiver is put on the 4 LSB. This 4-bit address is compared by the receiver with its own address, which is programmed in the ADDR bits in the USART_CTRL2 register.
  • Page 422 AT32F415 Series Technical Manual the parity bit an odd number. For example, there are four ‘1’ in data = 00110101; if odd parity is selected ( PSEL = 1 in USART_CTRL1), the parity bit will be ‘1’. Transmission mode: If the PCEN bit is set in USART_ CTRL1, then the MSB bit of the data written in the data register is transmitted after changed by the parity bit (even number of ‘1’s if even parity is selected ;...
  • Page 423 AT32F415 Series Technical Manual Figure 16-9 Break Detection in LIN Mode (11-bit break length - The LBDLEN bit is set) Case 1: Break signal not long enough => break discarded, LBDF not set RX line Break frame Capture strobe Break state Idle Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Idle...
  • Page 424 AT32F415 Series Technical Manual Figure 16-10 Break Detection and Framing Error Detection in LIN Mode In the following examples, assume that LBDLEN = 1( break length is 11 bits), LEN = 0 (8-bit data) Case 1:Break after idle RX line Data 1 Idle Break...
  • Page 425 AT32F415 Series Technical Manual Figure 16-11 Example of USART Synchronous Transmission Input data Output data Synchronous device USART (i.e. Slave SPI ) Figure 16-12 Example of USART Data Clock Timing (LEN = 0) Idle or the last Idle or the next LEN = 0 (8 data bits) transmission transmission...
  • Page 426 AT32F415 Series Technical Manual Figure 16-13 Example of USART Data Clock Timing (LEN = 1) Idle or the last Idle or the next LEN = 1 (9 data bits) Start Stop transmission transmission Clock (CLKPOL = 0, CLKPHA = 0) Clock (CLKPOL = 0, CLKPHA = 1) Clock (CLKPOL = 1, CLKPHA = 0) Clock (CLKPOL = 1, CLKPHA = 1)
  • Page 427 AT32F415 Series Technical Manual a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware; that is, the USART cannot receive data when it is at transmission state. Namely, in half-duplex mode, transmission has higher priority over reception, and the conflicts between them should be handled by software.
  • Page 428 AT32F415 Series Technical Manual ● The assertion of the TRAC flag can be delayed by programming the guard time register (GTVAL). In normal operation, TRAC is asserted when the transmit shift register is empty and no further transmit requests occur. In Smartcard mode, an empty transmit shift register triggers the guard time counter to count up to the programmed value in the guard time register (GTVAL).
  • Page 429 AT32F415 Series Technical Manual 14.3.12 IrDA SIR ENDEC Block The IrDA mode is selected by setting the IRDAEN bit in the USART_CTRL3 register. In IrDA mode, the following bits must be kept cleared: ● LINEN, STOPB, and CLKEN in the USART_CTRL2 register ●...
  • Page 430 AT32F415 Series Technical Manual Figure 16-17 IrDA SIR ENDEC Block Diagram Figure 16-18 IrDA Data Modulation (3/16) - Normal Mode 3/16 14.3.13 Continuous Communication Using DMA The USART is capable of continuing communication by using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently.
  • Page 431 AT32F415 Series Technical Manual finishes all the data to be transmitted, the TCIF flag is set in the DMA_ISTS register by the DMA controller. The TRAC flag can be monitored to ensure that the USART communication is completed. This avoids corrupting the last transmission before disabling the USART or entering the Stop mode. The software must wait until TDE = 1, and then TRAC = 1.
  • Page 432 AT32F415 Series Technical Manual 14.3.13.3 Error Flag and Interrupt Generation in Multi-buffer Communication In multi-buffer communication, if any error occurs during the communication, the error flag will be asserted after the current byte transmission. An interrupt will be generated if the interrupt enable bit is set.
  • Page 433 AT32F415 Series Technical Manual If the CTS flow control is enabled (CTSEN = 1), then the transmitter checks the CTS input before transmitting the next frame. If CTS is asserted (tied low), then the next data is transmitted (assuming that the data is ready to be transmitted, in other words, if TDE = 0); if CTS is deasserted (high) during a transmission, the transmitter stops after the current transmission is completed.
  • Page 434 AT32F415 Series Technical Manual Figure 16-24 USART Interrupt Mapping Diagram TRAC TRACIEN TDEIEN CTSEN CTSIEN interrupt IDLEF IDLEIEN RDNEIEN ORERR RDNEIEN RDNE PERRIEN PERR LBDF LBDIEN FERR NERR ERRIEN ORERR DMAREN 14.5 USART Mode Configuration Table 16-7 USART Mode Configuration ( N o t e ) USART Mode USART1...
  • Page 435 AT32F415 Series Technical Manual 0x0000 USART_CTRL1 0x0C Reserved 0x0000 STOPB USART_CTRL2 ADDR[3:0] [1:0] 0x10 Reserved 0x0000 USART_CTRL3 0x14 Reserved 0x0000 USART_GTP GTVAL[7:0] DIV[7:0] 0x18 Reserved 0x0000 14.6.2 Status Register (USART_STS) Address offset: 0x00 Reset value: 0x00C0 Reserved Reserved CTSF LBDF TRAC RDNE IDLEF...
  • Page 436 AT32F415 Series Technical Manual TDE: Transmit data register empty This bit is set by hardware when the content of the TDR register is transferred into the shift register. An interrupt is generated if the TDEIEN bit = 1 in the USART_ Bit 7 CTRL1 register.
  • Page 437 AT32F415 Series Technical Manual FERR: Framing error This bit is set by hardware when a de-synchronization, excessive noise, or a break character is detected. It is cleared by a software sequence (a read to the USART_STS register followed by a read to the USART_DT register). 0: No framing error is detected.
  • Page 438 AT32F415 Series Technical Manual Reserved. Forced to be ‘0’ by hardware. Bit 31:18 DIV_ Integer[11:0]: Integer of USARTDIV Bit 15:4 The 12 bits define the integer of USART Divider (USARTDIV). DIV_Decimal[3:0]: Decimal of USARTDIV Bit 3:0 The 4 bits define the decimalof USART Divider (USARTDIV). 14.6.5 Control Register 1 (USART_CTRL1) Address offset: 0x0C Reset value: 0x0000...
  • Page 439 AT32F415 Series Technical Manual TDEIEN: TDE interrupt enable This bit is set and cleared by software. Bit 7 0: Interrupt is disabled. 1: A USART interrupt is generated when TDE is ‘1’ in the USART_STS register. RDNEIEN: RDNE interrupt enable This bit is set and cleared by software.
  • Page 440 AT32F415 Series Technical Manual LINEN: LIN mode enable This bit is set and cleared by software. 0: LIN mode is disabled. Bit 14 1: LIN mode is enabled. In LIN mode, the SBR bit in the USART_CTRL1 register can be used to send LIN synch breaks (13 low bits) and to detect LIN sync breaks.
  • Page 441 AT32F415 Series Technical Manual Note: The three bits, CLKPOL, CLKPHA, and LBCP, cannot be modified after enabling transmission. 14.6.7 Control Register 3 (USART_CTRL3) Address offset: 0x14 Reset value: 0x0000 Reserved HALF Reserved Reserved. Forced to be ‘0’ by hardware. Bit 31:11 CTSIEN: CTSF interrupt enable 0: Interrupt is disabled.
  • Page 442 AT32F415 Series Technical Manual HALFSEL: Half-duplex selection Selection of single-wire half-duplex mode Bit 3 0: Half-duplex mode is not selected. 1: Half-duplex mode is selected. IRDALP: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes. Bit 2 0: Normal mode 1: Low-power mode...
  • Page 443 AT32F415 Series Technical Manual 14.6.8 Guard Time and Prescaler Register (GTP) Address offset: 0x18 Reset value: 0x0000 Reserved GTVAL[7:0] DIV[7:0] Reserved. Forced to be ‘0’ by hardware. Bit 31:16 GTVAL[7:0]: Guard time value This bit-field specifies the guard time value in terms of baud clocks. This function is Bit 15:8 used in Smartcard mode.
  • Page 444 AT32F415 Series Technical Manual 15 Serial Peripheral Interface (SPI) 15.1 SPI Introduction The SPI interface supports either the SPI protocol or the I S audio protocol. By default, the SPI function is selected. Users can switch from SPI mode to I S mode by software.
  • Page 445 AT32F415 Series Technical Manual  Master or slave operations  8-bit programmable linear prescaler reach accurate audio sample frequencies (from 8 kHz to 192 kHz)  Data format can be 16-bit, 24-bit, or 32-bit.  Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, or 32- bit data frame) by audio channel .
  • Page 446 AT32F415 Series Technical Manual Address and data bus Read Rx buffer SPI_CTRL2 MOSI Shift register MISO SPI_STS LSBEN Control bit MODF CERR Tx buffer Write Communication logic MCLKP[2:0] Baud rate generator SPI_CTRL1 MCLKP MCLKP MCLKP SPIEN MSTEN CPOL CPHA SPI_CR1 Main control logic BDOE CCE MODE...
  • Page 447 AT32F415 Series Technical Manual Master Slave MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI SPI clock generator (Note) (Note) If NSS is managed by software, this pin is not used. Note: The NSS pin is configured as an input here. The MOSI pins are connected together, and the MISO pins are connected together.
  • Page 448 AT32F415 Series Technical Manual Clock phase and clock polarity The CPOL and CPHA bits in the SPI_CTRL register can generate four possible timing relationships. The CPOL (clock polarity) bit controls the clock level at idle state when no data is being transferred. This bit takes effect both in master and slave modes.
  • Page 449 AT32F415 Series Technical Manual Figure 17-4 Data Clock Timing Diagram CPHA = 1 CPOL = 1 CPOL = 0 MISO 8-bit or 16-bit data frame format is determined by the DFF16 in SPI_CTRL1 MOSI (To slave) Capture CPHA = 0 CPOL = 1 CPOL = 0 MISO...
  • Page 450 AT32F415 Series Technical Manual transfer, the CPOL and CPHA bits must be configured in the same way in the slave device and the master device. The frame format (MSB-first or LSB-first depending on the LSBEN bit in the SPI_CTRL1 register) must be the same as the master device. In hardware mode (Please refer to the section of slave select (NSS) pin management), the NSS pin must be connected to a low level signal during the whole byte (8-bit or 16-bit) transmit sequence.
  • Page 451 AT32F415 Series Technical Manual  Data-in shift register is transferred to Rx buffer, and the RNE flag is set.  An interrupt is generated if the RNEIE bit is set in the SPI_CTRL2 register. After the last sampling clock edge, the RNE bit is set, data byte received in the shift register is moved to the Rx buffer.
  • Page 452 AT32F415 Series Technical Manual shift register and then parallelly loaded into the SPI_DT register (Rx buffer).  In unidirectional receive-only mode (BDMODE = 0 and RONLY = 1) ─ The sequence begins as soon as SPIEN = 1. ─ Only the receiver is activated, and the received data on the MISO pin are shifted serially into the 8-bit shift register and then are parallelly loaded into the SPI_DT register (Rx buffer).
  • Page 453 AT32F415 Series Technical Manual generated if the TEIE bit in the SPI_CTRL2 register is set. Writing to the SPI_DT register can clear the TE bit. The software must ensure that the TE flag is set to 1 before attempting to write to Note: the Tx buffer.
  • Page 454 AT32F415 Series Technical Manual 2020.06.28 Page 454 Version 1.02...
  • Page 455 AT32F415 Series Technical Manual Figure 17-6 TE/RNE/BSY Behavior during Continuous Transfer in Slave/Full-duplex Mode (BDMODE = 0 and RONLY = 0) Example of slave mode CPOL = 1,CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 MISO/MOSI(Output) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 Set by hardware, cleared by...
  • Page 456 AT32F415 Series Technical Manual Figure 17-7 TE/BSY Behavior during Continuous Transfer in Master Transmit-only Mode (BDMODE = 0 and RONLY = 0) Example of master mode CPOL = 1,CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 MISO/MOSI(Output) Set by hardware and...
  • Page 457 AT32F415 Series Technical Manual clears the RNE bit). Repeat this operation for each data item to be received. This procedure can also be implemented to handle the interrupts generated at rising edges of the corresponding RNE flags. Note: If the SPI is disabled after the last transfer, please follow the recommended procedure in Section 17.3.1.9.
  • Page 458 AT32F415 Series Technical Manual Configuration example:CPOL = 1,CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 MOSI (Output) b0 b1 b2 b3 b4 b5 b6 b0 b1 b2 b3 b4 b5 b6 b7 b1 b2 b3 b4 b5 b6 b7 TE flag Tx buffer 0×F2...
  • Page 459 AT32F415 Series Technical Manual Note: 1. When the SPI is in slave mode, please note that CRC calculation is only enabled after the clock becomes stable. Otherwise, the CRC calculation may be wrong. In fact, once the CCE bit is set, the CRC calculation is performed if input clock is present on the SCK pin, no matter what the SPIEN bit status 2.
  • Page 460 AT32F415 Series Technical Manual transfer. Note: Do not use the BSY flag to handle every data transmission or reception. It is better to use the TE and RNE flags instead. 15.3.1.8 Disabling SPI When communication is completed, disabling the SPI peripheral can stop the communication. This is done by clearing the SPIEN bit.
  • Page 461 AT32F415 Series Technical Manual this case, the OVR flag is set because the data received is not read (Note: Software can ignore this flag). When only the SPI is used to receive data, only the SPI Rx DMA channel needs to be enabled. In transmission mode, when the DMA transfers all the data to be transmitted (The TCIF flag becomes ‘1’...
  • Page 462 AT32F415 Series Technical Manual Figure 17-11 Transmission using DMA Configuration example:CPOL = 1, CPHA = 1 Data 1 = 0×F1 Data 2 = 0×F2 Data 3 = 0×F3 MISO/MOSI (Output) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 Set by hardware and cleared by Set by hardware and cleared by TE flag...
  • Page 463 AT32F415 Series Technical Manual 15.3.1.10 Error Flag Master mode fault (MODF) Master mode fault occurs only when: In NSS pin hardware mode, the master device has its NSS pin pulled low; or in NSS pin software mode, the ISS bit is set as ‘0’; this automatically sets the MODF bit.
  • Page 464 AT32F415 Series Technical Manual 15.3.2 I S Function Overview All AT32F415 products support I S audio protocol. 15.3.2.1 S Function Overview Figure 17-13 is the block diagram of I Figure 17-13 S Block Diagram Address and data bus Tx buffer I2SC MODF 16-bit...
  • Page 465 AT32F415 Series Technical Manual  CK: Serial clock (mapped on the SCK pin) as clock signal output in master mode; input in slave mode  For some external audio devices which require master clock, an additional pin could be used to output clock. ...
  • Page 466 AT32F415 Series Technical Manual Figure 17-14 S Philips Protocol W aveforms (16bit/32-bit full accuracy, CPOL = 0) Transmission Reception Could be 16-bit or 32-bit LSB MSB Channel left Channel right Data are transmitted on the falling edge of CK by the transmitter, and are read on the rising edge by the receiver.
  • Page 467 AT32F415 Series Technical Manual Figure 17-18 S Philips Protocol Standard Waveforms (16-bit extended to 32-bit frame, CPOL = 0) Transmission Reception 16-bit data Remaining 16 bits forced 0 Channel left 32 bits Channel right When 16-bit data frame extended to 32-bit channel frame is selected at the I S configuration phase, only one access to SPI_DT is required.
  • Page 468 AT32F415 Series Technical Manual Data are changed on the falling edge of clock signal for transmitter and are read on the rising edge for the receiver. Figure 17-21 MSB-justified 24-bit Data, CPOL = 0 Reception Transmission 24-bit data Remaining 8 bits force 0 Channel right Channel left 32 bits Figure 17-22...
  • Page 469 AT32F415 Series Technical Manual Figure 17-24 LSB-justified 24-bit Data, CPOL = 0 Transmission Reception 8-bit data forced 0 24-bit data Channel left 32 bits Channel right  In transmission mode If data 0x3478AE is to be transmitted, two write operations to the SPI_DT register are required through software or by DMA.
  • Page 470 AT32F415 Series Technical Manual operation shown in Figure 17-28 is required. Figure 17-28 Example During transmission, if TE is ‘1’, users have to write the data to be transmitted (0x76A3 in this case). The 0x0000 field used for extension on 32-bit is transmitted first. The next TE event occurs as soon as valid data begins to be sent from the SD pin.
  • Page 471 AT32F415 Series Technical Manual Note: For both modes (master and slave) and for both synchronizations (short and long), the number of bits between two consecutive pieces of data and two synchronization signals needs to be specified by the DLEN bit and the CHLEN bit in the SPI_I2SCTRL register (even in slave mode).
  • Page 472 AT32F415 Series Technical Manual Table 17-2 provides an example of the precision values for different clock configurations. Note: Other configurations can also be used to achieve the optimum clock precision. Table 17-2 Audio-frequency Precision Using System Clock 16 bits 32 bits SysCLK Target Fs MCLK...
  • Page 473 AT32F415 Series Technical Manual 96000 70312.5 26.76% 70312.5 26.76% 48000 46875 2.34% 46875 2.34% 44100 46875 6.29% 46875 6.29% 32000 31250 2.34% 31250 2.34% 22050 21634.62 1.88% 21634.62 1.88% 16000 15625 2.34% 15625 2.34% 11025 10817.31 1.88% 10817.31 1.88% 8000 8035.714 0.45% 8035.714...
  • Page 474 AT32F415 Series Technical Manual flag is set, and an interrupt is generated if the RNEIE bit is set in the SPI_CTRL2 register. According to the data and channel length configured, the audio value received for a right or left channel may require one or two receptions into the Rx buffer.
  • Page 475 AT32F415 Series Technical Manual channel is written into the I S data register. The I2SCS flag indicates that data to be transmitted corresponds to which channel. Compared to the master transmission mode, in slave mode, I2SCS is sensitive to the WS signal from the external S master.
  • Page 476 AT32F415 Series Technical Manual communication is continuous).  When I S is disabled. When communication is continuous:  In master transmit mode, the BSY flag is kept high during all the transfers.  In slave mode, the BSY flag goes low for one I S clock cycle between each transfer.
  • Page 477 AT32F415 Series Technical Manual Overrun Flag ERRIE Underrun Flag 15.3.2.9 DMA Function DMA works in exactly the same way as in the I S mode and in SPI mode, except that the CRC feature is not available in I S mode since there is no data transfer protection system. 2020.06.28 Page 477 Version 1.02...
  • Page 478 AT32F415 Series Technical Manual 15.4 SPI Registers These peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Table 17-4 SPI Register Map and Reset Values Offset Register SPI_CTRL1 0x00 Reserved 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CTRL2 0x04 Reserved...
  • Page 479 AT32F415 Series Technical Manual 15.4.1 SPI Control Register 1 (SPI_CTRL1) (Not Used in I Mode) Address offset: 0x00 Reset value: 0x0000 MCLKP[2:0] BDMODE: Bidirectional data mode enable 0: “2-line unidirectional” mode is selected. Bit 15 1: “1-line bidirectional” mode is selected. Note: This bit is not used in I S mode.
  • Page 480 AT32F415 Series Technical Manual LSBEN: Frame format 0: MSB first Bit 7 1: LSB first Note 1: This bit cannot be changed when communication is ongoing. Note 2: This bit is not used in I S mode. SPIEN: SPI enable 0: SPI is disabled.
  • Page 481 AT32F415 Series Technical Manual ERRIE: Error interrupt enable This bit controls interrupt generation when errors occur (CERR, OVR, or MODF). Bit 5 0: Error interrupt is disabled. 1: Error interrupt is enabled. Reserved. Forced to be ‘0’ by hardware. Bit 4:3 NSSOE: SS output enable 0: SS output is disabled in master mode, and the device can work in multi-master mode.
  • Page 482 AT32F415 Series Technical Manual UDR: Underrun flag 0: No underrun error 1: Underrun error occurs. Bit 3 This bit is set by hardware and reset by software sequence, please refer to Section 17.3.2.7. Note: This bit is not used in SPI mode. I2SCS: Channel side 0: Channel left is to be transmitted or received.
  • Page 483 AT32F415 Series Technical Manual 15.4.6 SPIRxCRC Register (SPI_RCRC) (Not Used in I S Mode) Address offset: 0x14 Reset value: 0x0000 RCRC[15:0] RCRC[15:0]: Rx CRC register When CRC calculation is enabled, RCRC[15:0] contains the CRC value computed based on the received bytes. This register is reset when the CCE bit in SPI_CTRL1 register is written ‘1’.
  • Page 484 AT32F415 Series Technical Manual I2SSEL: I S mode selection 0: SPI mode is selected. Bit 11 1: I S mode is selected. Note: This bit can be configured only after SPI or I S is disabled. I2SEN: I S enable 0: I S is disabled.
  • Page 485 AT32F415 Series Technical Manual 15.4.9 SPI_I2S Prescaler Register (SPI_I2SCLKP) Address offset: 0x20 Reset value: 0x0002 I2SM I2SO Reserved I2SDIV[9:8] I2SDIV[7:0] Reserved. Forced to be ‘0’ by hardware. Bit 15:12 I2SDIV[9:8]: I S linear prescaler Bit 12:11 Please refer to the description of I2SDIV[7:0]. I2SMCLKOE: Master clock output enable 0: Master clock output is disabled.
  • Page 486 AT32F415 Series Technical Manual 16 CAN Bus Controller 16.1 Introduction bxCAN is the abbreviation of Basic Extended CAN. It supports the CAN protocols version 2.0A and 2.0B. It is designed to manage a large quantity of incoming messages efficiently with a minimum CPU load.
  • Page 487 AT32F415 Series Technical Manual Network Management and Diagnostic messages are also introduced. ● An enhanced filtering mechanism is required to handle different types of messages. In addition, since application tasks take more CPU time, real-time constraints caused by message reception should be reduced. ●...
  • Page 488 AT32F415 Series Technical Manual Figure 18-2 CAN Block Diagram CAN with 512-byte SRAM Receive FIFO 0 Receive FIFO 1 Tx mailboxes mailbox 0 mailbox 0 mailbox 0 Control register Status register Transmission Tx status register scheduler Rx FIFO 0 status register Acceptance filter Rx FIFO 1 status register...
  • Page 489 AT32F415 Series Technical Manual clearing the INRQ bit in the CAN_MCTRL register, and then wait until the hardware sets the IAK bit in the CAN_MSTS register to confirm. The bxCAN enters Normal mode and is ready to transmit and receive messages when it is synchronized with the CAN bus, which means a sequence of 11 consecutive recessive bits (Bus Idle state) on the CANRX pin is detected.
  • Page 490 AT32F415 Series Technical Manual 16.3.3 Test Mode Test modes can be selected by the SIL and/or LBK bits in the CAN_BTMG register. These two bits must be configured in Initialization mode. Once Test mode is selected, the INRQ bit in the CAN_MCTRL register must be reset to successfully enter Test mode.
  • Page 491 AT32F415 Series Technical Manual Figure 18-5 bxCAN in Loopback Mode bxCAN CANTX CANRX Loopback mode can be used for self-test functions. To be independent of external events, the CAN core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data/remote frame) in Loopback mode.
  • Page 492 AT32F415 Series Technical Manual 16.3.3.3 Loopback and Silent Mode Figure 18-6 bxCAN in Loopback and Silent Mode It is also possible to combine Loopback mode and Silent mode by setting both the LBK and SIL bits in the CAN_BTMG register. This mode can be used for a “Hot Self-test”, which means that the bxCAN can be tested like in Loopback mode but without affecting the whole CAN system connected to the CANTX and CANRX pins.
  • Page 493 AT32F415 Series Technical Manual The transmit mailboxes can be configured as transmit FIFO by setting the TFP bit in the CAN_MCTRL register. In this mode, the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by setting the ARQ bit in the CAN_TSTS register.
  • Page 494 AT32F415 Series Technical Manual 16.3.7 Reception Handling The received messages are stored in FIFO with three-level mailbox depth. In order to save CPU load, simplify the software, and ensure data consistency, the FIFO is completely managed by hardware. The application accesses the messages received first in the FIFO only through the FIFO output mailbox.
  • Page 495 AT32F415 Series Technical Manual read the FIFO output mailbox to obtain the messages, and release the mailbox by setting the RRFM bit in the CAN_RF register. Then, the FIFO becomes empty again. If a new valid message is received in the meantime, the FIFO stays in pending_1 state, and software can read the FIFO output mailbox to obtain new messages.
  • Page 496 AT32F415 Series Technical Manual The filter banks are configured through the corresponding CAN_FM register. Before configuring a filter bank, it must be deactivated by clearing the FEN bit in the CAN_FA1 register. The filter scale is configured through the corresponding FBSx bit in the CAN_FS1 register. The identifier list or identifier mask mode for the corresponding mask/identifier registers is configured through the FMSx bit in the CAN_FM1 register.
  • Page 497 AT32F415 Series Technical Manual For filters in identifier list mode (nonmasked filters), the software no longer has to compare the identifier. For masked filters in mask mode, software only compares those masked bits needed (must match bits). When numbering filters, activation state of the filter banks is not taken into account. In addition, each FIFO numbers its own associated filter independently.
  • Page 498 AT32F415 Series Technical Manual ● A 32-bit filter takes priority over a 16-bit filter. ● For filters with equal scale, priority is given to the identifier list mode over the identifier mask mode. ● For filters with equal scale and in the same mode, priority is given according to the filter number (the lower the number, the higher the priority).
  • Page 499 AT32F415 Series Technical Manual information. Transmit mailbox The software should set up the message to be transmitted in an empty transmit mailbox (and then sends transmit requests). The status of the transmission is indicated in the CAN_TSTS register. Table 18-1 Transmit Mailbox Mapping Offset to Transmit Mailbox Base Address Register Name...
  • Page 500 AT32F415 Series Technical Manual 16.3.10 Error Management The error management as described in the CAN protocol is handled entirely by hardware with a Transmit Error Counter (the TEC field in the CAN_ESTS register) and a Receive Error Counter (the REC field in the CAN_ESR register). Its value is incremented or decremented according to the error. For detailed information about TEC and REC management, please refer to the CAN standard.
  • Page 501 AT32F415 Series Technical Manual Figure 18-13 Bit Timing Normal bit time SYNC_SEG Segment 1 (BS1) Segment 2 (BS2) t BS1 1×t q t BS2 Sample Transmit point point Baud rate = Normal bit time t BS1 t BS2 Normal bit time = 1 × Where: t BS1 ×...
  • Page 502 AT32F415 Series Technical Manual Figure 18-14 Various CAN Frames Inter-frame space Data frame (standard identifier) Inter-frame space or overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame space Inter-frame space Data frame ( extended identifier) or overload frame 64 + 8* N...
  • Page 503 AT32F415 Series Technical Manual 16.3.12 bxCAN Interrupt Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by the CAN interrupt enable register (CAN_INTEN). Figure 18-15 Event Flag and Interrupt Generation CAN_INTEN Transmission TMEIE RQC0 &...
  • Page 504 AT32F415 Series Technical Manual 16.4 CAN Registers These peripheral registers must be accessed by words (32-bit). Table 18-3 CAN Register Map and Reset Values Offset Register MCTRL 000h Reserved Reserved Reset Value 0 0 0 0 0 0 1 0 MSTS Reserve 004h...
  • Page 505 AT32F415 Series Technical Manual TMI1 SID/EID[28:18] EID[17:0] 190h Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x TDT1 Reserved Reserved...
  • Page 506 AT32F415 Series Technical Manual 218h Reserved 21Ch Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 220h~ Reserved 23Fh FB0R1 240h Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x FB0R2 244h Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...
  • Page 507 AT32F415 Series Technical Manual TTC: Time-triggered communication mode Bit 7 0: Time-triggered communication mode is disabled. 1: Time-triggered communication mode is enabled. ABO: Automatic bus-off management This bit determines the conditions under which the CAN hardware exits the bus-off state. 0: Software makes requests to leave bus-off state.
  • Page 508 AT32F415 Series Technical Manual 16.4.2.2 CAN Main Status Register (CAN_MSTS) Address offset: 0x04 Reset value: 0x0000 0C02 Reserved Reserved LSAP Reserved SAKIT WKIT ERIT rc w1 rc w1 rc w1 Reserved. Forced to be ‘0’ by hardware. Bit 31:12 RXS: CANRx signal Bit 11 This bit indicates the actual level of the CAN Rx pin (CAN_RX).
  • Page 509 AT32F415 Series Technical Manual 16.4.2.3 CAN Tx Status Register (CAN_TSTS) Address offset: 0x08 Reset value: 0x1C00 0000 LPM2 LPM1 LPM0 TSME2 TSME1 TSME0 NTM[1:0] ARQ2 Reserved TER2 ALS2 TOK2 RQC2 rc w1 rc w1 rc w1 rc w1 ARQ1 Reserved TER1 ALS1 TOK1...
  • Page 510 AT32F415 Series Technical Manual RQC2: Request completed mailbox 2 Set by hardware when the last request (transmit or abort) to mailbox 2 is completed. Cleared by software writing ‘1’ or by hardware on transmission request (TRQ set in the Bit 16 CAN_TMI2 register).
  • Page 511 AT32F415 Series Technical Manual Reserved Reserved Reserved RFP0 rc w1 rc w1 Reserved. Forced to be ‘0’ by hardware. Bit 31:6 RRFM0: Release receive FIFO 0 output mailbox Set by software to release the FIFO output mailbox. Setting this bit when the receive FIFO is empty has no effect;...
  • Page 512 AT32F415 Series Technical Manual RFFU1: FIFO 1 full Bit 3 Set by hardware when three messages are stored in the FIFO 1. This bit is cleared by software. Reserved. Forced to be ‘0’ by hardware. Bit 2 RFP1[1:0]: FIFO 1 message pending These bits indicate the number of messages pending in the receive FIFO 1.
  • Page 513 AT32F415 Series Technical Manual RFOVIE1: FIFO 1 overrun interrupt enable Bit 6 0: No interrupt is generated when the RFOV bit of FIFO 1 is set. 1: An interrupt is generated when the RFOV bit of FIFO 1 is set. RFFUIE1: FIFO 1 full interrupt enable Bit 5 0: No interrupt is generated when the RFFU bit of FIFO 1 is set.
  • Page 514 AT32F415 Series Technical Manual ERC[2:0]: Last error code Set by hardware according to the error condition on detection of CAN bus error. Cleared by hardware after message is correctly transmitted or received. Hardware does not use error code 7; the value of this bit field can be configured by software, so the updates of the code can be monitored.
  • Page 515 AT32F415 Series Technical Manual BS1[3:0]: Time segment 1 Bit 19:16 These bits define the number of time quanta in time segment 1. x (BS1[3:0] + 1) Reserved. Forced to be ‘0’ by hardware. Bit 15:12 BRP[11:0]: Baud rate prescaler These bits define the length of a time quanta (t Bit 11:0 = (BRP[11:0]+1) x t PCLK...
  • Page 516 AT32F415 Series Technical Manual EID[17:0]: Extended identifier Bit 20:3 The LSBs of the extended identifier. IDT: Identifier extension This bit defines the type of identifier of the mailbox messages. Bit 2 0: Standard identifier 1: Extended identifier RTR: Remote transmission request Bit 1 0: Data frame 1: Remote frame...
  • Page 517 AT32F415 Series Technical Manual 16.4.3.2 Mailbox Data Length and Time Stamp Register (CAN_TDTx) (x = 0…2) All bits of this register are write-protected when the mailbox is not in empty state. Address offset: 0x184, 0x194, 0x1A4 Reset value: Undefined TS[15:0] Reserved TMEN Reserved...
  • Page 518 AT32F415 Series Technical Manual D0[7:0]: Data byte 0 Bit 7:0 Data byte 0 of the message 16.4.3.4 Tx Mailbox Data High Register (CAN_TDHx) (x = 0…2) All bits of this register are write-protected when the mailbox is not in empty state. Address offset: 0x18C, 0x19C, 0x1AC Reset value: Undefined D7[7:0] : Data byte 7...
  • Page 519 AT32F415 Series Technical Manual RTR: Remote transmission request Bit 1 0: Data frame 1: Remote frame Bit 0 Reserved 16.4.3.6 Rx FIFO Mailbox Data Length and Time Stamp Register (CAN_RDTx) (x = 0…1) Address offset: 0x1B4, 0x1C4 Reset value: Undefined Note: All Rx mailbox registers are read-only.
  • Page 520 AT32F415 Series Technical Manual D0[7:0]: Data byte 0 Bit 7:0 Data byte 0 of the message A message can contain from 0 to 8 data bytes and starts with byte 0. 16.4.3.8 Rx FIFO Mailbox Data High Register (CAN_RDHx) (x = 0…1) Address offset: 0x1BC, 0x1CC Reset value: Undefined Note: All Rx mailbox registers are read-only.
  • Page 521 AT32F415 Series Technical Manual Reset value: 0x0000 0000 Note: This register can only be written when CAN_FM is set (FINT = 1), which puts filters in Initialization mode. Reserved Reserved Reserved. Forced to be ‘0’ by hardware. Bit 31:14 FMSx : Filter mode The operation mode of filter bank x.
  • Page 522 AT32F415 Series Technical Manual Reserved. Forced to be ‘0’ by hardware. Bit 31:14 FAFx: Filter assignment for FIFO configuration The message passing through certain filter will be stored in the assigned FIFO. Bit 13:0 0: Filter is assigned to FIFO 0. 1: Filter is assigned to FIFO 1.
  • Page 523 AT32F415 Series Technical Manual 16.4.4.5 CAN Filter Activation Register (CAN_FA1) Address offset: 0x21C Reset value: 0x0000 0000 Reserved Reserved Reserved. Forced to be ‘0’ by hardware. Bit 31:14 FENx: Filter active Software sets a certain bit to activate the corresponding filter. To modify the corresponding filter registers x (CAN_FBiRx), the FENx bit must be cleared, or the FINT bit of the CAN_FM Bit 13:0 register must be set.
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  • Page 525 AT32F415 Series Technical Manual 17 SDIO Interface 17.1 Introduction SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus, MultiMediaCard (MMC), SD memory cards, SDIO cards, and CE-ATA devices. The MultiMediaCard system specifications, published by the MMCA technical committee, are available on the MultiMediaCard Association website (www.mmca.org).
  • Page 526 AT32F415 Series Technical Manual Figure 20-1 SDIO “No Response” and “No Data” Operation From host From host From card to card to host to card SDIO_CMD SDIO_D Operation (No response) Operation (No data) Figure 20-2 SDIO (Multiple) Data Block Read Operation From host From card to card...
  • Page 527 AT32F415 Series Technical Manual Figure 20-4 SDIO Sequential Read Operation From host From card to card to host Data from card to Stop command host stops data transfer SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation Data transfer operation Figure 20-5 SDIO Sequential W rite Operation From host...
  • Page 528 AT32F415 Series Technical Manual Figure 20-6 SDIO Block Diagram After reset, SDIO_D0 is used for data transfer by default. After initialization, the host can change the data bus width. If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0], or SDIO_D[7:0] can be used for data transfer.
  • Page 529 AT32F415 Series Technical Manual 17.3.1.1 SDIO Adapter Figure 20-7 shows a simplified block diagram of an SDIO adapter. Figure 20-7 SDIO Adaptor SDIO adapter Control unit SDIO_CK Command path SDIO_CMD Adapter registers To AHB Data path SDIO_D[7:0] Interface SDIOCLK HCLK The SDIO adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card.
  • Page 530 AT32F415 Series Technical Manual Figure 20-8 Control Unit Control unit SDIO_CK Figure 20-8 is the block diagram of control unit. It consists of a power management sub-unit and a clock management sub-unit. The power management subunit disables the card bus output signals at the power-off and power-up phases.
  • Page 531 AT32F415 Series Technical Manual ● Command path state machine (CPSM) ─ When the command register is written, and the enable bit is set, command transfer starts. When the command transfer is completed, the command path state machine (CPSM) sets the status flags and enters the Idle state if a response is not required (See Figure 20-10).
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  • Page 533 AT32F415 Series Technical Manual ● Command format ─ Command: A command is a token that starts an operation. Commands are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available only for MMC V3.31 or previous). Commands are transferred serially on the CMD line.
  • Page 534 AT32F415 Series Technical Manual The command register contains the command index (six bits sent to a card) and the command type; they determine whether the command requires a response and whether the response is 48-bit or 136- bit long (See Section 20.4.4).
  • Page 535 AT32F415 Series Technical Manual Depending on the transfer direction (send or receive), the data path state machine (DPSM) moves to the Wait_S or Wait_R state when it is enabled: ● Send: DPSM moves to the Wait_S state. If there is data in the transmit BUF, DPSM moves to the Send state, and the data path subunit starts sending data to a card.
  • Page 536 AT32F415 Series Technical Manual ● Wait_S: DPSM moves to the Idle state if the data counter is 0. If not, it waits until the data BUF empty flag is deasserted, and then moves to the Send state. Note: DPSM remains at the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
  • Page 537 AT32F415 Series Technical Manual ofdata path asserts DOTX when it transmits data. 2020.06.28 Page 537 Version 1.02...
  • Page 538 AT32F415 Series Technical Manual Table 20-7 Transmit BUF Status Flag Flag Description TXBUF_F Set to high when all 32 transmit BUF words contain valid data. TXBUF_E Set to high when all the 32 transmit BUF words do not contain valid data. Set to high when 8 or more transmit BUF words are empty.
  • Page 539 AT32F415 Series Technical Manual increment, peripheral and source width is word size). d) Enable DMA2 Channel 4 5. Send CMD24 (WRITE_BLOCK) as follows: Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process). Program the SDIO argument register with the address location of the card, where data is to be transferred.
  • Page 540 AT32F415 Series Technical Manual The bus is activated. The SDIO card host broadcasts SEND_OP_COND (CMD1) and receives operation conditions. The response is the “wired AND” of the operation condition registers from all cards. Incompatible cards are placed at the inactive state. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.
  • Page 541 AT32F415 Series Technical Manual indicates the failure on the SDIO_D signal line; the transferred data are discarded and not written, and all further transmitted data blocks (in multiple block write mode) are ignored. If the host uses partial blocks, and the accumulated data length is not block aligned, then block misalignment is not allowed (the CSD parameter, WRITE_BLK_MISALIGN, is not set);...
  • Page 542 AT32F415 Series Technical Manual The maximum clock frequency for a stream write operation is calculated with the following equation: �������������������� ( 8 × 2 ) − 100 ∗ �������� ������ ���������� ������������������ = ������ (������������������, �������� × R2WFACTOR ● Max Write Frequency = The maximum of write frequency ●...
  • Page 543 AT32F415 Series Technical Manual If other commands (neither SEND_STATUS nor erase command) are received, the card sets the ERASE_RESET bit in the status register, resets the erase sequence, and executes a new command. If the erase range includes write protected blocks, they are left intact, and only non-protected blocks are erased.
  • Page 544 AT32F415 Series Technical Manual command byte is sent. ● LOCK_UNLOCK: Setting this bit locks the card. LOCK_UNLOCK can be set simultaneously with SET_PWD, but not with CLR_PWD. ● CLR_PWD: Setting this bit clears the password data. ● SET_PWD: Setting this bit saves the password data to the memory. ●...
  • Page 545 AT32F415 Series Technical Manual LOCK_UNLOCK_FAILED error bit is set in the card status register, and the lock fails. It is possible to set the password and to lock the card in the same sequence. In this case, the host module of SDIO card performs all the required steps mentioned above for setting the password, but it is necessary to set the LOCK_UNLOCK bit in Step 3 when the new password command is sent.
  • Page 546 AT32F415 Series Technical Manual ● X: Detection bit, set during command execution. The SDIO card host must poll the card status by issuing the status command to read these bits. Clear condition: ● A: According to the current card state ●...
  • Page 547 AT32F415 Series Technical Manual Clear Identifier Type Value Description Condition It can be either of the following errors:  The CID register is already written and cannot be overwritten. ‘0’ = No error  The read-only section of the CSD does not 16 CID/CSD_OVERWRITE EX ‘1’...
  • Page 548 AT32F415 Series Technical Manual ● S: Status bit ● R: Detection bit, set according to the actual command response. ● X: Detection bit, set during command execution. The SDIO card host must poll the card status by issuing the status command to read these bits. Clear condition: ●...
  • Page 549 AT32F415 Series Technical Manual Table 20-10 SD Status Clear Identifier Type Value Description Condition ‘00’ = 1 (Default) The current data bus width ‘01’ = Reserved 511:510 DAT_BUS_WIDTH SR defined by SET_BUS_WIDTH ‘10’ = 4-bit wide command ‘11’ = Reserved Card is in secured mode operation ‘0’...
  • Page 550 AT32F415 Series Technical Manual SPEED_CLASS This 8-bit field indicates the speed class and the value that can be calculated by P /2 (where PW is the write performance). Table 20-11 Speed Class Code Field SPEED_CLASS Value Definition Type 0 Type 2 Type 4 Type 6 04h ~ FFh...
  • Page 551 AT32F415 Series Technical Manual The Max. of AU Size 512 KB 1 MB 2 MB 4 MB ERASE_SIZE This 16-bit field indicates N . When N numbers of AUs are erased, the timeout value is ERASE ERASE specified by ERASE_TIMOUT. The host should determine the proper number of AUs to be erased in one operation so that the host can show the progress of the erase operation.
  • Page 552 AT32F415 Series Technical Manual and the card signals interrupt to the MultiMediaCard/SD module with this pin. The use of the interrupt is optional for each card or function within a card. The SD I/O interrupt is level sensitive, which means that the interrupt line must be held active (low) before it is recognized and obtains response from the MultiMediaCard/SD module;...
  • Page 553 AT32F415 Series Technical Manual 2. Send the required ACMD The card responds to the MultiMediaCard/SD module, indicating that the APP_CMD bit is set and that the accepted command is interpreted as an ACMD. When a non-ACMD is sent, it is handled by the card as a normal MultiMediaCard command, and the APP_CMD bit in the card status register is cleared.
  • Page 554 AT32F415 Series Technical Manual If the card provides write protection CLR_WRITE_ CMD29 [31:0] = Data address features, this command clears the write PROT protection bit of the addressed group. If the card provides write protection [31:0] = Write protect SEND_WRITE CMD30 adtc features, this command asks the card to...
  • Page 555 AT32F415 Series Technical Manual Used either to transfer a data block to the card or to get a data block from the card [31:1] = Stuff bits CMD56 adtc GEN_CMD for general purpose/application-specific [0] = RD/WR commands. The size of the data block is set by the SET_BLOCK_LEN command.
  • Page 556 AT32F415 Series Technical Manual End bit 17.3.3.4 R3 (The OCR Register) Code length: 48 bits. The contents of the OCR register are sent as a response to CMD1.The level code is defined as: Restricted voltage windows = low, card busy = low. Table 20-26 R3 Response Width (Bit)
  • Page 557 AT32F415 Series Technical Manual Once an SD I/O card receives a CMD5, the I/O part of the card is enabled to respond normally to all further commands. This enabled state of the I/O function within the card will remain set until the next reset, power-off, or CMD52 of I/O reset is received.
  • Page 558 AT32F415 Series Technical Manual 17.3.3.7 R5 (Interrupt Request) Only for MultiMediaCard. Code length: 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0. Table 20- 29 R5 Response Width (Bit) Value Description Start bit Transmission bit...
  • Page 559 AT32F415 Series Technical Manual 17.3.4.1 SDIO I/O Read Wait Operation by SDIO_D2 Signaling Read wait interval can be started before the first block is received; when the data path is enabled (the SDIO_DTCTRL[0] bit set), the SDIO-specific operation is enabled (the SDIO_DTCTRL[11] bit set), read wait starts (SDIO_DTCTRL[10] =0 and SDIO_DTCTRL[10] =1), and data direction is from card to SDIO (SDIO_DTCTRL[1] = 1), DPSM will directly move from Idle to read wait.
  • Page 560 AT32F415 Series Technical Manual If the ‘enable CMD completion’ bit in SDIO_CMD[12] is set, and the ‘non-interrupt enable’ bit in SDIO_CMD[13] is set, CPSM waits for the command completion signal at the Waitcpl state. When ‘0’ is received on the CMD line, CPSM enters the Idle state. No new command can be sent within the 7 cycles.
  • Page 561 AT32F415 Series Technical Manual SDIO_RSPC RSPCMD[5:0] 0x10 Reserved 0x00000000 0 0 0 0 0 0 SDIO_RSP1 CARDSTS1[31:0] 0x14 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDIO_RSP2 CARDSTS2[31:0] 0x18...
  • Page 562 AT32F415 Series Technical Manual Reset value: 0x00000000 Reserved Reserved PWRCTRL Bit 31:2 Reserved. Always read as 0. PWRCTRL: Power supply control bits These bits are used to define the current functional state of the card clock: 00: Power-off: The clock to card is stopped. Bit 1:0 01: Reserved 10: Reserved power-up...
  • Page 563 AT32F415 Series Technical Manual BYPS: Clock divider bypass enable bit 0: Disable bypass: SDIOCLK is divided according to the CLKPSC value before driving Bit 10 the SDIO_CK output signal. 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal. PWRSVG: Power saving configuration bit To save power, setting the PWRSVG bit can disable SDIO_CK clock output when the Bit 9 bus is idle.
  • Page 564 AT32F415 Series Technical Manual CMPL ATAC INTDI SDIO INTW erve RSPWT CMDIDX SGNL SUSP Bit 31:15 Reserved. Always read as 0. ATACMD: CE-ATA command Bit 14 If this bit is set, CPSM transfers CMD61. INTDIS: Interrupt disable Bit 13 If this bit is not set, interrupts of CE-ATA devices are enabled. CMPLSGNLEN: Enable CMD completion Bit 12 If this bit is set, the command completion signal is enabled.
  • Page 565 AT32F415 Series Technical Manual Reserved RSPCMD Bit 31:6 Reserved. Always read as 0. RSPCMD: Response command index Bit 5:0 Read-only bit field, which contains the command index of the last command response received. 17.4.6 SDIO Response 1…4 Register (SDIO_RSPx) Address offset: 0x14 + 4 * (x - 1), where x = 1…4 Reset value: 0x00000000 The SDIO_RSP1/2/3/4 register contains the card state;...
  • Page 566 AT32F415 Series Technical Manual TIMEOUT TIMEOUT: Data timeout period Bit 31:0 Data timeout period expressed in card bus clock periods Note: Before writing to data control register to perform data transfer, the data timer register and the data length register must be written first. 17.4.8 SDIO Data Length Register (SDIO_DTLEN) Address offset: 0x28...
  • Page 567 AT32F415 Series Technical Manual RDWTMODE: Read wait mode Bit 10 0: Read wait is controlled by SDIO_D2. 1: Read wait is controlled by SDIO_CK. RDWTSTOP: Read wait stop Bit 9 0: Read wait is in progress if RDWTSTART is set. 1: Read wait stops if RDWTSTART is set.
  • Page 568 AT32F415 Series Technical Manual Bit 31:25 Reserved. Always read as 0. CNT: Data count value Bit 24:0 Reading this bit is returns the number of remaining data bytes to be transferred. Writing to this register has no effect. Note: This register should be read only when the data transfer is complete d. 17.4.11 SDIO Status Register (SDIO_STS) Address offset: 0x34 Reset value: 0x00000000...
  • Page 569 AT32F415 Series Technical Manual Bit 10 DTBLKCMPL: Data block sent/received (CRC check passed) SBITERR: Start bit not detected on all data signals in wide bus mode Bit 9 DTCMPL: Data end (The data counter SDIO_DTCNTR = 0) Bit 8 CMDCMPL: Command sent (No response required) Bit 7 CMDRSPCMPL: Command response received (CRC check passed) Bit 6...
  • Page 570 AT32F415 Series Technical Manual RXERRO: RXERRO flag clear bit Bit 5 This bit is set by software to clear the RXERRO flag. TXERRU: TXERRU flag clear bit Bit 4 This bit is set by software to clear the TXERRU flag. DTTIMEOUT: DTTIMEOUT flag clear bit Bit 3 This bit is set by software to clear the DTTIMEOUT flag.
  • Page 571 AT32F415 Series Technical Manual TXBUF_E: Tx BUF empty interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated by Tx BUF empty. Bit 18 0: Tx BUF empty interrupt is disabled. 1: Tx BUF empty interrupt is enabled. RXBUF_F: Rx BUF full interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated by Rx BUF full.
  • Page 572 AT32F415 Series Technical Manual RXERRO: Rx BUF overrun error interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated by Rx BUF Bit 5 overrun error. 0: Rx BUF overrun error interrupt is disabled. 1: Rx BUF overrun error interrupt is enabled. TXERRU: Tx BUF underrun error interrupt enable This bit is set/cleared by software to enable/disable the interrupt generated by Tx BUF Bit 4...
  • Page 573 AT32F415 Series Technical Manual to read from/write to the BUF. DT: Receive and transmit BUF data Bit 31:0 The BUF data occupies 32 entries of 32-bit words, from address: (SDIO base + 0x80) to (SDIO base + 0xFC) 2020.06.28 Page 573 Version 1.02...
  • Page 574 AT32F415 Series Technical Manual 2020.06.28 Page 574 Version 1.02...
  • Page 575 AT32F415 Series Technical Manual 18 MCU Debug (MCUDBG) 18.1 Introduction ® AT32F415 are built with the Cortex -M4F core, which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint).
  • Page 576 AT32F415 Series Technical Manual 18.2 Function Overview 18.2.1 Debug Support for Low-power Mode To enter low-power mode, the instruction of WFI and WFE are executed. MCU supports several low-power modes, which can either deactivate the CPU clock or reduce the power consumption of the CPU.
  • Page 577 AT32F415 Series Technical Manual DBGMCU_CTRL Trace Pin Assignment Register Pin Assigned For TRACE TRACE PB3/JTDO/TR PE2/TRA PE3/TRA PE4/TRA PE5/TRA PE6/TRA _IOEN _MODE[1:0] ACESWO CECK CED[0] CED[1] CED[2] CED[3] No trace (Note) Released (By default) Released (Used as GPIOs) Asynchronous TRACES trace Synchronous TRAC...
  • Page 578 AT32F415 Series Technical Manual 18.3.1 MCUDBG Control Register (MCUDBG_CTRL) The MCUDBG_CTRL register is mapped on the external PPB bus at base address, 0xE0042000. It is asynchronously reset by PORESET (and not by system reset). It can be written by the debugger when the core is at reset state.
  • Page 579 AT32F415 Series Technical Manual TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control - When TRACE_IOEN = 0: TRACE_MODE = xx: Trace pins are not assigned (Default state). - When TRACE_IOEN = 1: Bit 7:5 TRACE_MODE = 00: Trace pin assignment for asynchronous mode TRACE_MODE = 01: Trace pin assignment for synchronous mode, with data size of 1 TRACE_MODE = 10: Trace pin assignment for synchronous mode, with data size of 2 TRACE_MODE = 11: Trace pin assignment for synchronous mode, with data size of 4...
  • Page 580 AT32F415 Series Technical Manual 19 Comparator (COMP) 19.1 COMP Introduction AT32F415 has two embedded ultra-low-power consumption comparators, COMP1 and COMP2. They can be used as independent devices (all ports are provided on I/O), or used together with timers. Comparators feature multiple functions, including: ...
  • Page 581 AT32F415 Series Technical Manual 19.3.2 COMP Pins and Internal Signals When I/Os are used as comparator inputs, they should be configured to analog mode in the GPIOs register. With the alternate function channel provided in the data sheet, comparator output can be mapped to I/O.
  • Page 582 AT32F415 Series Technical Manual 19.3.6 Power Mode For a given application, COMP power consumption and transfer hysteresis can be adjusted to reach the ideal balance. The COMPx_MDE bit in the COMP_CTRLSTS1 register can be programmed to provide higher speed/power or lower speed/power. 19.3.7 Interference Filter Interference filter can be used to filter glitch and noise interference.
  • Page 583 AT32F415 Series Technical Manual used for exiting low-power mode. Comparator 1 generates interrupt or event via EXTI line 19, and Comparator 2 via EXTI line 20. For more detailed information, please refer to the section of interrupts and events. 19.5 COMP Register Table 19-1 COMP Register Mapping and Reset Value Offset...
  • Page 584 AT32F415 Series Technical Manual COMP2LOCK: Comparator 2 lock This bit is set by software and cleared by system reset. It locks all contents of Bit 31 COMP_CTRLSTS1[31:16] and COMP_CTRLSTS2[31:0] of the comparator control registers. 0: Comparator COMP_CTRLSTS1[31:16] and COMP_CTRLSTS2[31:16] can be read/written. 1: Comparator COMP_CTRLSTS1[31:16] and COMP_CTRLSTS2[31:16] is read-only.
  • Page 585 AT32F415 Series Technical Manual 11: High hysteresis Please refer to hysteresis electrical characteristics. COMP1POL: Comparator 1 polarity selection bit This bit makes the polarity of Comparator 1 the opposite. Bit 11 0: Comparator 1 output value is not the opposite. 1: Comparator 1 output value is the opposite.
  • Page 586 AT32F415 Series Technical Manual 00: PA7 01: PA3 (Default input ) 10: PA2 11: Reserved Note: When COMP2_LOCK = 1, these bits are read-only. Bit 15:2 Reserved, kept at reset value. COMP1INPSEL: Comparator 1 non-inverting input selection These bits select the non-inverting input of Comparator 1. After reset, the value is 01, which means to select PA1.
  • Page 587 AT32F415 Series Technical Manual Bit 15:6 Reserved, always read as 0. L_PULSE_CNT: Low pulse count Invalid level change of filter input signal should be stable at least for L_PULSE_CNT+1 clock cycles, then it can be considered as valid input, and the output will turn to low level. 0: 1 pclk clock Bit 5:0 1: 2 pclk clocks...
  • Page 588 AT32F415 Series Technical Manual 20 HSI Auto Clock Calibration 20.1 ACC Introduction HSI Auto Clock Calibration (HSI ACC) utilizes the SOF signal (with cycle of 1 millisecond) generated by the USB module, to realize sampling and calibration to the HSI clock. The main function of this module is to provide clock with 48-MHz ±...
  • Page 589 AT32F415 Series Technical Manual frequency will decrease by 40 kHz (design value). ● HSITWK: Calibration signal of HSI module. For the divided (1/6) HSI clock, every HSITWK step variation will trim the divided (1/6) HSI clock by 20 kHz frequency (design value), and it is positive correlation.
  • Page 590 AT32F415 Series Technical Manual sampling cycle will be either < C2 or > C2. When this value is < C2, automatic calibration will increase HSICAL or HSITWK based on step definition until the actual sampling value is > C2, to realize the cross of sampling value from < C2 to > When this value is >...
  • Page 591 AT32F415 Series Technical Manual CALRDY CALRDYIEN Interrupt RSLOST EIEN 20.5 ACC Register Description For the abbreviations in the register description, please refer to Section 1.4.1. These peripheral registers can be accessed by half-word (16-bit) or word (32-bit). 20.5.1 ACC Register Address Mapping Offset Register ACC_STS...
  • Page 592 AT32F415 Series Technical Manual 20.5.2 Status Register (ACC_STS) Address offset: 0x00 Reset value: 0x0000 Reserved RSLOS CALRD Bit 31:3 Reserved, forced to be 0 by hardware. RSLOST: Reference Signal Lost During calibration process, if the sampling counter value of calibration module is twice of C2, and SOF reference signal has not been detected, then it means that reference signal is lost.
  • Page 593 AT32F415 Series Technical Manual CALRDYIEN: CALRDY interrupt enable This bit is set or cleared by software. Bit 5 0: Interrupt generation is disabled. 1: When CALRDY in ACC_STS is ‘1’, generate ACC interrupt. EIEN: RSLOST error interrupt enable This bit is set or cleared by software. Bit 4 0: Interrupt generation is disabled.
  • Page 594 AT32F415 Series Technical Manual 20.5.5 Compare Value 1 (ACC_C1) Address offset: 0x0C Reset value: 0x1F2C Reserved Bit 31:16 Reserved, forced to be 0 by hardware. C1: Compare 1 This value is the lower boundary of trigger calibration; the default value is 7980. When automatic calibration module’s sampling clock number <...
  • Page 595 AT32F415 Series Technical Manual 21 USB OTG Full-speed (OTG_FS) 21.1 OTG Module Introduction Portions Copyright (c) Synopsys, Inc (2004 and 2005). All rights reserved. Used with permission. This chapter introduces the structure and use of OTG_FS Core. Terminology: FS: Full speed LS: Low speed USB: Universal Serial Bus OTG: On-the-Go...
  • Page 596 AT32F415 Series Technical Manual 21.2.2 Host Mode Function OTG_FS interface: ● An external charge pump is required to supply VBUS. ● Supports up to 8 host channels, each can be dynamically configured as any transfer type. ● Embedded hardware scheduling controller: ─...
  • Page 597 AT32F415 Series Technical Manual 21.3 OTG_FS Function Descriptions Figure 21-1 Function Diagram Cortex-M4 core USB interrupt Pow er and cl ock USB2.0 control OTG FS Core USB suspend System USB Clock clock area area USB bus 1.25-Kbyte USB data FIFO 21.3.1 OTG Full-speed Core USB OTG full-speed core obtains 48 MHz ±...
  • Page 598 AT32F415 Series Technical Manual ● DP/DM line has embedded pull-up/pull-down resistor, controlled by OTG_FS Core to satisfy current device needs. In device mode, when high-level (B-type effective) occurs on VBUS, the controller will enable DP line’s pull-up resistor to inform the host the connection of a USB full-speed device.
  • Page 599 AT32F415 Series Technical Manual Figure 21-3 Simple USB Peripheral Connections 5 V to VDD V ol t age r egul at or AT32F415xx VBUS PA11 OSC_IN PA12 OSC_OUT 1.A bus power supply device can be designed by using voltage regulator. 2.VDD ranges from 2 V to 3.6 V.
  • Page 600 AT32F415 Series Technical Manual to confirm suspend. The device suspend bit in the device status register (the SUSPSTS bit in the OTG_FS_DSTS register) will be automatically set, and the OTG_FS core enters suspend state. The device can autonomously exit the suspend state by setting the remote wakeup signal bit (the RWKUPSIG bit in the OTG_FS_DCTL register) in the device control register and clearing the bit between 1 ms and 15 ms.
  • Page 601 AT32F415 Series Technical Manual ─ Set odd/even frame of the transfer frame that should be transmitted or received (Only effective to isochronous transfer) ─ Optional configuration: Set the NAK bit to response host with NAK regardless of the FIFO status ─...
  • Page 602 AT32F415 Series Technical Manual . Note: The controller cannot use 5-V VBUS power supply, so an external charge pump is required. If the application board can provide 5-V power supply, then the basic switch power can drive the 5-V VBUS. The external charge pump can be controlled by any universal I/O port. This design is needed for OTG A-type host, A-type device, and USB host.
  • Page 603 AT32F415 Series Technical Manual Once host detects device connection, it should enter enumeration process to transmit USB reset and configuration command to the new connected device. Since the connected device has pull-up resistor on DP (full-speed device) or DM (low-speed device) line, it will cause instability of the bus. When bus goes back to stable status, the OTG interrupt (the DBTDONE bit in the OTG_FS_GOTGINT Register) will be triggered;...
  • Page 604 AT32F415 Series Technical Manual configured first. Once the channel is enabled, the transfer size register will become read-only, and can only be updated by OTG_FS core. ● The following transfer parameters can be configured: ─ Single packet transfer size in bytes ─...
  • Page 605 AT32F415 Series Technical Manual ─ IN/OUT token, host channel number, and other status information Since each request queue can store up to 8 requests, application can therefore use this characteristic to push at most 8 periodic transfer requests and 8 non-periodic transfer requests to increase transfer efficiency.
  • Page 606 AT32F415 Series Technical Manual 21.7 SOF Trigger Figure 21-5 SOF Connection AT32F415 SOF output to external audio control VBUS PA11 ITRE pulse PA12 TIM2 PA10 generator OTG_FS core provides: ● SOF monitoring, tracking, and configuring ● SOF pulse output Since audio device should be isochronous with PC data, or the host should adjust frame frequency according to the audio device requirement, these functions are very useful to the clock output of audio application.
  • Page 607 AT32F415 Series Technical Manual The OTG PHY power supply is determined by the following 3 bits in the general controller configuration register: ● PHY power supply bit (the PWRDOWN bit in the GCCFG register) ─ Switch of PHY full-speed transceiver module. This bit should be configured in advance to allow USB communication.
  • Page 608 AT32F415 Series Technical Manual 21.9 USB Data FIFO Figure 21-6 shows the diagram of OTG_FS core and functions. Figure 21-6 OTG_FS Core Diagram AHB slave interface BIUS AHB Slave unit PSRAM FS serial interface BIUS: bus interface unit; AIU: application interface unit; PFC: packet FIFO controller; MAC: media access controller;...
  • Page 609 AT32F415 Series Technical Manual 21.10 Device FIFO Architecture FIFO Address Mapping and AHB FIFO Mapping in Device Mode Figure 21-7 A data FIFO DIEPTXF2[31:16] Write access from AHB Dedicated TX TX FIFO #n message to IN endpoint TX FIFO FIFO #n control DIEPTXFx[15:0] #n DFIFO (Optional)
  • Page 610 AT32F415 Series Technical Manual Dedicated FIFO structure is very flexible, which can greatly decrease application’s loading. These FIFOs do not have request sequence, and there is no need to predict access sequence when USB host accesses non-periodic endpoint. Based on the non-periodic TX FIFO empty level bit (the TXFEMLVL bit in the OTG_FS_GAHBCFG register) configured in the AHB configuration register, OTG_FS core will generate periodic TX FIFO empty interrupt (the NPTXFEMP bit in the OTG_FS_GINTSTS register) to indicate the corresponding IN endpoint that TX FIFO is half empty or completely empty.
  • Page 611 AT32F415 Series Technical Manual 21.11.2 Host TX FIFO In host mode, controller uses one TX FIFO to manage all non-periodic (control and bulk transfer) OUT transfers and uses the other TX FIFO to manage all periodic (isochronous and interrupt) OUT transfer.
  • Page 612 AT32F415 Series Technical Manual 21.13 OTG_FS Interrupt No matter OTG_FS core works in host mode or device mode, the application cannot access the registers in the other mode. If there is illegal access on the application, mode mismatch interrupt will be generated and affect the corresponding bit (the MODMIS bit in the OTG_FS_GINTSTS register) in the controller interrupt register.
  • Page 613 AT32F415 Series Technical Manual ● Host channel register set ● Device mode register set ● Device global register set ● Device endpoint register set ● Power and clock gating register set ● Data FIFO (DFIFO) access register set Only controller global register, Power and clock gating register, data FIFO access register, and host port control and status register are valid in both host mode and device mode.
  • Page 614 AT32F415 Series Technical Manual Global CSR address mapping These registers are valid both in host mode and device mode . Table 21-3 Controller Global Control and Status Register (CSRs) Register Code Offset address Register Name OTG_FS_GAHBCFG 0x008 OTG_FS AHB Configuration Register OTG_FS_GUSBCFG 0x00C OTG_FS USB Configuration Register...
  • Page 615 AT32F415 Series Technical Manual Device mode CSR address mapping These registers should be configured every time when switching to the device mode. Table 21-5 Device Mode Control and Status Register Register Code Offset address Register Name OTG_FS_DCFG 0x800 OTG_FS Device Configuration Register OTG_FS_DCTL 0x804 OTG_FS Device Control Register...
  • Page 616 AT32F415 Series Technical Manual Table 21-6 Data FIFO (DFIFO) Access Register Data FIFO (DFIFO) access register Address Range Access Device IN endpoint 0/Host OUT channel 0: DFIFO write-only write access 0x1000~0x1FFC Device OUT endpoint 0/Host IN channel 0: DFIFO read-only read access Device IN endpoint 1/Host OUT channel 1: DFIFO write-only write access...
  • Page 617 AT32F415 Series Technical Manual 21.14.2 OTG_FS Register Address Mapping Table 21-9 shows the USB OTG register mappings and reset values. Table 21-9 OTG_FS Register Mapping and Reset Values Offset Register OTG_FS_GAHBCFG 008h Reserved Reserved Reset Value OTG_FS_GUSBCFG TRDTIM 00Ch Reserved Reserved Reset Value 0 0 1 0 1...
  • Page 618 AT32F415 Series Technical Manual OTG_FS_GRXFSIZ RXFDEP 024h Reserved Reset Value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_FS_GNPTXFSIZ NPTXFDEP NPTXFSTADDR 028h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 OTG_FS_GNPTXSTS NPTXQTOP NPTREQXSAVAIL...
  • Page 619 AT32F415 Series Technical Manual OTG_FS_HCCHAR2 DEVADDR EPTNUM MAXPSIZE 540h Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_HCCHAR3 DEVADDR EPTNUM...
  • Page 620 AT32F415 Series Technical Manual Offset Register OTG_FS_HCINT6 5C8h Reserved Reset Value 0 0 0 0 0 0 0 OTG_FS_HCINT7 5E8h Reserved Reset Value 0 0 0 0 0 0 0 OTG_FS_HCINTMSK0 50Ch Reserved Reset Value 0 0 0 0 0 0 0 0 OTG_FS_HCINTMSK1 52Ch Reserved...
  • Page 621 AT32F415 Series Technical Manual OTG_FS_DCFG DEVADDR 800h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DCTL TSTCTRL 804h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DSTS SOFFN 808h...
  • Page 622 AT32F415 Series Technical Manual Offset Register OTG_FS_DIEPCTL2 TXFNUM MAXPSIZE 940h Reserved Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DTXFSTS2 INEPTFSAV 958h...
  • Page 623 AT32F415 Series Technical Manual Offset Register OTG_FS_DIEPINT3 908h Reserved Reset Value OTG_FS_DOEPINT0 B08h Reserved Reset Value OTG_FS_DOEPINT1 B28h Reserved Reset Value OTG_FS_DOEPINT2 B48h Reserved Reset Value OTG_FS_DOEPINT3 B68h Reserved Reset Value PKTCN OTG_FS_DIEPTSIZ0 XFERSIZE 910h Reserved Reserved Reset Value 0 0 0 0 0 0 0 OTG_FS_DIEPTSIZ1 MCNT PKTCNT...
  • Page 624 AT32F415 Series Technical Manual 21.14.3 OTG_FS Global Registers These registers are Accessible in both device mode and host mode, and do not need re-initialization when switching to different modes. If there is no special notes, every bit value in the registers is shown in a binary manner. 21.14.4 OTG_FS AHB Configuration Register (OTG_FS_GAHBCFG) Address offset: 0x08 Reset value: 0x0000 0000...
  • Page 625 AT32F415 Series Technical Manual 21.14.5 OTG_FS_USB Configuration Register (OTG_FS_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 0A00 This register is used to configure core during power-on or core mode switch. It mainly configures USB and USB PHY relevant parameters. The application should configure this register first before transferring data to AHB or USB.
  • Page 626 AT32F415 Series Technical Manual USB specification defines that full-speed packet timeout standard is 16-bit to 18-bit times. The application should set this bit according to speed of enumeration. The added bit time of PHY clock is 0.25-bit times. 21.14.6 OTG_FS Reset Register (OTG_FS_GRSTCTL) Address offset: 0x10 Reset value: 0x2000 0000 The application can reset each core hardware module with this register.
  • Page 627 AT32F415 Series Technical Manual current transaction and turn to idle state, and clearing the CSR control bits in the status device driven by AHB clock field. To clear this interrupt, the status mask bit generated for control interrupt status and AHB clock field driven device will be cleared.
  • Page 628 AT32F415 Series Technical Manual Reserved rc_w1 WKUPINT: Resume/remote wakeup detected interrupt In device mode, this interrupt is generated when detecting resume signal on USB; in Bit 31 host mode, this interrupt is generated when detecting remote wakeup signal on USB. Note: Accessible in both device mode and host mode Bit 30 Reserved...
  • Page 629 AT32F415 Series Technical Manual Note: Accessible only in device mode IEPTINT: IN endpoint interrupt In device mode, the core sets this bit to indicate that there is a pending IN endpoint event. The application needs to read device all endpoint interrupt register (OTG_FS_DAINT) to get the endpoint number of the generated interrupt event, and then Bit 18 reads the corresponding device IN endpoint x interrupt register (OTG_FS_DIEPINTx) to...
  • Page 630 AT32F415 Series Technical Manual Note: Accessible in both device mode and host mode OTGINT: OTG interrupt The core sets this bit to indicate that an OTG protocol event occurs. The application must read the OTG interrupt register (OTG_FS_GOTGINT) to get the detailed Bit 2 information of the generated interrupt.
  • Page 631 AT32F415 Series Technical Manual Bit 27 Reserved PTXFEMPM: Periodic TX FIFO empty mask 0: Mask interrupts Bit 26 1: Unmask interrupts Note: Accessible only in host mode HCHINTM: Host channels interrupt mask 0: Mask interrupts Bit 25 1: Unmask interrupts Note: Accessible only in host mode HPORTINTM: Host port interrupt mask 0: Mask interrupts...
  • Page 632 AT32F415 Series Technical Manual 1: Unmask interrupts Note: Accessible only in device mode GINNAKEFFM: Global non-periodic IN NAK effective mask 0: Mask interrupts Bit 6 1: Unmask interrupts Note: Accessible only in device mode NPTXFEMPM: Non-periodic TX FIFO empty mask 0: Mask interrupts Bit 5 1: Unmask interrupts...
  • Page 633 AT32F415 Series Technical Manual 0101: Data reverse bit error (trigger interrupt) 0111: Channel stops. (trigger interrupt) Others: Reserved DPID: Data PID It indicates the data PID of received data packet. 00: DATA0 Bit 16:15 10: DATA1 01: DATA2 11: MDATA BCNT: Byte count Bit 14:4 It indicates the byte count of received data packet.
  • Page 634 AT32F415 Series Technical Manual RXFDEP r/rw Bit 31:16 Reserved RXFDEP: RX FIFO depth This value is expressed in 32-bit words. Bit 15:0 The minimum value is 16. The maximum value is 256. Power-on reset value is the maximum depth value of RX FIFO. 21.14.11 OTG_FS Non-Periodic TX FIFO Size Register (OTG_FS_GNPTXFSIZ) Address offset: 0x028...
  • Page 635 AT32F415 Series Technical Manual 00: IN/OUT token 01: Transfer zero-length packet (device IN/host OUT) 11: Channel stop token Bit 24: End (the last request of the selected channel/endpoint) NPTREQXSAVAIL: Non-periodic transmit request queue space available It indicates the space available in non-periodic transfer request queue. In host mode, this queue stores IN transfer requests and OUT transfer requests;...
  • Page 636 AT32F415 Series Technical Manual 21.14.14 OTG_FS Core ID Register (OTG_FS_GUID) Address offset: 0x03C Reset value: 0x0000 1000 This register is read-only to protect product ID. USERID USERID USERID: Product ID field Bit 31:0 The application can program this ID field. 21.14.15 OTG_FS Host Periodic TX FIFO Size Register (OTG_FS_HPTXFSIZ) Address offset: 0x100...
  • Page 637 AT32F415 Series Technical Manual r/rw INEPTXFDEP: IN endpoint TX FIFO depth This value is expressed in 32-bit words. Bit 31:16 The minimum value is 16. The maximum value is 512. Reset value is the max. possible IN endpoint TX FIFO depth. INEPTXSTADDR: IN endpoint FIFOx transmit RAM start address Bit 15:0 This value is the start address of IN endpoint TX FIFO in RAM.
  • Page 638 AT32F415 Series Technical Manual Reset value: 0x0000 EA60 This register configures frame interval time for OTG_FS core selected speed in enumeration Reserved FRAINT Bit 31:16 Reserved FRAINT: Frame interval The application sets the time interval between two consecutive SOFs (full-speed) or keep-alive (low-speed) with this bit. This register indicates the frame interval in number of PHY clocks.
  • Page 639 AT32F415 Series Technical Manual PTXQTOP PTXQSPCAVL PTXFSPCAVL PTXQTOP: Top of the periodic transmit request queue It indicates that the periodic transmit request that is being processed by MAC. This register is used only for module debugging. Bit 31: Odd/Even frame 0: Even frame transmit 1: Odd frame transmit Bit 31:24...
  • Page 640 AT32F415 Series Technical Manual HAINT: Channel interrupts Bit 15:0 Each bit corresponds to a channel: Bit 0 corresponds to channel 0, and bit 15 corresponds to channel 15. 21.14.23 OTG_FS Host All Channel Interrupt Mask Register (OTG_FS_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 This register is used with the OTG_FS_HAINT register for interrupting the application when events are generate.
  • Page 641 AT32F415 Series Technical Manual PRTSPD: Port speed It indicates speed of the device connected to port. Bit 18:17 01: Full-speed device 10: Low-speed device 11: Reserved PRTTSCTRL: Port test control The application enters test mode by writing non-0 value to this bit; the corresponding signal will appear on the port.
  • Page 642 AT32F415 Series Technical Manual PRTENCHNG: Port enable/disable change Bit 3 The core sets this bit when the port enable bit (Bit 2) in this register has changes. PRTENA: Port enable The port can be enabled by the core only after the reset sequence. It is disabled when there is over current, device disconnect, or when the core clears this bit.
  • Page 643 AT32F415 Series Technical Manual EPTYPE: Endpoint type It indicates the selected transaction type. 00: Control transfer Bit 19:18 01: Isochronous transfer 10: Bulk transfer 11: Interrupt transfer LSPDDEV: Low speed device Bit 17 The application sets this bit to indicate that the device is low-speed device. Bit 16 Reserved EPTDIR: Endpoint direction...
  • Page 644 AT32F415 Series Technical Manual XFERC: Transfer completed Bit 0 Transfer is completed normally without errors. 21.14.27 OTG_FS Host Channel x Interrupt Mask Register (OTG_FS_HCINTMSKx)(where x is channel number, x = 0...7) Address offset: 0x50C + (channel number × 0x20) Reset value: 0x0000 0000 This register is used to mask various channel interrupts mentioned in the last section.
  • Page 645 AT32F415 Series Technical Manual DPID PKTCNT XFERSIZ XFERSIZ Bit 31 Reserved DPID: Data PID The application informs the core of the PID type used in the initial transaction by this bit. The core will automatically control the PID type of the following transfers. Bit 30:29 00: DATA0 01: DATA2...
  • Page 646 AT32F415 Series Technical Manual The application fills this bit after receiving SetAddress control token based on the parameters. Bit 3 Reserved NZLSTSOHSK: Non-zero-length status OUT handshake At control transfer status, if a non-zero-length data packet is received, the application can select to transmit a handshake signal through this bit. 1: Transmit STALL handshake to non- zero -length status OUT transfer and do not Bit 2 send received OUT packet to the application...
  • Page 647 AT32F415 Series Technical Manual Others: Reserved GOUTNAKSTS: Global OUT NAK status 0: Transmit handshake signal according to FIFO status and NAK/STALL bit status Bit 3 1: Regardless of whether memory is empty or not, data is not written to the RX FIFO. Transmit NAK handshake signal to all transactions except for SETUP, and abandon all isochronous OUT packets.
  • Page 648 AT32F415 Series Technical Manual Bit 31:22 Reserved Bit 21:8 SOFFN: Frame number of the received SOF Bit 7:4 Reserved ETICERR: Erratic error The core sets this bit when erratic error occurs. If erratic error occurs, the OTG_FS core will enter suspend state and set early suspend in the core interrupt register. Bit 3 Afterwards, the ESUSP bit in the OTG_FS_GINTSTS register will generate interrupt.
  • Page 649 AT32F415 Series Technical Manual INEPTNMISM: IN token received with EP mismatch mask Bit 5 0: Mask interrupts 1: Unmask interrupts INTTXFEM: IN token received when TX FIFO empty mask Bit 4 0: Mask interrupts 1: Unmask interrupts TIMEOUT: Timeout condition mask (Non-isochronous endpoints) Bit 3 0: Mask interrupts 1: Unmask interrupts...
  • Page 650 AT32F415 Series Technical Manual OUTTEPDM : OUT token received when endpoint disabled mask Bit 4 0: Mask interrupts 1: Unmask interrupts SETUPM: SETUP phase done mask Only valid to control endpoint effective Bit 3 0: Mask interrupts 1: Unmask interrupts Bit 2 Reserved EPTDISM: Endpoint disabled interrupt mask...
  • Page 651 AT32F415 Series Technical Manual corresponding bits in the device all endpoint interrupt register (OTG_FS_DAINT) is still set when being masked. OUTEPTM INEPTM OUTEPTM: OUT EP interrupt mask bits Each bit corresponds to an OUT endpoint. Bit 31:16 Bit 16 corresponds to OUT endpoint 0, and Bit 31 corresponds to OUT endpoint 15. 0: Mask interrupts 1: Unmask interrupts INEPTM: IN EP interrupt mask bits...
  • Page 652 AT32F415 Series Technical Manual This section describes device control IN endpoint 0 control register. Non-0 control endpoint uses the corresponding endpoint 1-15 registers. Reserved TXFNUM EPTYPE Reserved MAXPSIZE EPTENA: Endpoint enable The application sets this bit to enable data transaction at endpoint 0. The core will Bit 31 clear this bit before generating the following endpoint interrupts: 0: The endpoint is disabled.
  • Page 653 AT32F415 Series Technical Manual 01: 32 bytes 10: 16 bytes 11: 8 bytes 21.14.39 OTG_FS Device Endpoint x Control Register (OTG_FS_DIEPCTLx)(where x is endpoint number, x = 1...3) Address offset: 0x900 + (endpoint number x 0x20) Reset value: 0x0000 0000 The application controls the operation of endpoints, except for endpoint 0.
  • Page 654 AT32F415 Series Technical Manual STALL: STALL handshake Only valid to non-control and non-isochronous IN endpoint (operation type is rw). After the application sets this bit, the endpoint will response all host commands with STALL. Even the NAK bit, global IN NAK bit, or global OUT NAK bit are set at the same time, the STALL bit still has the highest priority.
  • Page 655 AT32F415 Series Technical Manual Reserved Reserved EPTYPE Reserved MAXPSIZE EPTENA: Endpoint enable The application sets this bit to enable data transaction at endpoint 0. The core will clear this bit before generating the following endpoint interrupts: Bit 31 SETUP phase is completed. Endpoint is disabled.
  • Page 656 AT32F415 Series Technical Manual 21.14.41 OTG_FS Device OUT Endpoint x Control Register (OTG_FS_DOEPCTLx)(where x is endpoint number, x = 1...3) Address offset: 0xB00 + (endpoint number x 0x20) Reset value: 0x0000 0000 The application controls the operation of endpoints, except for endpoint 0. Reserved EPTYPE Reserved...
  • Page 657 AT32F415 Series Technical Manual Only valid to control endpoint (the operation type is rs.) The application can only set this bit, and the core will clear this bit when receiving SETUP command. Even the NAK bit, global IN NAK bit, or global OUT NAK bit are set at the same time, the STALL bit still has the highest priority.
  • Page 658 AT32F415 Series Technical Manual Reserved Reserved Bit 31:8 Reserved TXFE: Transmit FIFO empty When the corresponding TX FIFO of this endpoint is empty or half-empty, this Bit 7 interrupt is generated. The TX FIFO empty level bit in the core AHB configuration register (the OTG_FS_GAHBCFG register, TXFEMLVL bit) will determine whether to generate interrupt when TX FIFO is at empty or half-empty status.
  • Page 659 AT32F415 Series Technical Manual Reserved Bit 31:7 Reserved B2BSTUP: Back-to-back SETUP packets received Bit 6 It is valid only to OUT endpoint. It indicates that the endpoint receives over 3 consecutive SETUP packets. Bit 5 Reserved OTEPDIS: OUT token received when endpoint disabled It is valid only to OUT endpoint.
  • Page 660 AT32F415 Series Technical Manual Every time when the core reads a data packet (the maximum size data packet and short packet) from TX FIFO, this field is automatically decremented by 1. Bit 18:7 Reserved XFERSIZE: Transfer size It indicates the byte number to be transferred by the endpoint 0. Core will generate interrupt to inform the application when this field is 0.
  • Page 661 AT32F415 Series Technical Manual The application must configure this register before enabling the endpoint. Once the endpoint is enabled by the endpoint enable bit (the OTG_FS_DIEPCTLx Register, the EPENA Bit) of the device endpoint x control register, this register can only be modified by the core. Before the core clears the endpoint enable bit, the application can only read this register.
  • Page 662 AT32F415 Series Technical Manual 0x200: 512 words available Others: Reserved 21.14.48 OTG_FS Device Endpoint x Transfer Size Register (OTG_FS_DOEPTSIZx)(where x is endpoint number, x = 1...3) Address offset: 0xB10 + (endpoint number x 0x20) Reset value: 0x0000 0000 The application must configure this register before enabling the endpoint. Once the endpoint is enabled by the endpoint enable bit (the OTG_FS_DOEPCTLx Register, the EPENA Bit) of the device endpoint x control register, this register can only be modified by the core.
  • Page 663 AT32F415 Series Technical Manual Reserved Reserved Bit 31:5 Reserved PHYSUSP: PHY suspend Bit 4 It indicates that PHY is suspended. This bit is set when the application makes PHY enter the suspend state by configuring the STPPCLK bit (Bit 0). Bit 3:2 Reserved GATEHCLK: Gate HCLK...
  • Page 664 AT32F415 Series Technical Manual 21.15 OTG_FS Programming Model 21.15.1 Core Initialization The application should initialize core in sequence. At power-on state, USB is connected, and the current operation mode bit in the core interrupt register (the CURMOD bit in the OTG_FS_GINTSTS register) will indicate the current operation mode.
  • Page 665 AT32F415 Series Technical Manual ─ Device speed ─ Response status to non-zero-length OUT PACKET 2. Configure the OTG_FS_GINTMSK register to enable the following interrupts: ─ USB reset ─ Enumeration complete ─ USB early suspend ─ USB suspend ─ 3. In B-type device mode, configure the VBUSBSESEN bit in the OTG_FS_GCCFG register to enable VBUS and DP line pull-up 5 V.
  • Page 666 AT32F415 Series Technical Manual channels), the CHDIS bit can be written ’1’ in the OTG_FS_HCCHARx register and wait for the CHENA bit turning ‘0’ to clear transfer requests issued. The application needs to disable the channel under the following conditions: 1.
  • Page 667 AT32F415 Series Technical Manual Figure 21-12 TX FIFO W rite Task Read the GNPTXSTS/ start HPTXSIZ register to get available FIFO and queue space 1 MPS or Wait for the LPS FIFO space NPTXFEMP/PTXFEMP interrupt in the OTG_FS_GINTSTS available? Write 1 data message to the TX FIFO Transmit more data messages?
  • Page 668 AT32F415 Series Technical Manual Figure 21-13 RX FIFO Read Task Start RXFLVL interrupt? Mask RXFLVL Mask RXFLVL Disable mask RXFLVL interrupt interrupt interrupt Read received data message Read from RX FIFO OTG_FS_GRXSTSP PKTSTS 0b0010? 是 BCNT > 0? Bulk and control OUT/SETUP Figure 21-14 shows the typical bulk transaction or control transaction OUT/SETUP procedure.
  • Page 669 AT32F415 Series Technical Manual Figure 21-14 Normal Bulk/Control OUT/SETUP and IN Transaction Procedure Application Host Device init_reg(ch_1) Non-periodic request queue init_reg(ch_2) Assumed that this queue can take four requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) write_tx_fifo ch_2 (ch_1) set_ch_en ch_1 (ch_2) ch_2 DAT A0 set_ch_en...
  • Page 670 AT32F415 Series Technical Manual Transfer Done = 1 Unmask CHHLT Disable Channel else if (NAK or XACTERR) Rewind Buffer Pointers Unmask CHHLT Disable Channel if (XACTERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHHLT) mask CHHLT if (Transfer Done or (Eerror_count == 3)) De-allocate Channel else...
  • Page 671 AT32F415 Series Technical Manual Mask CHHLT if (Transfer Done or (Erro_Count == 3)) De-allocate Channel else Re-initialize channel else if (ACK) Reset Error Count Mask ACK else if (DTGERR) Reset Error Count The application should wait until XFERC event occurs to write request when request queue has space available.
  • Page 672 AT32F415 Series Technical Manual Figure 21-15 Bulk/Control IN Transaction Procedure Device Application Host init_reg(ch_1) Non-periodic request queue init_reg(ch_2) Assume that this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) write_tx_fifo ch_2 (ch_1) set_ch_en ch_1 (ch_2) ch_2 DAT A0 set_ch_en (ch_2) DAT A0...
  • Page 673 AT32F415 Series Technical Manual g) The application reads received data packet status; if it is not an IN data packet (which means the PKTSTS bit ≠0x0010 in the RXSTSR register), then ignore it. h) The core generates XFERC interrupt after the receive data packet status is read. i) During XFRC interrupt procedure, the OTG_FS_HCCHAR2 register should be set to disable channel and stop writing more requests.
  • Page 674 AT32F415 Series Technical Manual Figure 21-16 Normal Interrupt OUT/IN Transaction Procedure Application Host Device init_reg(ch_1) Periodic request queue init_reg(ch_2) Assumed that this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) ch_2 Odd (micro) frame DAT A0 XFERC interrupt init_reg(ch_1) write_tx_fifo (ch_1)
  • Page 675 AT32F415 Series Technical Manual Unmask CHHLT Disable Channel if (STALL) Transfer Done = 1 else if (NAK or XACTERR) Reset Buffer Pointer Reset Error Count Mask ACK Unmask CHHLT Disable Channel else if (CHHLT) Mask CHHLT if (Transfer Done or (Erro_Count == 3)) De-allocate Channel else Re-initialize Channel(in next b_interval - 1 Frame)
  • Page 676 AT32F415 Series Technical Manual if (STALL or BBLERR) Reset Error Count Transfer Done = 1 else if (!FRMOVR) Reset Error Count else if (XACTERR) Increment Error Count Unmask ACK Unmask CHHLT Disable Channel else if (CHHLT) Mask CHHLT if (Transfer Done or (Erro_Count == 3)) De-allocate Channel else Re-initialize channel (in next b_interval –...
  • Page 677 AT32F415 Series Technical Manual f) During RXFLVL interrupt procedure, the application reads received packet status to know the received byte number and read the corresponding RX FIFO. Before reading the RX FIFO, the RXFLVF interrupt should be masked, and enable the RXFLVL interrupt after complete packet is read. g) After the transfer complete status is stored into RX FIFO, the core will generate RXFLVL interrupt.
  • Page 678 AT32F415 Series Technical Manual Figure 21-17 Normal Isochronous OUT/IN Transaction Procedure Application Host Device init_reg(ch_1) Periodic request queue init_reg(ch_2) Assume this queue can take 4 requests write_tx_fifo (ch_1) set_ch_en ch_1 (ch_2) ch_2 Odd (micro) frame DAT A0 XFERC interrupt init_reg(ch_1) write_tx_fifo (ch_1) DAT A0...
  • Page 679 AT32F415 Series Technical Manual Unmask CHHLT Disable Channel else if(CHHLT) Mask CHHLT De-allocate Channel Code sample: Isochronous IN Unmask (XACTERR/XFERC/FRMOVR/BBLERR) if (XFERC or FRMOVR) if (XFERC and OTG_FS_HCTSIZx.PKTCNT == 0) Reset Error Count De-allocate Channel else Unmask CHHLT Disable Channel else if (XACTERR or BBLERR) Increment Error Count...
  • Page 680 AT32F415 Series Technical Manual MCNT bit in the OTG_FS_HCCHAR2 register before switching to other channels (to specify the maximum number of packets to be received at the next frame). c) Every time when the application configures the CHENA bit in the OTG_FS_HCCHAR2 register, the core writes an IN request to periodic request queue.
  • Page 681 AT32F415 Series Technical Manual ─ Set the INEPTINT 0 bit to ‘1’ in the OTG_FS_DAINTMSK register (control IN endpoint 0) ─ Set the OUTEPTINT 0 bit to ‘1’ in the OTG_FS_DAINTMSK register (control OUT endpoint 0) ─ Set the SETUP bit to ‘1’ in the DOEPMSK register ─...
  • Page 682 AT32F415 Series Technical Manual 1. Configure the following bits in the OTG_FS_DIEPCTLx register (for IN or bi-directional endpoint) or OTG_FS_DOEPCTLx register (for OUT or bidirectional endpoint): ─ Maximum size ─ USB effective endpoint bit = ’1’ ─ Endpoint start data toggle number (for interrupt and bulk transfer type endpoints) ─...
  • Page 683 AT32F415 Series Technical Manual 6. Every time a RXFLVL (OTG_FS_GINTSTS) interrupt is detected, the above five steps should be repeated. Reading an empty RX FIFO will cause undefined consequence. Figure 21-18 shows the flow of the above procedures: Figure 21-18 Reading RX FIFO Data Message in Slave M ode: Waiting for the RXFLVL in the OTG_FS_GINTSTSG rd_data = rd_reg (OTG_FS_GRXSTSP)
  • Page 684 AT32F415 Series Technical Manual 4. The application needs to read a DWORD of SETUP phase complete message in RX FIFO. ● Internal data flow 5. When receiving SETUP packet, the core will store the received data into RX FIFO; at this time, it will not detect whether RX FIFO has remaining space, neither detect the NAK or STALL bit status of the endpoint.
  • Page 685 AT32F415 Series Technical Manual Figure 21-19 Processing a SETUP Data Message Wait for STUP in OTG_FS_DOEPINTx rem_supcnt = rd_reg(DOEPTSIZx) setup_cmd[31:0] = mem[4-2* rem_supcnt] setup_cmd[63:32] = mem[5-2* rem_supcnt] Look for Setup Command read write type ctrl-rd/wr/2 phase 2-阶段 setup_np_in_pkt setup_np_in_pkt rcv_out_pkt data IN phase Status IN phase data OUT phase...
  • Page 686 AT32F415 Series Technical Manual ─ GINNAKEFFM = 0 in the GINTMSK register 5. Once it is required to exit global OUT NAK mode,the SGOUTNAK bit in the OTG_FS_DCTL register can be cleared. This operation will clear the GOUTNAKEFF (OTG_FS_GINTSTS) interrupt. ─...
  • Page 687 AT32F415 Series Technical Manual PID number; under this condition, the packet number bit in the register will not be automatically decreased. ─ If RX FIFO does not have space available, isochronous or non-isochronous data packet will be dropped and not written into RX FIFO. In addition, for non-isochronous OUT data packet, NAK handshake signal will be transmitted.
  • Page 688 AT32F415 Series Technical Manual ─ EONUM (the OTG_FS_DOEPCTLx Register) = SOFFN[0](the OTG_FS_DSTS Register) 3. After reading complete isochronous OUT data packet (including data and status) from the RX FIFO, the core will update the RXDPID bit in the OTG_FS_DOEPTSIZx register based on the last read isochronous OUT data packet in the RX FIFO.
  • Page 689 AT32F415 Series Technical Manual ─ After the application reads and empties the RX FIFO, it generates XFERC interrupt (OTG_FS_DOEPINTx); at this time, endpoint needs to be re-enabled to receive isochronous OUT data in the next frame. 3. When detecting INCOMISOOUTM interrupt (OTG_FS_GINTSTS), all isochronous OUT endpoint control register (OTG_FS_DOEPCTLx) should be read to check which endpoint has incomplete transfer in the current frame.
  • Page 690 AT32F415 Series Technical Manual Figure 21-20 Bulk OUT Transaction Host Device Application init_out_ep XFERSIZE = 512 bytes PKTCNT = 1 wr_reg(DOEPTSIZx) XFERSIZE = 512 bytes PKTCNT = 1 wr_reg(DOEPTCTLx) 512 bytes xact_1 RXFLVL interrupt Idle until interrupt rcv_out_pkt() XFERSIZE = 0 New transfer or Rx FIFO Not empty...
  • Page 691 AT32F415 Series Technical Manual FIFO. Usually, except for configuring endpoint enable bit, the application must configure the OTG_FS_DIEPCTLx register by read-modify-write operation to prevent register content from being changed. If TX FIFO has sufficient space available, it is allowed to write several data packets to the same endpoint consecutively.
  • Page 692 AT32F415 Series Technical Manual 6. The application must read periodic IN endpoint OTG_FS_DIEPTSIZx register to know how much data the endpoint has transmitted to USB. 7. The application needs to configure the following bits in the OTG_FS_GRSTCTL register to clear data in the endpoint TX FIFO: ─...
  • Page 693 AT32F415 Series Technical Manual 4. After data is written into TX FIFO, the core reads the data after receiving IN token. For every non-isochronous IN data packet transfer ended with ACK, the endpoint packet number register will be automatically decreased by 1, until the packet number turns to 0. The packet number register will be automatically decreased because of timeout.
  • Page 694 AT32F415 Series Technical Manual 3. All data that should be transmitted within a frame must be written into TX FIFO before receiving IN token. For data that should be transmitted within a frame, even if there is only one DWORD not written to TX FIFO, the core will still regard FIFO as empty.
  • Page 695 AT32F415 Series Technical Manual ● Incomplete isochronous IN data transaction This section describes how the application process internal data when there is incomplete isochronous IN transfer: 1. When any of the following condition occurs, it is regarded as isochronous IN transfer incomplete: ─...
  • Page 696 AT32F415 Series Technical Manual 6. When application sets or clears the STALL bit based on SetFeature.Endpoint Halt command or ClearFeature.Endpoint Halt command, configuration to the STALL bit must be done before status transfer phase is established at the control endpoint. Special case: To stall a control OUT endpoint When the number of IN/OUT tokens transmitted by the core at host is over the number defined by SETUP packet, IN/OUT token can be stalled at control data transaction phase.
  • Page 697 AT32F415 Series Technical Manual TRDTIM under Maximum Time Sequence Figure 21-21 50ns 100ns 150ns 200ns HCLK PCLK tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 clock cycles 2020.06.28 Page 697 Version 1.02...
  • Page 698 AT32F415 Series Technical Manual 22 Revision History Document Revision History Date Version Revision Note 2018.08.12 1.00 Original version 1.Updated front page function descriptions 2018.08.23 1.01 2.Updated Figure 19-14 3.Corrected typos 1. Added the description of PLL configuration mode in 3.2.3 section 2020.6.28 1.02 2 .Updated the description of RCC_PLL register in 3.2.12 section.
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