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ARTERY AT32F415 Getting Started

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Introduction
This application note is written to help users with rapid project development using AT32F415xx.
Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by
Artery. For other versions of BSP, please pay attention to the differences in usage.
Applicable products:
Part number
2022.10.21
Getting Started with AT32F415
Getting Started with AT32F415
AT32F415xx
1
AN0022
Application Note
Ver 2.0.3

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Summary of Contents for ARTERY AT32F415

  • Page 1 This application note is written to help users with rapid project development using AT32F415xx. Note: The corresponding code in this application note is developed on the basis of V2.x.x BSP provided by Artery. For other versions of BSP, please pay attention to the differences in usage. Applicable products:...

  • Page 2: Table Of Contents

    1.1.2 Programming tools and software................6 1.1.3 AT32 development environment................7 1.1.4 How to replace SXX ....................12 AT32F415 chip enhanced functions ................13 1.2.1 Prefetch buffer ....................... 13 1.2.2 PLL clock settings ....................14 1.2.3 Encryption mode ....................16 1.2.4...
  • Page 3 Getting Started with AT32F415 List of tables Table 1. Document revision history ....................29 2022.10.21 Ver 2.0.3...
  • Page 4 Figure 16. Wait states of Flash performance select register (FLASH_PSR) ........13 Figure 17. System clock configuration function “system_clock_config”.......... 13 Figure 18. AT32F415 150 MHz PLL clock configuration ..............14 Figure 19. SXX PLL auto step-by-step switch configurations............15 Figure 20. AT32 PLL auto step-by-step switch configurations............15 Figure 21.
  • Page 5 Getting Started with AT32F415 Figure 34. Operate ConfigJLink_V1.0.0 in KEIL ................26 Figure 35. ConfigJLink_V1.0.0 execution progress in KEIL ............26 Figure 36. Operate ConfigJLink_V1.0.0 in IAR................27 Figure 37. ConfigJLink_V1.0.0 execution progress in IAR ............. 27 2022.10.21 Ver 2.0.3...

  • Page 6: Preliminary Environment Requirements

    Build AT32 development environment 1.1.1 Debug tools and evaluation board The AT32F415 evaluation board has an AT-Link-EZ debug tool, as shown in the red box in Figure 1 below. The AT-Link-EZ can be disassembled and used with other circuit boards, supporting IDE online debugging, online programming and USB-to-serial port.

  • Page 7: At32 Development Environment

    Getting Started with AT32F415 EZ, ICP/ISP.  party programming tools: J-Link, Armfly, Alientek, XWOPEN, ICWORKSHOP, ZLG, MaxWiz, Amomcu, Acroview, Forcreat, Galecomm, Prosystems, Rx-prog, Sinaen, XELTEK, Zhifeng, etc. ARTERY’s official website→SUPPORT→Hardware Development Note: For more information, please visit Tool and 3 Party Writer.

  • Page 8: Figure 5. Keil_V5 Templates

    (ApNote) of the template project. Except for templates, BSP also includes code examples (Keil_v5 project files) in terms of peripherals for reference (AT32F415_Firmware_Library_V2.x.x\project\at_start_f4xx\examples). Note: For more details about BSP, please refer to “Section 4 BSP application” of AT32F415 Firmware ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download BSP&Pack User Guide.

  • Page 9: Figure 6. Pack Download

    If the path is not recognize d or incorrect, you need to manually select the Keil installation path. Figure 7. Set up ArteryTek.AT32F415 _DFP Figure 8. Set up Keil4_AT32MCU_AddOn You can also open keil and click on “Pack Installer” icon; then click on the top left “file” and select “import”...

  • Page 10: Figure 9. Pack Installer Icon In Keil

    If the path is not recognized or incorrect, you need to manually select the IAR installation path. Figure 10. Set up IAR_AT32MCU_AddOn Note: For more details about Pack setup, please refer to “Section 2 Pack setup” of AT32F415 Firmware ARTERY’s official website→PRODUCTS→Value line→AT32F4xx; download BSP&Pack User Guide.

  • Page 11: Figure 11. Keil Debug Option

    Getting Started with AT32F415 Figure 11. Keil Debug option Go to Debug and click on Settings to enter the Cortex-M Target Driver Setup interface. Select AT-Link(WinUSB)-CMSIS-DAP/AT-Link-CMSIS-DAP; Note: For details about WinUSB, please refer to FAQ0136_How to use AT-LINK WinUSB to improve download (ARTERY’s official...

  • Page 12: How To Replace Sxx

    Note: For details about Flash algorithm file, MCU switch and solutions for “J -Link cannot find MCU”, please ARTERY’s official website→PRODUCTS→Value refer to AT32F415 Firmware BSP&Pack User Guide. Path: line→AT32F4xx; download and unzip BSP, and get the “\AT32F415_Firmware_Library_Vx.x.x\document”. 1.1.4 How to replace SXX  Please refer to MG0005_ Migrating from SXX32F0xx&GX32F3x0 to AT32F415 (ARTERY’s 2022.10.21 Ver 2.0.3...

  • Page 13: At32F415 Chip Enhanced Functions

    If the program still cannot run properly after completing the above steps, please refer to other sections of this application note or contact the agent and ARTERY technicians for help. Note: Compared with SXX32F0xx, AT32F415 is more flexible to achieve better performance. Please refer to (ARTERY’s official website→SUPPORT→AP Note→AN0004) to learn...

  • Page 14: Pll Clock Settings

    When the SXX32F0xx BSP is used, the PLL setting example (HEXT=8 MHz, PLL=48 MHz): RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL 6); If the user wants to use SXX32F0xx program to output a clock greater than 48 MHz on AT32F415, it is necessary to configure the CRM_CFG register (corresponds to the RCC_CFGR register of SXX32).

  • Page 15: Figure 19. Sxx Pll Auto Step-By-Step Switch Configurations

    Getting Started with AT32F415 1.2.2.2 Auto step-by-step switch When the internal PLL of AT32F415 is set to 108 MHz and above, it is necessary to perform auto step-by-step switch. When the SXX32F0xx BSP is used, the user needs to open system_sxx32f0xx.c and find out the current system clock configuration function (go through Section 1.2.2.1 PLL settings), and add the...

  • Page 16: Encryption Mode

    The ICP/ISP tool can be used to enable and disable IC access protection, as shown below:  Artery ICP Programmer (BOOT0=0, BOOT1=0) Enable access protection: Open Artery ICP Programmer—Access protection—Enable high- level access protection. Disable access protection: Open Artery ICP Programmer—Access protection—Disable.

  • Page 17: Figure 22. Enable Access Protection In Isp Programmer

    Getting Started with AT32F415 Figure 22. Enable access protection in ISP Programmer Figure 23. Disable access protection in ISP Programmer  Artery ISP Multi-Port Programmer (BOOT0=1, BOOT1=0) Enable access protection: Protection/Enable/High-level access protection—Start, encrypted; Disable access protection: Protection/Disable/Access protection—Start, Flash decrypted.

  • Page 18: Figure 24. Enable Erase And Program Protection In Icp Programmer

     Artery ICP Programmer (BOOT0=0, BOOT1=0) Enable erase and program protection: Open Artery ICP Programmer —User system data—Tick the sectors that require erase and program protection—Apply to device. Disable erase and program protection: Open Artery ICP Programmer—User system data—...

  • Page 19: Set Boot Memory As Main Flash Memory Extension Area

    1.2.4 Set boot memory as main Flash memory extension area By default, boot memory stores the original boot codes in BOOT mode. For AT32F415 series MCUs, the boot memory also can be used as the main Flash memory extension area (AP mode) to store user-defined codes.

  • Page 20: Figure 26. Set Ap Mode In Icp Programmer

    “Flash info” interface will display a success or failure message. Figure 27. AP mode enabling in ICP Programmer The user can use Artery ICP Programmer to set the boot memory as the main Flash memory extension area (in mass production) as follows: ...

  • Page 21: Figure 28. Offline Config Settings In Icp Programmer

    Getting Started with AT32F415  Open Artery ICP programmer and select AT-Link to connect;  AT-Link Setting—AT-Link offline config settings;  Generate an offline project as follows: Click on “Create”; Enter project name; Select MCU part number; Add .hex file Select SWD as the download interface;...

  • Page 22: Recognize At32 Mcu In Program

    Getting Started with AT32F415 Figure 29. AT-Link project file settings  If the project is saved to AT-Link successfully, in the offline download status interface (as shown in Figure 25), select offline download item—Save and activate, to start download. Figure 30. AT-Link offline download status ...

  • Page 23: Figure 31. Read Cortex Id

    Figure 32. Read PID and UID /* Get the base address of AT32 MCU PID/UID */ #define DEVICE_ID_ADDR1 0x1FFFF7F3 // Define Artery MCU part number, UID base address #define DEVICE_ID_ADDR2 0xE0042000 // Define MCU device number, PID base address /* Used to store ID */ uint8_t ID[5] = {0};...

  • Page 24: Faqs In Downloading/Compiling

    Please refer to FAQ0008_ J-Link cannot find IC SUPPORT→FAQ→FAQ0008). (ARTERY’s official website→  Please refer to FAQ0132_Add Artery MCU to J-Link SUPPORT→FAQ→FAQ0132). Problems in program downloading 2.3.1 Error: Flash Download failed–“Cortex-M4” The following pop-up window appears in KEIL emulation or downloading: Figure 33.

  • Page 25: No Debug Unit Device Found

     Replace with better USB-to-serial port tools, i.e., CH340 chip. 2.3.5 Resume download When using AT32F415, the user may not be able to download the program again in the following conditions:  After disabling JTAG/SWD PIN in the program, the program cannot be downloaded and JTAG/SWD device is not found.

  • Page 26: Figure 34. Operate Configjlink_V1.0.0 In Keil

    Note 3: If the MCU enters Standby mode every time the program is downloaded, perform the preceding steps before the chip is powered on. Note 4: In Keil, after AT32F415 MCU enters Standby mode, the solution using ConfigureJLink.exe is invalid.

  • Page 27: Figure 36. Operate Configjlink_V1.0.0 In Iar

    Getting Started with AT32F415 Figure 36. Operate ConfigJLink_V1.0.0 in IAR Figure 37. ConfigJLink_V1.0.0 execution progress in IAR Note 1: Make sure that SEGGER J-Link interface DLL is not lower than V6.14. Note 2: If JTAG/SWD PIN is disabled every time the program is downloaded, perform the preceding steps before downloading the program.

  • Page 28: Security Library (Slib)

    IP-Codes (such as core algorithms) developed by software solution providers. The AT32F415 series is designed with a security library (sLib) to protect important IP-Codes against being changed or read by the end user’s program.

  • Page 29: Revision History

    Getting Started with AT32F415 Revision history Table 1. Document revision history Date Version Revision note 2021.12.20 2.0.0 Initial release. 2022.08.04 2.0.1 Updated 3rd party programming tools. 2022.10.10 2.0.2 Added description of development environment and file path. 2022.10.21 2.0.3 Optimized description of UID and PID.
  • Page 30 No license, express or implied, to any intellectual property right is granted by ARTERY herein regardless of the existence of any previous representation in any forms. If any part of this document involves third party’s products or services, it does NOT imply that ARTERY authorizes the use of the third party’s products or services, or permits any of the intellectual property, or guarantees any uses of the third...

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