Agp Timing Settings; Pci Timing Settings - JETWAY 867ASR2A User Manual

If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.

3-6-2 AGP Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
AGP Transfer Aperture Size
AGP Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
AGP Master 1 WS Write
AGP Master 1 WS Read
CPU to AGP Post Write
AGP Delay Transaction
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
¡ ü ¡ ý ¡ ú ¡ û
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.

3-6-3 PCI Timing Settings

CMOS Setup Utility – Copyright(C) 1984-2001 Award Software
PCI Master 1 WS Write
PCI Master 1 WS Read
CPU to AGP Post Write
PCI Delay Transaction
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
¡ ü ¡ ý ¡ ú ¡ û
F5:Previous Values
AGP Timing Settings
128M
Auto
Auto
DA
Disabled
Enabled
Enabled
Disabled
Disabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
Disabled
Disabled
F6:Optimized Defaults
28
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults