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查询CDB42528供应商
查询CDB42528供应商
114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
Features
Eight 24-bit D/A, two 24-bit A/D Converters
114 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
S/PDIF Receiver Compatible with EIAJ CP1201
and IEC-60958
Recovered S/PDIF Clock or System Clock
Selection
8:2 S/PDIF Input MUX
ADC High-pass Filter for DC Offset Calibration
Expandable ADC Channels and One-line Mode
Support
Digital Output Volume Control with Soft Ramp
Digital +/-15dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports logic levels between 5 V and 1.8 V.
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
TXP
VARX
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
Rx
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
GPO
M UTEC
M UTE
FILT+
VQ
Ref
REFGND
VA
AGND
AINL+
ADC#1
AINL-
AINR+
ADC#2
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
General Description
The CS42528 codec provides two analog-to-digital and eight
digital-to-analog delta-sigma converters, as well as an integrat-
ed S/PDIF receiver, in a 64-pin LQFP package.
The CS42528 integrated S/PDIF receiver supports up to eight
inputs, clock recovery circuitry and format auto-detection. The
internal stereo ADC is capable of independent channel gain
control for single-ended or differential analog inputs. All eight
channels of DAC provide digital volume control and differential
analog outputs. The general purpose outputs may be driven
high or low, or mapped to a variety of DAC mute controls or
ADC overflow indicators.
The CS42528 is ideal for audio systems requiring wide dynam-
ic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42528-CQZ
CS42528-DQZ
CDB42528
AGND
LPFLT
DGND VD
DGND
C&U Bit
Data Buffer
S/PDIF
Clock/Data
Decoder
Recovery
Form at
Detector
Internal M CLK
DEM
Digital Filter
Gain & Clip
ADC
Serial
Data
Digital Filter
Gain & Clip
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
(All Rights Reserved)
CS42528
-10° to 70° C 64-pin LQFP
-40° to 85° C 64-pin LQFP
Evaluation Board
VD
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OM CK
M ult/Div
RM CK
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CODEC
Serial
CX_SDIN4
Port
Lead Free
Lead Free
JAN '05
DS586PP5
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Table of Contents
Related Manuals for Cirrus Logic CS42528-CQZ
Summarization of Contents
Applications
Analog Inputs
Details the line-level differential analog inputs and biasing requirements.
Analog Outputs
Covers on-chip buffer amplifiers for line-level outputs and filter considerations.
S/PDIF Receiver
Explains the S/PDIF receiver's capabilities, error handling, and data formats.
Clock Generation
PLL and Jitter Attenuation
Discusses the on-chip PLL for clock recovery and its jitter attenuation characteristics.
Digital Interfaces
Serial Audio Interface Formats
Details the supported serial audio data formats like I2S, Left/Right Justified, and One Line modes.
Control Port Description and Timing
I2C Mode
Details the I2C mode operation for the control port, including timing and pseudocode.
Register Description
Power Control
Manages device power states, including receiver, ADC, DAC, and overall power down.
Functional Mode
Selects operating modes like Single, Double, or Quad Speed for converters.
Interrupt Status
Reports the status of various interrupt conditions like PLL unlock and ADC overflow.
Appendix A: External Filters
ADC Input Filter
Recommends analog input buffer circuit to filter ADC signals and provide impedance matching.
Appendix B: S/PDIF Receiver
Error Reporting and Hold Function
Explains error reporting mechanisms and how audio samples are held on error.
Channel Status Data Handling
Details handling of channel status data, including professional/consumer bits and de-emphasis.
Appendix C: PLL Filter
External Filter Components
Lists recommended external components for the PLL filter and their impact on performance.
Appendix D: External AES3/SPDIF/IEC60958 Receiver Components
AES3 Receiver External Components
Details external components for consumer-standard AES3/S/PDIF receiver interfaces.
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