Asus AP1720-I5 User Manual page 54

Prl-dl m/b user guide
Table of Contents

Advertisement

2. Disabled CPU cache.
3. Check if go to BOOTBLOCK POST.
POST Code < 05h >
1. Blank out the video screen.
2. Initialized the keyboard.
POST Code < 07h >
1. Used walking 1's algorithm to check out interface to CMOS circuitry.
2. Also set real-time clock power status. Then check for override.
POST Code < 09h >
1. Programed chipset register to default value according to ROMTABLE.
2. early initialize CPU.
3. Initialized APIC.
4. Set A20 off.
POST Code < 0Ah >
1. Initialized int. vectors (0-77h) to the spurious interrupt handler. Then
initialize 00h-1fh to their proper places.
POST Code < 0Bh >
1. Checked normal ISA CMOS checksum and battery. If it fails, we load the
manufacturing defaults.
2. Chipset very early PM initialization, change SMBASE for CPU and move
SMM code.
3. PMM initialization.
4. Disable all memory caching then enable E800 and F000 segement
caching.
5. PnP early initialization.
6. BBS initialization.
POST Code < 0Ch >
1. Initialize the keyboard controller and set up all of the 40: area data.
2. Load CPU micro-code update if BIOS updated option is enable.
2-28
Chapter 2: Hardware information

Advertisement

Table of Contents
loading

This manual is also suitable for:

Prl-dl

Table of Contents