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Caen Manuals
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DT5730
User manual
Caen DT5730 User Manual
8-channel 14-bit 500/250 ms/s digitizer
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Contents
Table of Contents
Bookmarks
Table of Contents
Purpose of this Manual
Change Document Record
Symbols, Abbreviated Terms and Notation
Reference Documents
Index
Table of Contents
List of Figures
List of Tables
1 Introduction
Tab. 1.1: Table of Models and Related Items
2 Block Diagram
Fig. 2.1: Block Diagram
3 Technical Specifications
Tab. 3.1: Specifications Table
4 Packaging and Compliancy
Fig. 4.1: Front View
5 Power Requirements
Fig. 5.1: AC/DC Power Supply Provided with the Module
6 Cooling Management
7 Temperature Protection
8 Panels Description
Fig. 8.1: Front Panel View
Fig. 8.2: Rear Panel View
Front Panel
Rear Panel
9 Functional Description
Analog Input Stage
Fig. 9.1: Analog Input Diagram
Clock Distribution
Fig. 9.2: Clock Distribution Diagram
PLL Mode
Changing the ADC Frequency
Trigger Clock
Acquisition Modes
Channel Calibration
Fig. 9.3: Typical Channel before the Calibration (a and B) and after the Calibration (C)
Fig. 9.4: Automatic Calibration at Wavedump First Run
Fig. 9.5: Temperature Monitoring with Manual Calibration in Wavedump Software
Fig. 9.6: Channel Calibration in DPP-PSD Control Software
Fig. 9.7: Channel Calibration in MC
Acquisition Run/Stop
Acquisition Triggering: Samples & Events
Fig. 9.8: Trigger Overlap
Multi-Event Memory Organization
Custom Sized Events
Tab. 9.1: Buffer Organization
Event Structure
Tab. 9.2: TRG OPTIONS Configuration Table
Event Format Example
Tab. 9.3: Event Format Example
Acquisition Synchronization
Trigger Management
Software Trigger
External Trigger
Fig. 9.9: Block Diagram of the Trigger Management
Self-Trigger
Fig. 9.10: Self Trigger and Trigger Request Logic for Ch0 and Ch1 Couple. a Single Trigger Request Signal Is Generated
Fig. 9.11: Channel Over/Under Threshold Signal
Fig. 9.12: Channel Pulse Signal
Trigger Coincidence Level
Fig. 9.13: Trigger Request Management at Mezzanine Level with Majority Level = 0
Fig. 9.14: Trigger Request Management at Motherboard Level with Majority Level = 0
Fig. 9.15: Trigger Request Relationship with Majority Level = 1 and T
Trigger Distribution
Fig. 9.17: Trigger Configuration on GPO Front Panel Output Connector
Example
Reset, Clear and Default Configuration
Global Reset
Memory Reset
Timer Reset
Data Transfer Capabilities
Block Transfers
Single Data Transfer
Optical Link and USB Access
10 Drivers & Libraries
Drivers
Libraries
Fig. 10.1: Required Libraries and Drivers
11 Software Tools
Fig. 11.1: Caenupgrader Graphical User Interface
Caencomm Demo
Fig. 11.2: Caencomm Demo Java and Labview Graphical Interface
CAEN Wavedump
Fig. 11.3: CAEN Wavedump
Fig. 11.4: Caenscope Main Frame
Caenscope
DPP-PSD Control Software
Fig. 11.5: DPP-PSD Control Software: Top - DPP Settings Tab and Typical 60 Co Total Charge Spectrum; Bottom - PSD 2-D Scatter Plot
Fig. 11.6: MC²Analyzer (MC²A) Software Tool
12 HW Installation
Power-On Sequence
Power-On Status
Fig. 12.1: Front Panel Leds Status at Power on
13 Firmware and Upgrades
Default Firmware Upgrade
Upgrade Files Description
DPP Firmware Upgrade
Upgrade File Description
14 Technical Support
Returns and Repairs
Technical Support Service
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CAEN
n
Electronic Instrumentation
Tools for Discovery
User Manual UM3148
DT5730/DT5725
8-Channel 14-bit 500/250 MS/s Digitizer
Rev. 2 - 10 June 2016
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