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Summary of Contents for Caen V1724 Series
- Page 1 Technical Information Manual Revision n. 7 6 November 2007 MOD. V1724 8 CHANNEL 14 BIT 100 MS/S DIGITIZER MANUAL REV.7 NPO: 00103/05:V1724x.MUTx/07...
- Page 2 User. It is strongly recommended to read thoroughly the CAEN User's Manual before any kind of operation. CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice. Disposal of the Product The product must never be dumped in the Municipal Waste.
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Page 3: Table Of Contents
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 TABLE OF CONTENTS GENERAL DESCRIPTION.........................8 1.1..............................8 VERVIEW 1.2............................9 LOCK IAGRAM TECHNICAL SPECIFICATIONS ......................10 2.1.............................10 ACKAGING 2.2...........................10 OWER REQUIREMENTS 2.3. - Page 4 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.4..........................25 ERO SUPPRESSION 3.4.1. Zero Suppression Algorithm ......................25 3.4.1.1. Full Suppression based on the integral of the signal.................. 25 3.4.1.2. Full Suppression based on the amplitude of the signal................25 3.4.1.3.
- Page 5 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.13.8. CAENVME_FIFOBLTReadCycle....................44 3.13.9. CAENVME_MBLTReadCycle .......................44 3.13.10. CAENVME_FIFOMBLTReadCycle ..................44 3.13.11. CAENVME_IRQCheck ......................45 3.13.12. CAENVME_IRQEnable......................45 3.13.13. CAENVME_IRQDisable......................45 3.13.14. CAENVME_IRQWait.........................46 VME INTERFACE .............................47 4.1........................47 EGISTERS ADDRESS MAP 4.2.
- Page 6 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4.31. 8140; ) ........................57 OARD 4.32. 8144; )......................57 ONITOR 4.33. 814C; )........................57 VENT 4.34. 8150; ).....................57 NALOG ONITOR 4.35. VME C EF00; ) ......................58 ONTROL 4.36.
- Page 7 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 . 3.9: E ..........27 XAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING LFWD . 3.10: E ..........27 XAMPLE WITH NEGATIVE LOGIC AND NON OVERLAPPING LFWD .
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Page 8: General Description
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 1. General description 1.1. Overview The Mod. V1724 is a 1-unit wide VME 6U module housing a 8 Channel 14 bit 100 MS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities. -
Page 9: Block Diagram
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Single Data Transfer (D32), 32/64 bit Block Transfer (BLT/MBLT), 2eVME, 2eSST and 32/64 bit Chained Block Transfer (CBLT). The board houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight V1724 (64 ADC channels) to a single Optical Link Controller (Mod. -
Page 10: Technical Specifications
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 2. Technical specifications 2.1. Packaging The module is housed in a 6U-high, 1U-wide VME unit. The board hosts the VME P1, and P2 connectors and fits into both VME/VME64 standard and V430 backplanes. VX1724 versions require VME64X compliant crates. -
Page 11: Front Panel
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 2.3. Front Panel Mod. V560E Mod. V1724 EXTERNAL CLOCK IN INTERNAL CLOCK OUT LOCAL TRIGGER OUT EXTERNAL TRIGGER IN SYNC/SAMPLE START ANALOG INPUT ANALOG MONITOR... -
Page 12: External Connectors
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 2.4. External connectors 2.4.1. ANALOG INPUT connectors Single ended version (see options in § 1.1): Function: Analog input, single ended, input dynamics: 2.25Vpp Zin=50Ω (on request: 10Vpp Zin=1KΩ) Mechanical specifications: MCX connector (CS 85MCX-50-0-16 SUHNER) -
Page 13: Digital I/O Connectors
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 2.4.4. Digital I/O connectors Function: N.16 programmable differential LVDS I/O signals, Zdiff_in= 110 Ohm. Four Indipendent signal group 0÷3, 4÷7, 8÷11, 12÷15, In / Out direction control; see also § 3.6. Mechanical specifications: 3M-7634-5002- 34 pin Header Connector 2.4.5. -
Page 14: Fig . 2.3: Rotary And Dip Switches Location
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 y y y y CLK SOURCE: SW1 BASE ADDRESS [31:16] ROTARY SWITCHES SW2..5 FW JUMPER: JP2 Fig. 2.3: Rotary and dip switches location NPO: Filename: Number of pages:... -
Page 15: Technical Specifications Table
Frequency from 10 to 100MHz. AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM / TTL is CLK_IN also possible via custom CAEN cable). DC coupled differential LVDS output clock, locked to ADC sampling clock. Frequency values in 10 CLK_OUT ÷... -
Page 16: Functional Description
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3. Functional description 3.1. Analog Input The module is available either with single ended (on MCX connector) or, on request, differential (on Tyco MODU II 3-pin connector) input channels. 3.1.1. -
Page 17: Clock Distribution
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.2. Clock Distribution Fig. 3.3: Clock distribution diagram The module clock distribution takes place on two domains: OSC-CLK and REF-CLK; the former is a fixed 50MHz clock provided by an on board oscillator, the latter provides the ADC sampling clock. -
Page 18: Pll Mode
CAENPLLConfig is available at: http://www.caen.it/nuclear/lista-sw.php?mod=V1724 And must be simply run on the PC connected to the used CAEN VME Controller The User has to select the board type and base address (in the ADC BOARD field), then the used mode (PLL or Direct Feed/BYPASS in the INPUT field); see figure below:... -
Page 19: Pll Programming
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Fig. 3.4: CAENPLLConfig Main menu 3.2.6. PLL programming In PLL mode the User has to enter the divider for input clock frequency (input clock divider field in CAENPLLConfig Main menu);... -
Page 20: Multiboard Synchronisation
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.2.9. Multiboard synchronisation More boards can work synchronously, using an external clock source. Synchronisation can be achieved either by daisy chaining the boards or by using a fan out unit as clock distributor. -
Page 21: Gate And Sample Mode Acquisition
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Subsequentially acquisition is stopped either: − resetting the RUN/STOP bit (bit[2]) in the Acquisition Control register (bits [1:0] of Acquisition Control must be set to REGISTER-CONTROLLED RUN MODE or S-IN CONTROLLED RUN MODE) −... -
Page 22: Sample Mode
P R E L I M I N A R Y Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.3.3. Sample mode In Sample mode only the first value sampled after the S-IN signal leading edge is stored; ;... -
Page 23: Custom Size Events
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 An event is therefore composed by the trigger time tag, pre- and post-trigger samples and the event counter. Overlap between “acquisition windows” may occur (a new trigger occurs while the board is still storing the samples related to the previous trigger);... -
Page 24: Event Structure
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 = 0 means “default size events”, i.e. the number of memory locations is the maximum allowed. = N1, with the constraint 0<N1<½NS, means that one event will be made of 2⋅N1 samples. -
Page 25: Memory Full Management
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.3.6. Memory FULL management Bit5 of Acquisition Control register (see § 4.17), allows to select Memory FULL management mode: In Normal Mode the board becomes full, whenever all buffers are full (see § 4.15); otherwise (“Always one buffer free”... -
Page 26: Fig . 3.8: Zero Suppression Example
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 With Zero length encoding it is also possible to set N (LOOK BACK), the number of data to be stored before the signal crosses the threshold and/or, N (LOOK LFWD FORWARD), the number of data to be stored after the signal crosses the threshold (see... - Page 27 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Fig. 3.9: Example with positive logic and non-overlapping N LFWD then the readout event is: + N' + 5 (control words) + 1 (size) Skip N Good N' LFWD...
- Page 28 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 then the readout event is: + N' + N' + 5 (control words) + 1 (size) Good N' LFWD ... N' words with samples under threshold Skip N LFWD Good N'...
- Page 29 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Skip N LFWD Good N ... N words with samples over threshold 3) If the algorithm works in positive logic, and = 0 ; ≤...
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Page 30: Trigger Management
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 + N' + 4 (control words) + 1 (size) Skip N Good N' LFWD ... N' words with samples over threshold Good N' = (N ) + N LFWD... -
Page 31: Local Channel Auto-Trigger
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.5.3. Local channel auto-trigger Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold (ramping up or down, depending on VME settings), and remains under or over threshold for Nth “quartets”... -
Page 32: Analog Monitor
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Table 3.3 : Front Panel I/Os default setting Direction Description Ch 0 Trigger Request Ch 1 Trigger Request Ch 2 Trigger Request Ch 3 Trigger Request Ch 4 Trigger Request Ch 5 Trigger Request... -
Page 33: Test Mode (Monitor Mode = 1)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Nth [4samples] Nth [4samples] THRESHOLD CH0 IN Nth [4samples] Nth [4samples] THRESHOLD CH1 IN 2.5mV 1.25mV MAJORITY Fig. 3.15: Majority logic (2 channels over threshold; bit[6] of Ch. Config. Register =0) In this mode the MON output provides a signal whose amplitude is proportional to the number of channels over the trigger threshold. -
Page 34: Procedure To Enable "Analog Monitor" Mode
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Data converted by channel ADC are brought to the FPGA via a 2 bit BUS. Data transfer timing is provided by TRG-CLK; the available bandwidth is 200 Mb/s. The FPGA ROC handles 8 bit data. -
Page 35: Buffer Occupancy Mode (Monitor Mode = 3)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Channel sum with maximum dynamics: Fig. 3.18: Example of Magnify and Offset parameters use on single channel The assumption is an input signal on CH0 using th whole dynamics and all channels participating to Analog Monitor. -
Page 36: Test Pattern Generator
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.8. Test pattern generator The FPGA AMC can emulate the ADC and write into memory a ramp (0, 1, 2, 3,…3FFF, 3FFF, 3FFE.., 0) for test purposes. It can be enabled via Channel Configuration register, see §... -
Page 37: Cr/Csr Address
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 16 15 OFFSET Fig. 3.19: A24 addressing 0x00000000 0xFFFF0000 A32 mode 16 15 OFFSET Fig. 3.20: A32 addressing The Base Address of the module is selected through four rotary switches (see § 2.6), then it is validated only with either a Power ON cycle or a System Reset (see §... -
Page 38: Data Transfer Capabilities
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.11. Data transfer capabilities The board supports D32 single data readout, Block Transfer BLT32 and MBLT64, 2eVME and 2eSST cycles. Sustained readout rate is up to 60 MB/s with MBLT64, up to 100 MB/s with 2eVME and up to 160 MB/s with 2eSST. -
Page 39: Chained Block Transfer D32/D64
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Block size = 1024 bytes BERR = enabled BLT size = 16384 bytes N = 4 Fig. 3.23: Example of BLT readout Since some 64 bit CPU’s cut off the last 32 bit word of a transferred block, if the number of words composing such block is odd, it is necessary to add a dummy word (which has then to be removed via software) in order to avoid data loss. -
Page 40: Event Polling
V1724 (64 ADC channels) to a single Optical Link Controller: a standard PC equipped with the PCI card CAEN Mod. A2818. The A2818 is a 32-bit 33 MHz PCI card; the communication path uses optical fiber cables as physical transmission line (Mod. -
Page 41: Caenvme_Init
The present description refers to CAENVMELib, available in the following formats: − Win32 DLL (CAEN provides the CAENVMELib.lib stub for Microsoft Visual C++ 6.0) − Linux dynamic library CAENVMELib is logically located between an application like the samples provided and the device driver. -
Page 42: Caenvme_Readcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Returns: An error code about the execution of the function. Description: Notifies the library about the end of work and free the allocated resources. -
Page 43: Caenvme_Multiwrite
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 [in] Address : An array of VME bus addresses. [out] Data : An array of data read from the VME bus. [in] AM : An array of address modifiers. -
Page 44: Caenvme_Fifobltreadcycle
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 3.13.8. CAENVME_FIFOBLTReadCycle Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [out] Buffer : The data read from the VME bus. [in] Size : The size of the transfer in bytes. -
Page 45: Caenvme_Irqcheck
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Description: The function performs a VME multiplexed block transfer read cycle. The Address is not incremented on the VMEBus during the cycle. CAENVME_API CAENVME_FIFOMBLTReadCycle(int32_t Handle, uint32_t Address, void *Buffer, int Size, CVAddressModifier AM, int *count);... -
Page 46: Caenvme_Irqwait
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 CAENVME_API CAENVME_IRQDisable(long dev, unsigned long Mask); 3.13.14. CAENVME_IRQWait Parameters: [in] Handle : The handle that identifies the device. [in] Mask : A bit-mask indicating the IRQ lines. [in] Timeout : Timeout in milliseconds. -
Page 47: Vme Interface
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4. VME Interface The following sections will describe in detail the board’s VME-accessible registers content. 4.1. Registers address map Table 4.1: Address Map for the Model V1724 REGISTER NAME ADDRESS ASIZE... -
Page 48: Configuration Rom
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 REGISTER NAME ADDRESS ASIZE DSIZE MODE H_RES S_RES CLR ROC FPGA FIRMWARE REVISION 0x8124 A24/A32 DOWNSAMPLE FACTOR 0x8128 A24/A32 EVENT STORED 0x812C A24/A32 SET MONITOR DAC 0x8138... -
Page 49: Channel N Zs_Thres (0X1N24; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Table 4.2: ROM Address Map for the Model V1724 Description Address Content checksum 0xF000 0xA4 checksum_length2 0xF004 0x00 checksum_length1 0xF008 0x00 checksum_length0 0xF00C 0x20 constant2... -
Page 50: Channel N Zs_Nsamp (0X1N28; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4.4. Channel n ZS_NSAMP (0x1n28; r/w) Function With “Full Suppression based on the amplitude” (ZS AMP), bits [20:0] allow to set the number Ns of subsequent samples which must be found over/under threshold (depending on the used logic) necessary to validate the event;... -
Page 51: Chanuffernufferel Nuffer Buffer Occupanuffercy
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Bits [15:0] contain the firmware revision number coded on 16 bit (X.Y format). Example: revision 1.3 of 12 June 2007 is: 0x760C0103 4.9. -
Page 52: Channel Configuration Bit Set (0X8004; W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4.13. Channel Configuration Bit Set (0x8004; w) Function Bits set to 1 means that the corresponding bits in the Channel [7..0] Configuration register are set to 1. 4.14. -
Page 53: Acquisition Control (0X8100; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4.18. Acquisition Control (0x8100; r/w) Function 0 = Normal Mode (default): board becomes full, whenever all buffers are full (see § 4.15) 1 = Always keep one buffer free: board becomes full, whenever N-1buffers are full;... -
Page 54: Software Trigger (0X8108; W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Clock source (see § 2.6): 0 = Internal 1 = External EVENT FULL: it is set to 1 as the maximum nr. of events to be read is reached EVENT READY: it is set to 1 as at least one event is available to readout... -
Page 55: Post Trigger Setting (0X8114; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Function 1 = Channel 6 trigger enabled 0 = Channel 5 trigger disabled 1 = Channel 5 trigger enabled 0 = Channel 4 trigger disabled 1 = Channel 4 trigger enabled 0 = Channel 3 trigger disabled 1 = Channel 3 trigger enabled... -
Page 56: Channel Enable Mask (0X8120; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 Function 0 = TRG/CLK are NIM I/O Levels 1 = TRG/CLK are TTL I/O Levels 4.26. Channel Enable Mask (0x8120; r/w) Function 0 = Channel 7 disabled 1 = Channel 7 enabled 0 = Channel 6 disabled... -
Page 57: Set Monitor Dac (0 X 8138; R / W )
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 4.30. Set Monitor DAC (0x8138; r/w) Function [11:0] This register allows to set the DAC value (12bit) This register in Voltage level mode (see § 2.7). allows to set the DAC value LSB = 0.244 mV, terminated on 50 Ohm. -
Page 58: Vme Control (0Xef00; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 1 = Channel 0 enabled 4.35. VME Control (0xEF00; r/w) Function 0 = RELOC Disabled (BA is selected via Rotary Switch; see § 2.6) 1 = RELOC Enabled (BA is selected via RELOC register;... -
Page 59: Relocation Address (0Xef10; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 11 = intermediate 4.39. Relocation Address (0xEF10; r/w) Function These bits contains the A31...A16 bits of the address of the module: [15..0] it can be set via VME for a relocation of the Base Address of the module. -
Page 60: Flash Data (0Xef30; R/W)
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 1 = Flash write DISABLED This register is handled by the Firmware upgrade tool. 4.47. Flash Data (0xEF30; r/w) Function [7:0] Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool. -
Page 61: Installation
STD position (left), or in the BKP position (right). It is possible to upgrade the board firmware via VME, by writing the Flash; for this purpose, download the software package available at: http://www.caen.it/nuclear/product.php?mod=V1724 The package includes the new firmware release file: •... -
Page 62: V1724 Upgrade Files Description
Base Address (Hex 32 bit) of the V1724 BaseAdd image is '/standard' (default) or '/backup' '/fast' enables fast programming (MultiRead/Write with CAEN Bridge)' disables programming check '/nover' N.B.: it is strongly suggested to upgrade ONLY one of the stored firmware... - Page 63 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1724 8 Channel 14bit - 100MS/s Digitizer 06/11/2007 aligned; it is not guaranteed that the latest revision of one FPGA is compatible with an older revision. Upgrade examples: 1) Upgrade to Rev 1.0(main FPGA)/Rev 0.2 (channel FPGA) of the standard page of the V1724: CAENDigitizerUpgrade v1724_r1_rev1.0_0.2.rbf 32100000 /standard 2) Upgrade to Rev 1.0(main FPGA)/Rev 0.2 (channel FPGA) of the backup page of the...
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