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Summary of Contents for Caen DT5740
- Page 1 Technical Information Manual Revision n. 12 04 May 2016 MOD. DT5740 32 CHANNEL 12 BIT 65 MS/S DIGITIZER MANUAL REV.12 NPO: 00100/09:5740x.MUTx/12...
- Page 2 The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without giving any notice; for up to date information please visit www.caen.it.
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Page 3: Table Of Contents
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 TABLE OF CONTENTS INTRODUCTION ............................6 ..............................6 VERVIEW ............................8 LOCK IAGRAM TECHNICAL SPECIFICATIONS ........................9 ........................9 ACKAGING AND OMPLIANCY .......................... - Page 4 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 ..........................29 RIGGER ANAGEMENT 3.4.1 Software Trigger ..........................30 3.4.2 External Trigger ..........................30 3.4.3 Self-Trigger ............................ 30 3.4.4 Trigger Coincidence Level ......................31 3.4.5...
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Page 5: List Of Figures
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 LIST OF FIGURES . 1.1: M . DT5740 B ........................8 LOCK IAGRAM . 2.1: AC/DC .................... 9 POWER SUPPLY PROVIDED WITH THE MODULE . -
Page 6: Introduction
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 1 Introduction This document contains the full hardware description of the DT5740 module, and the principle of operating as Waveform Digitizer basing on the default firmware for the waveform recording (hereafter called default firmware). -
Page 7: Table 1.1: Available Items
The acquisition can continue without any dead time in a new buffer DT5740 features a front panel CLK-IN connector as well as an internal PLL for clock synthesis from internal/external references. Multiple DT5740 boards can be synchronized to a common clock source ensuring Trigger time stamps alignment. -
Page 8: Block Diagram
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 1.2 Block Diagram FRONT PANEL x32 channels INPUTS AMC [FPGA] ADC & MEMORY CONTROLLER BUFFERS CLOCK CLK IN MANAGER (AD9520) TRG IN... -
Page 9: Technical Specifications
CAEN equipment 2.2 Power Requirements The DT5740 module is powered by the external AC/DC stabilized power supply provided with the digitizer and included in the delivered kit. The board’s typical power consumption is 1.9A (@+12V). -
Page 10: Cooling Management
Bit[3] = 1 sets HIGH the fan speed. WARNING: It is recommended not to run ROC FPGA firmware revision < 4.4 on DT5740 with hardware revision ≥ 4 as the fans will work always at the maximum speed to prevent from hardware damages, but with a high noisiness on the other hand. -
Page 11: Front And Back Panel
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 2.4 Front and Back Panel Fig. 2.2: Mod. DT5740 front panel Fig. 2.3: Mod. DT5740 back panel NPO: Filename: Number of pages: Page: 00100/09:5740x.MUTx/12... -
Page 12: External Connectors
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 2.5 External Connectors 2.5.1 ANALOG INPUT connectors The module has 32 channels on single ended ERNI SMC input connector (see Fig. 2.4). -
Page 13: Control Connectors
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 Fig. 2.7: MCX connector Function: Analog input, single ended, input dynamics: 2V Zin = 50Ω (DT5740C: 10V Zin = 1KΩ) Mechanical specifications:... -
Page 14: Adc Reference Clock Connectors
Compliant to Multimode 62.5/125μm cable featuring LC connectors on both sides. CAEN provides optical fiber cable selection for A3818 and A2818 Controllers (see Table 1.1) with duplex connector on the controller side and two simplex connectors on the digitizer side; the simplex connector with the black wrap is for the RX line (lower) and the one with the red wrap is for the TX (higher). -
Page 15: Dc Input
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 2.5.6 12V DC Input Function: Input connector for the Desktop digitizer 12V main power supply from the external AC/DC adapter. Mechanical specifications: RAPC722X PCB DC Power Jack. -
Page 16: Technical Specifications Table
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 2.7 Technical Specifications Table Table 2.3: Mod. DT5740 technical specifications Form Factor Weight GENERAL 154x50x164 mm (WxHxD) Desktop 680 g Channels Connector... - Page 17 Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 ADC & MEMORY Altera Cyclone EP3C16 or EP3C40 (DT5740D only) CONTROLLER One FPGA serves 16 channels Optical Link CAEN CONET proprietary protocol USB 2.0 compliant...
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Page 18: Functional Description
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3 Functional Description 3.1 Analog Input Input dynamic is 2V = 50 Ω). A 10V = 1 kΩ) dynamic is available on request. By means of a 16-bit DAC it is possible to add up to a ±1V DC offset (±5V @10V... -
Page 19: Clock Distribution
(via local oscillator) source, in the latter case OSC-CLK and REF-CLK will be synchronous (the operation mode remains the same anyway). DT5740 uses an integrated phase-locked-loop (PLL) and clock distribution device (AD9520). It is used to generate the sampling clock for ADCs and mezzanine FPGA (SAMP-CLK0/SAMP-CLK1), as well as the trigger logic synchronization clock (TRG-CLK). -
Page 20: Pll Mode
3. External clock source different from 50 MHz – In this case, it is necessary to re-program the AD9520. NOTE: please, contact CAEN (§ 8) for the feasibility of point 3 and to receive the PLL programming file. PLL programming files can then be loaded by the user by using the CAENUpgrader software tool. -
Page 21: Reducing The Sampling Frequency
3.2.2 Reducing the Sampling Frequency It could be required to operate the DT5740 at a sampling frequency (SAMP-CLK) lower than the nominal. In principle, this can be alternatively achieved by: 1. Direct way: reprogramming the AD9520 dividers. REF-CLK can be configured as in § 3.2.1. Not all the frequencies are admitted and a lower frequency limit must be considered, due to the internal electronics. -
Page 22: Acquisition Modes
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.3 Acquisition Modes 3.3.1 Acquisition Run/Stop The acquisition can be started and stopped in different ways, according to bits[1:0] setting of Acquisition Control register (address 0x8100) and bit[2] of the same register: ... -
Page 23: Fig. 3.3: Trigger Overlap
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 EVENT n EVENT n+1 EVENT n+2 Recorded Not Recorded TRIGGER POST ACQUISITION WINDOW Overlapping Triggers Fig. 3.3: Trigger Overlap A trigger can be refused for the following causes: ... -
Page 24: Multi-Event Memory Organization
3.3.3 Multi-Event Memory Organization Each channel of the DT5740 features a SRAM memory to store the acquired events. The memory size for the event storage is 192 kS/ch and it can be divided in a programmable number, N , of buffers (N from 1 up to 1024) by the register address 0x800C, as described in Table 3.1 below. -
Page 25: Event Structure
4.5 on (reserved otherwise), this bit is set to “1” in consequence of a hardware problem (e.g. PLL unlocking). The user can collect more information about the cause by reading at register address 0x8104 and contact CAEN Support Service if necessary (see § 8); EVENT MODE (Bit[24] of 2 header word) = this bit identifies the event format;... -
Page 26: Data
Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 GROUP MASK (Bit[7:0] of the 2 header word) = it is the mask of the groups participating in the event (e.g. GR1 and GR3 participating → Group Mask = 0xA). This information must be used by the software to acknowledge which group the samples are coming from (the first event contains the samples from the group with the lowest number);... -
Page 27: Event Format Examples
3.3.4.3 Event Format Examples Fig. 3.4 shows the event format of the DT5740 digitizer as described in § 3.3.4. NOTE: data transfer starts from Channel 0 of Group 0; once all the data from one Group are transferred, data transfer from the subsequent Group (from 0 to 3) begins. -
Page 28: Acquisition Synchronization
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.3.5 Acquisition Synchronization Each channel of the digitizer is provided with a SRAM memory that can be organized in a programmable number N of circular buffers (N = [1:1024], see Table 3.1). -
Page 29: Trigger Management
Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.4 Trigger Management According to the default firmware operating, all the channels in a board share the same trigger (board common trigger), so they acquire an event simultaneously and in the same way (a determined number of samples according to buffer organization and custom size settings, and position with respect to the trigger given by the post-trigger). -
Page 30: Software Trigger
3.4.3 Self-Trigger In the trigger domain, the input channels of the DT5740 are managed as 8-channel groups: Group 0 = 0÷7 Ch, Group 1 = 8÷15 Ch, Group 2 = 16÷23 Ch and Group 3 = 24 ÷31 Ch. Each... -
Page 31: Trigger Coincidence Level
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.4.4 Trigger Coincidence Level Operating with the default firmware, the acquisition trigger is a board common trigger. This common trigger allows the coincidence acquisition mode to be performed through the Majority operation. -
Page 32: Fig . 3.8: Trigger Requests Relationship With Majority Level
Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 Fig. 3.8 shows the trigger management in case the coincidences are enabled with Majority level = 1 and T is a value different from 0. -
Page 33: Fig . 3.9: Trigger Requests Relationship With Majority Level
(no T is waited). TVAW NOTE: a practical example of making coincidences with the digitizer in the standard operating is detailed in the document: GD2817 - How to make coincidences with CAEN digitizers (web available). NPO: Filename: Number of pages: Page: 00100/09:5740x.MUTx/12... -
Page 34: Trigger Distribution
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.4.5 Trigger Distribution As described in § 3.4, the OR of all the enabled trigger sources, synchronized with the internal clock, becomes the common trigger of the board that is fed in parallel to all channels, consequently provoking the capture of an event. -
Page 35: Example
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.4.5.1 Example For instance, it could be required to start the acquisition on all the channels of a multi-board system as soon as one of the channels of a board (board “n”) crosses its threshold. Trigger Out signal is then fed to an external Fan Out logic unit;... -
Page 36: Reset, Clear And Default Configuration
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 3.5 Reset, Clear and Default Configuration 3.5.1 Global Reset Global Reset is performed at Power-On of the module or via software by write access at register address 0xEF24 (whatever 32-bit value can be written). -
Page 37: Data Transfer Capabilities
04/05/2016 3.6 Data Transfer Capabilities DT5740 features a Multi-Event digital memory per channel, configurable by the user to be divided into 1 up to 1024 buffers, as detailed in § 3.3.3. Once they are written in the memory, the events become available for readout via USB or Optical Link. During the memory readout, the board can store other events (independently from the readout) on the available free buffers. -
Page 38: Optical Link And Usb Access
80 MB/s. The latter allows to connect up to 8 DT5740 boards to a single A2818 PCI Optical Link Controller or up to 32 boards to a single A3818 PCIe Optical Link Controller. -
Page 39: Drivers & Libraries
4 Drivers & Libraries 4.1 Drivers In order to interface with the DT5740, CAEN provides the drivers for all the different types of physical communication channels featured by the board and compliant with Windows and Linux • USB 2.0 Drivers are downloadable on CAEN website (www.caen.it) in the “Software/Firmware”... -
Page 40: Fig. 4.1: Block Diagram Of The Software Layers
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 CAENComm (and so the CAENDigitizer) supports the following communication channels: PC → USB → DT5740 PC → PCI/PCIe (A2818/A3818) → CONET → DT5740 User’s own SW... -
Page 41: Software Tools
User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 5 Software Tools CAEN provides software tools to interface the DT5740, which are available for free download on www.caen.it at: Home / Products / Firmware/Software / Digitizer Software 5.1 CAENUpgrader CAENUpgrader is a free software composed of command line tools together with a Java Graphical User Interface. -
Page 42: Caencomm Demo
Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 5.2 CAENComm Demo CAENComm Demo is a simple program developed in C/C++ source code and provided both with Java and LabVIEW GUI interface. The demo mainly allows for a full board configuration at low level by direct read/write access to the registers and may be used as a debug instrument. -
Page 43: Caen Wavedump
Linux needs the required libraries to be previously installed by the user. Installation packages and documentation can be downloaded on CAEN web site (login required) Home / Products / Firmware/Software / Digitizer Software / Readout Software / CAEN WaveDump NPO: Filename:... -
Page 44: Dpp-Qdc Demo Software
DPP-QDC Demo Software is provided including C source files for developers DPP-QDC Demo Software can operates with Windows OS, 32 and 64-bit. Installation packages and documentation can be downloaded on CAEN web site (login required) Home / Products / Firmware/Software / DPP Firmware/Software Tools (Digitizer) / DPP Firmware / DPP-QDC... -
Page 45: Hw Installation
6.1 Power-on Sequence To power on the board, follow this procedure: 1. connect the 12V DC power supply to the DT5740 through the DC input rear connector; 2. power up the DT5740 through the ON/OFF rear switch. See § 2.5 to identify the relevant components. -
Page 46: Firmware And Upgrades
Title: Revision date: Revision: User's Manual (MUT) Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 7 Firmware and Upgrades The board hosts one FPGA on the mainboard and two FPGAs on the mezzanine (i.e. one FPGA per 16 channels or two 8-channel groups). The channel FPGAs firmware is identical. A unique file is provided that will update all the FPGAs at the same time. -
Page 47: Default Firmware Upgrade
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 7.1 Default Firmware Upgrade The DT5740 is delivered running a default firmware to operate the board for waveform recording. The default firmware updates are available for download on CAEN website (www.caen.it) in the Software/Firmware tab at the DT5740/DT5740D web pages (login required): Home / Products / Modular Pulse Processing Electronics / VME / Digitizers / <Digitizer Model>... -
Page 48: Dpp Firmware Upgrade
7.2.1 DPP Firmware File Description The extension of the programming DPP firmware file is CFA (CAEN Firmware Archive), which is a sort of archive format file aggregating all the firmware files compatible with the same DPP firmware and family of digitizers. -
Page 49: Troubleshooting
STD page of the FLASH. In this case, when a failure occurs during the upgrade of the STD page of the FLASH, which compromises the communication with the DT5740, the user can perform the following recovering procedure as first attempt: - Force the board to reboot loading the copy of the firmware stored on the BKP page of the FLASH. -
Page 50: Technical Support
Mod. DT5740 32 Channel 12bit - 65MS/s Digitizer 04/05/2016 8 Technical Support CAEN support services are available for the user by accessing the Support & Services area on CAEN website at www.caen.it. 8.1 Returns and Repairs Users who need for product(s) return and repair have to fill and send the Product Return Form (PRF) in the Returns and Repairs area at Home / Support &...
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