Related Manuals for National Semiconductor LMK01000
Summary of Contents for National Semiconductor LMK01000
- Page 1 LMK01000 Precision Clock Conditioner Evaluation Board Operating Instructions 2-20-2008 National Semiconductor Corporation Interface Division 10333 North Meridian Street Suite 400 Indianapolis, IN, 46290...
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Page 2: Table Of Contents
ABLE OF ONTENTS ..........................3 ENERAL ESCRIPTION ............................3 ASIC PERATION ........................... 6 OARD NFORMATION CLKin Inputs ......................6 CLKout Outputs......................7 SYNC*........................8 GOE*........................8 OISE LOOR EASUREMENTS ....................10 Reason and Methodology ..................10 Charts ........................11 ..........................12 ELAY EASUREMENTS .......................... -
Page 3: General Description
• CodeLoader software The CodeLoader software will run on a Windows 2000 or Windows XP PC. The purpose of the CodeLoader software is to program the internal registers of the LMK01000 device through a MICROWIRE interface. Basic Operation To prepare the computer for use with the evaluation board, first install the CodeLoader4 software. Reference the document, “Installing CodeLoader 4”... - Page 4 4) Connect… • PC directly to the evaluation board with the LPT to 10 pin uWire cable, plugging the cable into an LPT port on the computer. This setup is shown below. The cable can be removed after programming to minimize noise and EMI.
- Page 5 7) Select (ENABLE) output to measure, any of CLKout (0-7) or EN_CLK from either Clock Outputs or Bits/Pins tabs. For default mode, all outputs are disabled. 8) Program the LMK01000 evaluation board by clicking “Keyboard Controls” “Load Device”, or by pressing Ctrl+L.
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Page 6: Board Information
CLKin Inputs CLKin0 is one of two inputs that can be used to drive the LMK01000. Although this input is rated to higher frequencies, the balun on the board is only rated to 400 MHz. Ensure CLKin_SELECT is set to CLKin0 when using this input. -
Page 7: Clkout Outputs
CLKout Outputs CLKout0 to CLKout2 are LVDS outputs. For CLKout2, there is a balun attached, so it can be attached to single- ended test equipment. Although the output is rated to higher frequencies, the balun is only rated to 400 MHz. CLKout3 to CLKout7 are LVPECL outputs and all are configured the same. -
Page 8: Sync
This input connects to the SYNC* pin that can be used to synchronize the outputs in the event that they are dividing the input signal (divided mode). For bypass mode, this is not necessary. For the LMK01000 to run, this has to be set to high logic level. -
Page 9: Recommended Equipment
Recommended Equipment Power Supply The Power Supply should be a low noise power supply. An Agilent 6623A Triple power supply with external LC filters or an HP E3610A with external LC filters was used in creating these evaluation board instructions. The LC filters on the outputs help to reduce noise from the power supplies. -
Page 10: Noise Floor Measurements
LMK01000. The measured output noise consists of the output noise of the LMK01000 - plus the inherent noise of the signal generator, or reference signal input, chosen. To determine the actual noise floor of the device, the input noise must be measured, or interpolated. The charts referenced below were compiled with measurements from an Agilent E5052A Signal Source Analyzer. -
Page 11: Charts
Charts 245.76 MHz Input – Actual Measurements -135 LVDS—elevated dBc measurements— not -140 intended for single- ended performance. -145 Chart #1 -150 -155 -160 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Offset (Hz) S igGen LVDS Single-Ended LVDS Balun LVPE CL Single-E nded 245.76 MHz Input –... -
Page 12: Delay Measurements
Delay Measurements These measurements illustrate how skew errors due to different length traces, may be tuned out. The delay may be adjusted in steps of 150 ps. Delays 150, 300, 450, 600, 750 ps CLKout0_DLY = 0 ps CLKout1_DLY = 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350,... -
Page 13: Codeloader Settings
CodeLoader Settings Default Mode The default mode for all programming registers can be restored by clicking Mode “245.76 MHz OSCin”. The default reference oscillator used for these instructions is 245.76 MHz and the restored mode expects a 245.76 MHz OSCin signal. For the loaded mode to take affect the device must be first loaded by pressing Ctrl+L. - Page 14 Port Setup and Debugging Communication Issues Debugging Communication Issues Ensure that the correct mode of USB or LPT is selected. Ensure that the port setup is correct Ensure that the cable is properly hooked to the board such that it dangles off the edge of the board, as opposed to across the board.
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Page 15: Bits/Pins Tab
Bits/Pins Tab The Bits/Pins tab shows some of the internal registers, which are not accessible from any of the other visual tabs like “Clock Outputs”. Right-click on any of the bits to view a description. Program Bits POWERDOWN Powers the part down. The registers can be defaulted by checking and un-checking RESET. -
Page 16: Clock Outputs Tab
Clock Outputs Tab The Clock Outputs tab allows the user to visualize the clock distribution portions of the device. From this tab the device’s dividers, delays, clock output muxes, and output drivers can be programmed. Remember to enable an output to observe it. Note: the enables on this page are linked directly to the EN_CLKoutX on the Bits/Pins tab. -
Page 17: Appendix A: Schematic
0 ohm CLKin1 1 uF 0.1 uF Open Bias CLKin1* Vcc1 CLKin1 CLKuWire Vcc10 DATAuWire Open Open LEuWire Vcc9 LMK01000 0 ohm Open Vcc8 ADT 2-1T CLKin0* 0.1 uF Open Open Vcc2 CLKin0* Open Open 100 ohm CLKin0 CLKin0 SYNC* 0.1 uF... - Page 18 CLKout0 CLKout1 CLKout2 Open Open Open Open Open Open Open Open Open Open ADT2-1T CLKout0 CLKout1 CLKout2 CLKout0 CLKout1 CLKout2 0.1 uF 0.1 uF 0.1 uF Open Open Open Open CLKout0* CLKout2* CLKout1* ADT 2-1T CLKout0* CLKout1* CLKout2* Open 0.1 uF 0.1 uF 0.1 uF Open...
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Page 19: Appendix B: Layer Stack Up Information
Appendix B: Layer Stack up Information Top Layer 1oz thick RO4003 (Er = 3.38) CONTROLLED THICKNESS of 16 mils thick GND plane FR4 (Er = ~4.6) CONTROLLED THICKNESS: 2.5mils Vcc Plane Make sure total board thickness is 62 mils Bottom Layer... -
Page 20: Appendix C: Bill Of Materials
FCI Electronics 52601-S10-8 uWire Vcc,CLKin0,CLKin1,CLKin1*,CLKout0, CLKout0*, CLKout1,CLKout1*,CLKout2, CLKout3,CLKout3*, Johnson Components 142-0701-851 CLKout4, CLKout4*,CLKout5,CLKout5*,CLKout6,CLKout6*, CLKout7, CLKout7*,GOE,SYNC* LMK010X0 PCB National Semiconductor LMK010X0EVPCB 0.375" Stand-Offs SPC Technology SPCS-6 Place in 4 corner holes of the board Clock Conditioner National Semiconductor LMK01000 3.3 V zener... - Page 21 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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