Architecture; System Block Diagram - Compaq DS20E - AlphaStation - 1 GB RAM Technical Manual

Architecture

This system is designed to maximize the potential of the Alpha
21264 chip. The traditional bus interconnect has been replaced
by a switch-based interconnect system. With a bus design, the
processors, memory, and I/O modules must share the bus. As
the number of bus users increases, the transactions interfere
with one another, increasing latency and decreasing aggregate
bandwidth. However, with a switch-based system there is no
degradation in performance as the number of CPUs, memory,
and I/O users increase. Although the users increase, the speed is
maintained.
With a switch-based, or point-to-point interconnect, the perform-
ance remains constant, even though the number of transactions
multiplies. The switched system interconnect uses a set of com-
plex chips that route the traffic over multiple paths. The chipset
consists of one C-chip, eight D-chips, and two P-chips,
2
Command, Address, and Control lines for each Memory Array
C-chip
Control lines for D-chips
Probe/
Probe/
Addr. CAPbus
Addr.
P-chip
CMD/
Addr.
CPU 1
(optional)
CMD/
Addr.
CPU 0
CPU
Data
Bus
B-cache
B-cache

System Block Diagram

C-chip. Provides the interface from the CPUs and main
memory. Although there is only one in the system, it
allows each CPU to do transactions simultaneously.
D-chips. Provide the data path for the CPUs, main
memory, and I/O.
P-chips. Provide the interface to two independent 64-bit
PCI buses.
The DS20E system supports up to two CPUs and up to 4
Gbytes memory in 16 DIMM slots. Each memory option
contains four DIMMs, so each bank has four DIMMs.
Two 256-bit memory buses support four memory arrays,
yielding a 5.2 Gbytes/sec system bandwidth. Transactions are
ECC protected. Upon the receipt of data, the receiver checks
for data integrity and corrects any errors. Commands and
addresses are parity protected.
P-chip
64 bit PCI
64 bit PCI
PAD
Bus
1 or 2
Memory
Banks
Memory
Data
Bus
8 D-chips
1 or 2
Memory
Banks
PKW1400-99