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Curtiss-Wright VMESC5 Hardware Reference Manual

Slave 5-slot ip module carrier
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Systran VMESC5
IP Module Carrier
A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
• C r i t i c a l a n d e x p e d i t e d s e r v i c e s
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Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate, representative, or authorized distributor for any manufacturer listed herein.
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  • Page 1 Systran VMESC5 IP Module Carrier In Stock Used and in Excellent Condition Open Web Page https://www.artisantg.com/66482-2 A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
  • Page 2 VMESC5 VME6U Slave 5-Slot IP Module Carrier Hardware Reference Document No. B-T-MR-VMESC5##-A-0-A6...
  • Page 4 ALTERA: Code © 1997, 2000, Curtiss-Wright Controls, Inc., All Rights Reserved. The code (programs) contained in this product are proprietary to Curtiss-Wright Controls, Inc. and copying or other use of the bit-stream programs, except as expressly authorized by Curtiss-Wright Controls, Inc., are expressly prohibited.
  • Page 5 This product is intended for use in industrial, laboratory or military environments. This product uses and emits electromagnetic radiation which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.

  • Page 6: Table Of Contents

    3.1 Unpacking the VMESC5 ..................3-1 3.2 Visual Inspection of the VMESC5 ................3-1 3.3 VMESC5 Installation....................3-1 3.3.1 Installation of IP Modules on the VMESC5..........3-2 3.3.2 VMESC5 VME Base Address..............3-3 3.3.3 Installation of I/O Cables................. 3-6 3.4 VMESC5 IP Module STROBE Connector............... 3-7...
  • Page 7 Figure 2-4 IACK Daisy Chain on the Carrier ................2-5 Figure 2-5 VMESC5 Block Diagram................... 2-7 Figure 2-6 VMESC5 Mechanical Assembly................2-8 Figure 3-1 Installation of an IP Module on the VMESC5............3-2 Figure 3-2 VMESC5 Jumpers J5 - J1.................... 3-3 TABLES Table 2-1 Interrupt Request Level Priorities................

  • Page 8: Introduction

    1.2 Scope This manual covers the physical and operational description of the VMESC5, both from hardware and software perspectives. This manual also contains detailed technical information about the VMESC5’s performance characteristics, and a few typical applications.

  • Page 9: Reliability

    INTRODUCTION 1.5 Reliability Curtiss-Wright Controls’ policy is to provide the highest quality products in support of customer needs. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Curtiss-Wright Controls’ commitment to quality begins with product concept, and continues after receipt of the purchased product.

  • Page 10: Technical Support

    • Word Wide Web address: www.cwcembedded.com 1.7 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time.
  • Page 11 INTRODUCTION This page intentionally left blank Copyright 2004 VMESC5 HW Reference Manual...

  • Page 12: Product Overview

    Figure 2-1 VMESC5 Board 2.2 Functional Description The VMESC5 is a VME6U slave board that supports five singlewide IP Modules, three singlewide and one doublewide, or one singlewide and two doublewide IP Modules. This carrier is limited to the support of 8 MHz IP Modules. DMA and Memory accesses are not supported.

  • Page 13: Features

    VME-to-IP Module bus coupling carrier. The VMESC5 provides up to 250 I/O points (50 per IP Module) per VME6U slot with the entire area under the IP Modules as a solid ground plane to provide “quiet” operating conditions for sensitive analog IP Modules.

  • Page 14: Vme Memory Mapping Scheme

    N_INTREQ0 and N_INTREQ1. Upon receipt of the interrupt acknowledge from the VMEbus master, the VMESC5 will conduct a D8 transfer of the interrupt vector from the IP Module to the VMEbus. The interrupt request release will be dependent upon the individual IP Module being used.

  • Page 15: Figure 2-2 Interrupt Priority Tiers

    The relative position in the daisy chain is determined by the VME chassis slot location (see Figure 2-3) and the IP Module slot location on the VMESC5 carrier (see Figure 2-4). Copyright 2004...

  • Page 16: Figure 2-3 Vme Chassis Slot Prioritization Through Iack Daisy Chain

    Chain IRQ level IRQ level Figure 2-3 VME Chassis Slot Prioritization Through IACK Daisy Chain The VMESC5 IP Module slot priority order from highest to lowest is A0, A1, B0, B1, C0, C1, D0, D1, E0, E1. VMESC5 Module A...

  • Page 17: General Purpose Registers

    2.2.9 Diagnostic LEDs Seven diagnostic LEDS are located on the front panel of the VMESC5. Six of the LEDs, labeled A, B, C, D, E, and CRA, indicate when a read or write access is attempted to one of the five IP Module slots or the carrier registers.

  • Page 18: Theory Of Operation

    The P1 connector is located on the upper left of the VMESC5 Assembly Drawing (Figure 2-6). When looking at the “top” or component side of the VMESC5, the IP Module slots are labeled from left to right for slot A through slot E. All of the I/O signals are connected through the five 50-pin connectors located at the bottom of Figure 2-6.

  • Page 19: Functional Logic Module Overview

    The VMESC5 board has VHDL models that are sectioned into four functional logic blocks. Two of them are located in the VMESC5 module. The VMESC5 module works in conjunction with two other modules called VSC5INT and the V5LEDIPR module for driving the front panel LEDs and the IP Module’s N_RESETx lines.

  • Page 20: Vsc5Int Module

    VMEbus and assert DTACK upon detection of the appropriate IP Module N_ACK signal. REGISTERS The VMESC5 module contains the Reset, Error Status, and General Purpose registers. For a detailed description of these registers, see Appendix B. 2.4.2 VSC5INT Module VME INTERRUPT ENGINE This module detects an interrupt request(s) from an IP Module(s), then asserts and selects VME interrupt request level(s).

  • Page 21: V5Ledipr Module

    The V5LEDIPR module is responsible for monitoring all of the IP Module select signals from the VMESC5 module, combinationally driving the front panel LEDs from the one- shot drivers, and for logically “ORing” the VME system reset (V_SYSRESET) with the individual IP Module reset one-shot signals for driving each IP Module Reset signal.

  • Page 22: Installation

    Examine the VMESC5 to determine if any damage occurred during shipping. 3.3 VMESC5 Installation NOTE: The VMESC5 is an Electrostatic Sensitive Device (ESD). Use an anti-static mat connected to a wristband when handling or installing the board. The tools required for the VMESC5 installation are listed in Table 3-2.

  • Page 23: Installation Of Ip Modules On The Vmesc5

    2a. Remove the VMESC5 from it’s shipping container and move it to the ESD controlled area where the installation of the IP Module(s) can be made. *2b. Remove the VMESC5 from the VME card cage and move it to the ESD controlled area where the installation of the IP Module(s) can be made.

  • Page 24: Vmesc5 Vme Base Address

    INSTALLATION 3.3.2 VMESC5 VME Base Address The VMESC5 VME board base address is set with five jumpers J5 - J1, corresponding to VME address bits A15 to A11, respectively. The board can be placed at one of 32 possible base addresses on 2 K boundaries.
  • Page 25 INSTALLATION For details of VME accesses to the VMESC5 on-board registers or IP Modules, see Appendix B. NOTE: When using the MVME162 with OS-9, OS-9 maps the VMEChip2 GCSRs (Global Control Status Registers) to the beginning of short I/O space. This causes a bus conflict with boards placed at this address.

  • Page 26: Table 3-3 Vmesc5 Board Base Address Jumper Selection Table

    INSTALLATION Table 3-3 VMESC5 Board Base Address Jumper Selection Table J5(A15) J4(A14) J3(A13) J2(A12) J1(A11) VME Short I/O Address (hex) 0x0000 0x0800 0x1000 0x1800 0x2000 0x2800 0x3000 0x3800 0x4000 0x4800 0x5000 0x5800 0x6000 0x6800 0x7000 0x7800 0x8000 0x8800 0x9000 0x9800...

  • Page 27: Installation Of I/O Cables

    All of the VMESC5 IP Module I/O connector pin numbers directly correspond to each IP Module I/O pinout (i.e. a one-to-one relationship with pin 50 connected to pin 50 down to pin 1 connected to pin 1).

  • Page 28: Vmesc5 Ip Module Strobe Connector

    J17 with the IP Module slot “A” strobe signal on pin 1 through slot “E” on pin 5 with pin 6 grounded. Each of the strobe signals on the VMESC5 are pulled-up to +5 V via 10 KΩ resistors. The strobe connector (J17) is located at the upper left of the VMESC5 Assembly Drawing (which is at the top of the VMESC5 when installed).
  • Page 29 VMEA15 VME_A7 IRQ7* V_IRQ7 VMEA14 VME_A6 IRQ6* V_IRQ6 VMEA13 VME_A5 IRQ5* V_IRQ5 VMEA12 VME_A4 IRQ4* V_IRQ4 VMEA11 VME_A3 IRQ3* V_IRQ3 VMEA10 VME_A2 IRQ2* V_IRQ2 VMEA9 VMEA1_IN IRQ1* V_IRQ1 VMEA8 -12V -12V +5VSTDBY +12V +12V Copyright 2004 VMESC5 HW Reference Manual...
  • Page 30 IP Module signal nomenclature, and the signals on the right are those used by Curtiss-Wright Controls, Inc. The lower case “x” in the Curtiss-Wright Controls, Inc. signal name represents the “A”, “B”, “C”, “D”, or “E”...

  • Page 31: Table 3-7 Ip Module Logic Bus Pin Assignments

    +12 Vdc +12 Vdc -12V -12VDC -12 Vdc -12 Vdc BS1* V_BS1 BS0* V_BS0 VLD15 VLD14 VLD13 VLD12 VLD11 VLD10 VLD9 VLD8 VLD7 VLD6 VLD5 VLD4 VLD3 VLD2 VLD1 VLD0 Reset* N_IPxRESET ICLK_x Copyright 2004 3-10 VMESC5 HW Reference Manual...

  • Page 32: Appendix Aspecifications

    APPENDIX A SPECIFICATIONS...
  • Page 34 Shock (Operating): 50 G's maximum, all axes • Altitude (Operating): 10,000 feet maximum MEAN TIME BETWEEN FAILURE (MTBF): • 616292 hours per MIL-HDBK-217F • 559372 hours per Bellcore 332 Issue 6 ground benign environment. Copyright 2004 VMESC5 HW Reference Manual...
  • Page 35 SPECIFICATIONS This page intentionally left blank. Copyright 2004 VMESC5 HW Reference Manual...

  • Page 36: Appendix Bprogramming Guide

    B.6 VMESC5 Programming Examples ..................B-5 B.6.1 Reset Example......................B-5 B.6.2 Interrupt Initialization Example ..................B-5 TABLES Table B-1 VMESC5 Address Map ....................B-2 Table B-2 Reset Register Bit Description..................B-3 Table B-3 Error Status Register Bit Description................B-3 Table B-4 Interrupt Level Register Bit Description..............B-4...

  • Page 38: Overview

    Chapter 2. and application concepts are discussed in Appendix D. B.2 Description The VMESC5 is an easy to use VME6U slave card that holds five singlewide, three singlewide and 1 doublewide, or 1 singlewide and 2 doublewide IP Modules. In addition to providing access to the I/O and ID space of the IP Modules via the VMEbus, the VMESC5 has 12 onboard control/status registers.

  • Page 39: Address Map

    B.4 Address Map The IP Module IO and ID spaces, and the carrier’s control and status registers, reside at a fixed relative address from the VMESC5 base address. Table B-1 shows the complete memory map for the board. Table B-1 VMESC5 Address Map...

  • Page 40: Register Descriptions

    PROGRAMMING GUIDE B.5 Register Descriptions The VMESC5 registers can be accessed as byte (D8) or word (D16) values. When accessed as words, the upper byte is not driven by the carrier and its value is all ‘1’s due to VLD[15:8] pull-up resistors. The unused bits in the lower byte are driven as ‘0’s on reads.

  • Page 41: Interrupt Level Registers A To E (0X580/0X581 To 0X588/0X589

    B.5.4 General Purpose Registers A to E (0x600/0x601 to 0x608/0x609) General purpose registers A to E are completely user definable. These read/write registers can be used for semaphores, shared memory, etc. For more application information regarding these registers, see Appendix D. Copyright 2004 VMESC5 HW Reference Manual...

  • Page 42: Vmesc5 Programming Examples

    State NOTE: GPR7-GPR0: The General Purpose Register byte value. B.6 VMESC5 Programming Examples The following examples illustrate how to program the VMESC5 to achieve various operational modes. B.6.1 Reset Example This example resets one, then all five IP Modules, and then monitors the reset signals to determine when they are de-asserted.
  • Page 43 VME chassis slot location and the IP Module slot location on the VMESC5 carrier. The VMESC5 IP Module slot priority order from highest to lowest is A0, A1, B0, ... D1, E0, E1. For more details regarding interrupt prioritization, see Chapter 2. or Appendix D.

  • Page 44: Appendix Cperformance

    APPENDIX C PERFORMANCE TABLE OF CONTENTS C.1 Overview ..........................C-1 C.2 State Timing Diagrams ......................C-1 C.2.1 ID Read Cycle......................C-2 C.2.2 I/O Read Cycle......................C-3 C.2.3 I/O Write Cycle......................C-4 C.2.4 I/O Read-Modify-Write Cycle ..................C-5 C.2.5 I/O Write Cycle With IP Module Wait States.............C-6 C.2.6 Interrupt Request......................C-7 FIGURES Figure C-1 Performance Test Equipment Configuration .............C-1...

  • Page 46: Overview

    Chapter 2. and Appendix A. C.2 State Timing Diagrams The VMESC5 test configuration consisted of a typical VME card cage with a MVME- 162-23 as the host CPU and one Curtiss-Wright Controls TESTIP installed in slot ‘A’...

  • Page 47: Id Read Cycle

    PERFORMANCE C.2.1 ID Read Cycle Figure C-2 is a complete ID read cycle of the TESTIP on the VMESC5 in slot ‘A’. On the left side of the figure the MVME-162 initiated a VME read cycle by asserting a valid address and then asserting the VME address and data strobe (V_AS and V_DS0) signals.

  • Page 48: I/O Read Cycle

    ICLK (at the end of the terminate cycle) and drives the VME data bus. About 9 or 10 ns after the VME data bus is driven, the VMESC5 asserts the VME data acknowledge (VDTACK) signal and waits for the VME host CPU to terminate the VME read cycle by de-asserting the address and data strobes signals.

  • Page 49: I/O Write Cycle

    PERFORMANCE C.2.3 I/O Write Cycle Figure C-4 is a complete I/O write cycle to the TESTIP on the VMESC5 in slot ‘A’ . On the left side of the figure, the MVME-162 initiated a VME write cycle by asserting a valid address and data along with the VME write (VMER/W) signal, and then asserting the VME address and data strobe (V_AS and V_DS0) signals.

  • Page 50: I/O Read-Modify-Write Cycle

    PERFORMANCE C.2.4 I/O Read-Modify-Write Cycle Figure C-5 is a complete I/O read-modify-write cycle to the TESTIP on the VMESC5 in slot ‘A’. On the left side of the figure, the MVME-162 initiated a VME read cycle by asserting a valid address and then asserting the VME address and data strobe (V_AS and V_DS0) signals.

  • Page 51: I/O Write Cycle With Ip Module Wait States

    C.2.5 I/O Write Cycle With IP Module Wait States Figure C-6 is a complete I/O write cycle to the TESTIP on the VMESC5 in slot ‘A’, similar to Figure C-4 except with IP Module wait states inserted. On the left side of the...

  • Page 52: Interrupt Request

    (ISR) from the MVME-162 host CPU. For this test, the VMESC5 was configured to drive the VME interrupt level one request (V_IRQ1) when the TESTIP asserted the IP Module interrupt request signal zero (INTRQ0). On the left side of the figure, the TESTIP has asserted the INTRQ0 and about 1.5 µs later the...
  • Page 53 Figure C-8 is a zoomed in view of the TESTIP driving the INTRQ0 signal and in turn the VMESC5 driving the VME interrupt request level one signal (V_IRQ1) in about 14 ns. Figure C-8 IP Module INTREQ0 Driving VME IRQ1...
  • Page 54 IP Module terminate cycle. On the right side of the figure, the VMESC5 DTE latches the data from the TESTIP on the rising edge of ICLK (at the end of the terminate cycle) and drives the VME data bus. About 9 or 10 ns after the VME...
  • Page 55 VME IACKOUT daisy-chain signal being passed along by the VMESC5 in about 64 ns. This means that the VMESC5 will not cause a VME system time-out or bus error by driving the IACKOUT signal as fast as possible.

  • Page 56: Appendix Dtypical Applications

    APPENDIX D TYPICAL APPLICATIONS TABLE OF CONTENTS D.1 Applications ...........................D-1 D.2 Sharing IP Modules between Multiple VME Masters ............D-1 D.2.1 VME Master 1......................D-2 D.2.2 VME Master 2......................D-2 D.3 Configuring Interrupts for Multiple Priority Schemes............D-3 FIGURES Figure D-1 A System With Two VME Masters................D-1...

  • Page 58: Applications

    Curtiss-Wright Controls, Inc. extends an open invitation to all users to freely submit their applications that might, or do, use the VMESC5 Slave Carrier to solve a problem. This section of the manual will be revised periodically to include new application ideas for all users to consider.

  • Page 59: Vme Master 1

    Send the IP Module x data to the remote computer. This is just one example of using the General Purpose registers. They are completely user definable and therefore can be used for any purpose. Copyright 2004 VMESC5 HW Reference Manual...

  • Page 60: Configuring Interrupts For Multiple Priority Schemes

    Some systems must run more than one application for a given hardware configuration. The two applications may require two distinct interrupt priority schemes. This example illustrates how to configure the interrupt level registers on the VMESC5 to achieve two different priority schemes.
  • Page 61 TYPICAL APPLICATIONS This page intentionally left blank Copyright 2004 VMESC5 HW Reference Manual...
  • Page 62 GLOSSARY...
  • Page 64 µs, ms-------------------------- Nanoseconds, microseconds, and milliseconds respectively. singlewide ------------------------- An IP Module printed circuit board (3.9 by 1.8 inches). Each module has two 50-pin connectors. VHDL ----------------------------- Very high-speed integrated circuit Hardware Description Language. Copyright 2004 GLOSSARY-1 VMESC5 HW Reference Manual...
  • Page 65 GLOSSARY This page intentionally left blank. Copyright 2004 GLOSSARY-2 VMESC5 HW Reference Manual...
  • Page 66 INDEX...

  • Page 68: Index

    ........3-1 required tools ........ 3-1 steps ..........3-2 singlewide....2-1, 2-2, B-1, D-1 removing ........3-2 slave card .......... B-1 Interrupt Engine ......2-7, 2-9 specifications interrupt requests..2-2, B-4, B-6, D-3 Copyright 2004 INDEX-1 VMESC5 HW Reference Manual...
  • Page 69 INDEX electrical........A-1 environmental .......A-1 test equipment configuration .... C-1 mechanical ........A-1 TESTIP ......B-6, C-1-C-9 strobe signals......2-1, 3-7 transfers .......2-1, 2-2, 2-3, 2-7 VHDL ..........2-8 Copyright 2000 INDEX-2 VMESC5 HW Reference Manual...

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