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Curtiss-Wright SCRAMNet+ SC150 VME6U Hardware Reference Manual

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SC150 VME6U
Hardware Reference
Document No. D-T-MR-VME6U###-A-0-AA

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Summary of Contents for Curtiss-Wright SCRAMNet+ SC150 VME6U

  • Page 1 SC150 VME6U Hardware Reference Document No. D-T-MR-VME6U###-A-0-AA...
  • Page 3 Curtiss-Wright Controls, Inc. reserves the right to make changes without notice. Curtiss-Wright Controls, Inc. makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
  • Page 4 This product is intended for use in industrial, laboratory or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.
  • Page 5 TABLE OF CONTENTS 1. INTRODUCTION............................1-1 1.1 How To Use This Manual ......................1-1 1.1.1 Purpose ........................1-1 1.1.2 Scope ........................1-1 1.1.3 Style Conventions....................1-1 1.2 Related Information........................1-1 1.3 Quality Assurance ........................1-2 1.4 Technical Support........................1-2 1.5 Ordering Process ........................1-3 2.
  • Page 6 TABLE OF CONTENTS 3.8 Options ............................. 3-4 3.8.1 Electronic Bypass Switch ..................3-4 3.8.2 Quad Switch ......................3-4 3.8.3 Cabinet Kit......................3-5 4. INSTALLATION............................4-1 4.1 Installation Procedures ......................4-1 4.2 Unpack the Board ........................4-2 4.3 Visually Inspect the Board ....................... 4-2 4.3.1 SIMM Connections....................
  • Page 7 TABLE OF CONTENTS 5.10.3 Presetting Values ....................5-17 5.11 Modes of Operation......................5-17 5.11.1 Data Filter ......................5-17 5.11.2 HIPRO Mode..................... 5-19 5.11.3 Loopback Modes ....................5-20 5.11.4 Node Insert Mode ....................5-25 5.11.5 VME Holdoff Mode ..................5-26 5.11.6 Write-Me-Last Mode ..................5-28 5.12 Quad Switch .........................

  • Page 8: Table Of Contents

    TABLE OF CONTENTS FIGURES Figure 2-1 Functional Diagram ........................2-2 Figure 2-2 ACR/Memory Access........................2-5 Figure 2-3 Outgoing Interrupt ........................2-7 Figure 2-4 Incoming Interrupt........................2-7 Figure 3-1 VME6U Board, Version B1......................3-2 Figure 3-2 Node Inclusion and Isolation ......................3-5 Figure 4-1 Fiber-optic Media Card (Bottom view) ..................
  • Page 9 TABLE OF CONTENTS TABLES Table 4-1 Setting the CSR Physical Address ....................4-5 Table 4-2 Example of a CSR Address......................4-5 Table 4-3 Setting the Resolution Switch ......................4-6 Table 4-4 Trigger Pin Connections (J7) ......................4-8 Table 4-5 External Trigger Actions........................ 4-8 Table 4-6 Auxiliary Connection Pinout......................
  • Page 10 TABLE OF CONTENTS This page intentionally left blank Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 11 1.1 How To Use This Manual 1.1.1 Purpose This document is a reference manual for the SCRAMNet+ SC150 VME6U host interface board. It provides a physical and functional description of the SCRAMNet+ SC150 VME6U board. The manual describes how to unpack, set up, install, and operate the hardware.
  • Page 12 INTRODUCTION 1.3 Quality Assurance Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Our quality commitment begins with product concept, and continues after receipt of the purchased product.
  • Page 13 World Wide Web address: www.cwcembedded.com 1.5 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. •...
  • Page 14 INTRODUCTION This page intentionally left blank Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 15 2. SCRAMNET NETWORK 2.1 Overview The SCRAMNet Network is a real-time communications network, based on a replicated, shared-memory concept. Each host processor on the network has access to its own local copy of shared memory that is updated over a high-speed, serial-ring network. The network is optimized for the high-speed transfer of data among multiple, real-time computers that are all solving portions of the same real-time problem.

  • Page 16: Figure 2-1 Functional Diagram

    SCRAMNET NETWORK Figure 2-1 Functional Diagram Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 17 SCRAMNET NETWORK cases, the mode of operation is set during initialization and remains unchanged during run time. The CSRs are described in detail in Section 5. 2.2.3 Virtual Paging All SCRAMNet nodes use the same 8 MB shared memory map. This feature permits different SCRAMNet boards with 4 MB of shared memory or less to be paged into different sections of the 8 MB memory map.
  • Page 18 SCRAMNET NETWORK 2.4 Network Ring The SCRAMNet Network is a ring topology network. Data is transmitted at a rate of 150 Mbits/s over dual fiber-optic cables. The two lines together produce the incoming data clock. Due to the network speed and message slot size, the network can accommodate over 1,800,000 message slots passing by each node every second.

  • Page 19: Figure 2-2 Acr/Memory Access

    SCRAMNET NETWORK CSR0[4] Shared Memory Byte 0 Byte 1 Byte 2 Byte 3 Host READ/WRITE request to a specific 32-bit memory address ACR Memory Byte 0 LEGEND DOES NOT PHYSICAL REALLY EXIST MEMORY CHIP Figure 2-2 ACR/Memory Access , host CPU READ/WRITE operations are channeled to either SCRAMNet Figure 2-2 memory or to the ACR.
  • Page 20 SCRAMNET NETWORK 2.6.1 Network Interrupt WRITEs FOREIGN MESSAGE The node can receive a message from another node with the interrupt bit set. If Receive Interrupt Enable ACR[0] and Interrupt Mask Match Enable CSR0[5] are enabled, the data is written to shared memory and the address is placed on the Interrupt FIFO. NATIVE MESSAGE If the message received was originated by the node, and Write Own Slot Enable CSR2[9] and Enable Interrupt on Own Slot CSR2[10] are enabled, the host has authorized a Self-...

  • Page 21: Figure 2-3 Outgoing Interrupt

    SCRAMNET NETWORK OUTGOING Address A22 - A0 D31 - D0 Data SHARED MEMORY D31 - D0 A22 - A0 Address Data D31 - D0 Interrupt Bit RING NETWORK RING LOGIC Figure 2-3 Outgoing Interrupt INCOMING INTERRUPT INTERRUPT FIFO A16 - A0 A22 - A16 SHARED MEMORY CSR 4...
  • Page 22 SCRAMNET NETWORK Error conditions are listed in CSR1 and may be masked by setting the corresponding bit in CSR9. If the Mask bits in CSR9 are all set to ‘1,’ any error will generate an interrupt. Otherwise, only errors with a ‘1’ in the appropriate Mask bit will generate an interrupt. A Network Interrupt vector may be placed in CSR7 to identify a Network Error Interrupt Service Routine.
  • Page 23 SCRAMNET NETWORK 2.9 LED Status Indicators INSERT The green Insert LED is ON when the node is inserted into the SCRAMNet Network ring. This is the result of setting CSR 0[15]. MESSAGE WAITING The green Message Waiting LED lights when a message is placed in the Transmit FIFO. CARRIER DETECT The green carrier detect LED is ON when there is a valid pair of transmit lights from the previous SCRAMNet...
  • Page 24 SCRAMNET NETWORK 2.10.2 High Performance (HIPRO) Mode HIPRO provides an efficient means to transmit 8-bit and 16-bit data transactions as one 32-bit network WRITE. It also provides a means of keeping 32-bit data from becoming fractured. EXAMPLE #1: A floating-point length numeric sent in 8-bit or 16-bit pieces may not be accurately re- assembled at the destination.
  • Page 25 SCRAMNET NETWORK In some system designs, and on some computer buses, it is not desirable or effective to have the WRITE cycle lengthened to match network throughput—even at the expense of possible data loss across the network. In this case this option may be disabled by setting CSR8[1] ON.
  • Page 26 SCRAMNET NETWORK Write-Me-Last Mode 2.10.5 The Write-Me-Last mode of operation allows the originating node to be the last node in the ring to have the data deposited to its memory. This can be useful for synchronization. This means that when the host performs a WRITE to the SCRAMNet shared memory, this data is not immediately written to the host node’s memory, but is first sent to the other nodes on the network.
  • Page 27 3. PRODUCT OVERVIEW 3.1 Overview SCRAMNet (Shared Common Random Access Memory Network) is a communications network geared toward real-time applications, and based on a replicated, shared-memory concept. The SCRAMNet VME6U host interface node board is backwards compatible with the original SCRAMNet Classic product. The SCRAMNet Classic Gold Ring communication protocol is compatible with the SCRAMNet+ Platinum protocol, but not with BURST PLUS or PLATINUM PLUS.

  • Page 28: Figure 3-1 Vme6U Board, Version B1

    PRODUCT OVERVIEW Figure 3-1 VME6U Board, Version B1 3.1.3 VME6U Board Features • SIMM memory upgrade option • General purpose counter • Error-interrupt mask • Dynamic shared-memory addressing • Switch-selectable CSR address selector • Virtual paging for shared memory (CSR selectable) •...
  • Page 29 PRODUCT OVERVIEW 3.3 Addressing Compatibility 3.3.1 Memory The shared memory resident on the SCRAMNet VME6U host interface board must be located on either the A24 standard bus or the A32 extended bus. The address is CSR selectable. The memory address selected must be an address boundary that is a multiple of the shared-memory size, and must be loaded and enabled through the CSRs.
  • Page 30 PRODUCT OVERVIEW 3.7 Utility Software 3.7.1 SCRAMNet Diagnostics The SCRAMNet Network Hardware Diagnostics are designed to test the functionality of the hardware. This suite of tests will detect whether it is testing a Classic board or a SCRAMNet-LX/SCRAMNet board and adjust the test menus accordingly. 3.7.2 EEPROM Initialization (EPI) The EEPROM Initialization program is a SCRAMNet utility used to simplify...

  • Page 31: Figure 3-2 Node Inclusion And Isolation

    PRODUCT OVERVIEW As a repeater, each Quad Switch port converts optical signals to electrical signals. These signals are re-synchronized and re-transmitted. This allows each connection to the Quad Switch to be the maximum length for the type of media selected. The Quad Switch can also perform media conversion.
  • Page 32 PRODUCT OVERVIEW This page intentionally left blank Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 33 4. INSTALLATION 4.1 Installation Procedures Installation of the VME6U board includes the following: • Unpack the board • Visually inspect the board Check SIMM connection(s), if any Check Media Card connection • Externally configure the board Set/verify EEPROM WRITE jumper (J303) Set/verify EEPROM READ jumper (J304) Set CSR Address switches (S1-S7) Set bus resolution switch (S8)

  • Page 34: Figure 4-1 Fiber-Optic Media Card (Bottom View)

    Network node consists of a single board as shown in Figure 4-2. If the optional memory upgrade was ordered, it will come already installed. In the event that any shipping damage has occurred, notify Curtiss-Wright Controls, Inc. or your supplier immediately.

  • Page 35: Figure 4-2 Vme6U Layout

    INSTALLATION Figure 4-2 VME6U Layout Copyright 2007 VME6U HARDWARE REFERENCE...

  • Page 36: Figure 4-3 Eeprom Write (J303)

    INSTALLATION This fiber-optic card has two power options; host power and standby or battery power. Jumper J2 in Figure 4-1 controls the power options. Pins 1 and 2 are for normal host power, and pins 2 and 3 are for standby power. The standby or battery power requires external connection via the auxiliary connection on the cabinet kit board or the host interface board if no cabinet kit is installed.

  • Page 37: Table 4-1 Setting The Csr Physical Address

    INSTALLATION 4.4.2 CSR Address Switches The CSR addressing for the VME6U bus can be short (16-bit), standard (24-bit) or extended (32-bit). The SCRAMNet CSRs must be configured on a contiguous 64-byte boundary. Set the base address for the Control/Status Registers using S1 through S7 as indicated in Table 4-1 and Figure 4-2.

  • Page 38: Figure 4-5 Software Compatibility (J2)

    INSTALLATION 4.4.3 Resolution Bus Switch (S8) Switch S8 is the Resolution Bus switch. Set switch S8 to the desired value as indicated in Table 4-3 and Figure 4-2. Resolution bus switch factory default setting: 0x6-CSR A16 MEMORY A24 Table 4-3 Setting the Resolution Switch Memory Value 4.4.4 Software Compatibility (SW_CMPT) (J2)

  • Page 39: Figure 4-7 Install Simms

    INSTALLATION OPTIONS Low density, 512 KB SIMMs 1 = 512 KB (SIMM 1) 2 = 1 MB (SIMM 1 and 2) 4 = 2 MB (SIMMs 1 through 4) High density, 2 MB SIMMs 1 = 2 MB (SIMM 1) 2 = 4 MB (SIMM 1 and 2) 4 = 8 MB (SIMMs 1 through 4) Figure 4-7 Install SIMMS...

  • Page 40: Figure 4-9 Ground (J6)

    INSTALLATION 4.4.7 Ground Jumper (J6) The Chassis/Signal Ground is a user option (Figure 4-9). Factory default setting: CHASSIS GROUND ( Figure 4-9 Ground (J6) 4.4.8 External Trigger Connections The SCRAMNet board generates two external triggers. Activating the triggers for any shared-memory location will cause an external trigger to be generated when the shared- memory location is accessed (Figure 4-10, Table 4-4, and Table 4-5).
  • Page 41 INSTALLATION 4.5 Install the Board Once all the switch settings have been made, the board is ready to be installed so the CSRs may be accessed to continue configuration. CAUTION: Make certain that the power to the host computer is OFF. The SCRAMNet Network node requires one board slot in the backplane.

  • Page 42: Figure 4-11 Fiber-Optic St Connector

    INSTALLATION 4.6.2 Fiber-Optic Configuration The basic SCRAMNet Network communication architecture consists of SCRAMNet boards tied together by paired sets of fiber-optic cable in a ring configuration. The maximum recommended distance between each node of the network using this configuration is approximately 300 meters. Maximum node separation using long-link fiber is 3,500 meters.

  • Page 43: Figure 4-12 Fiber-Optic Connections

    INSTALLATION 4.6.5 Fiber-optic Connection The fiber-optic cable transmitter pairs of the up-stream node are connected to the receiver pair of the down-stream node. Data flows from the transmitter pair of one node to the receiver pair of the next node as described in Figure 4-12. Node Node Node...

  • Page 44: Figure 4-13 Inserted State (Power On)

    INSTALLATION 4.7 Install Fiber Optic Bypass Switch (Optional) Make Fiber Optic Bypass Switch connections as shown in Figure 4-13 and Figure 4-14. Figure 4-13 Inserted State (Power On) Figure 4-14 Bypass State (Power Off) 4.7.1 Auxiliary Connection The optional Fiber Optic Bypass switch is used to provide an uninterrupted fiber-optic path when the node is not powered up.

  • Page 45: Figure 4-15 Auxiliary Connection

    PROM programmers. An EEPROM initialization program is included in the Core Software Package offered by Curtiss-Wright Controls, Inc. The initialization of the SCRAMNet node from a cold boot is determined by the settings of the EEPROM as indicated in Table 4-7.

  • Page 46: Table 4-8 Eeprom Initialization

    INSTALLATION Table 4-8 EEPROM Initialization SCRAMNet+ Registers CSR0 - 0 CSR1 - READ Only (Errors) CSR2 - 0xC040 (BURST Mode) CSR3 - Node ID (0 - 255) CSR4 - 0 (READ Only) CSR5 - 0x0010 READ Only (WRITE Network Time-out to shadow register) CSR6 - 0 (Data Vector) CSR7 - 0 (Error Vector) CSR8 - 0x0800 (Mech Switch Override)

  • Page 47: Table 4-9 Big Endian - Little Endian Comparisons

    INSTALLATION 4.8.3 Memory MEMORY ADDRESSING The memory base address is software configurable anywhere through the A24 and A32 address space. If the shared-memory and CSR addresses should overlap, the CSR s will be decoded making the overlapped memory inaccessible. The Least Significant Word (LSW) of shared-memory address is in CSR10[15:12]. The Most Significant Word (MSW) of shared-memory address is contained in CSR11[15:0].
  • Page 48 10400000 or 10600000 are on 2 MB boundaries. 4.10.2 Customer Support If the system does not boot correctly, reseat the board and double-check cable connections. If problems persist, call Curtiss-Wright Controls, Inc. Customer Support at (937) 252-5601 for assistance. Please be prepared to supply the following information:...
  • Page 49 5. OPERATION 5.1 Overview The SCRAMNet Network is a shared-memory system. Every computer on the network has a constantly updated local copy of all global data that is passed to all the network computers. The network protocol is implemented in the SCRAMNet hardware and therefore no software overhead is required to retrieve this information from the network.

  • Page 50: Figure 5-1 Memory Sharing With Virtual Paging

    OPERATION NOTE: Virtual paging does not affect host access to shared memory. Virtual Paging only changes the network address. The HOST SPECIFIC logic always sees the base address of SCRAMNet shared memory as zero. Network Address Node 1 Node 2 Node 3 Node 4 Node 5...
  • Page 51 OPERATION 5.2.2 Memory Considerations When using SCRAMNet shared-memory, consider the following: PROGRAM AND DATA LIMITATIONS Limitations on application program size and data variable size for a host computer system also apply to applications that use SCRAMNet memory because it becomes part of the host system.

  • Page 52: Table 5-1 Scramnet+ Message Contents

    OPERATION NOTE: All SCRAMNet nodes in the fiber-optic network ring must be powered on unless Fiber Optic Bypass Switches or Quad Switches are installed. 5.4 Basic Send/Receive Configuration The following conditions must exist in order to have basic send and receive capability on the network: •...
  • Page 53 OPERATION This 8-bit field increments by one as a message passes through each network node. If the age ever exceeds 256 (the maximum number of nodes on the network), the message is removed from the network. CONTROL BITS RES - Reserved. INT - When this bit is set it signals an Interrupt Message.
  • Page 54 OPERATION The PLUS mode allows variable-length message packets in which sequentially addressed data in the Transmit FIFO is transferred as a block in a single packet. Both BURST modes are open loop, non-error-corrected modes of operation. The node appends 4-byte data values with sequential addresses until the maximum of 256 or 1024 bytes is reached, a non-sequential address is detected, the Transmit FIFO is empty, or a transmit interrupt event is detected.
  • Page 55 OPERATION nodes in the system, and add a propagation delay of 5 ns/meter multiplied by the total message path of the ring in meters. DATA TRANSFER While the SCRAMNet Network appears as a shared-memory system, it is still a data network.

  • Page 56: Table 5-2 Acr Functions

    OPERATION 5.6 Auxiliary Control RAM The ACR is an 8-bit register. However, only ACR[4:0] are implemented. ACR[7:5] are not defined. When ACR Enable CSR0[4] is set, shared memory is not accessible by the host, and the ACR byte is viewed as the least significant byte of every shared-memory four-byte address.

  • Page 57: Table 5-3 Interrupt Controls

    OPERATION 5.7 Interrupt Controls SCRAMNet allows a processor to receive interrupts from and/or transmit interrupts to any other processors on the network, including the originating processor. Table 5-3 indicates the various sources for interrupt control. 5.7.1 Interrupt Options Table 5-3 Interrupt Controls Condition Register Description...
  • Page 58 OPERATION SEND/RECEIVE WITH INTERRUPTS • Set CSR0 to ‘0x0010’ to enable the Auxiliary Control RAM (ACR). • Clear the SCRAMNet ACR by writing zeros to the entire address range. • Set the SCRAMNet ACR memory locations designated to receive and/or transmit interrupts.

  • Page 59: Figure 5-2 Transmit Interrupt Logic

    OPERATION HOST TRANSMIT ENABLE WRITE CSR0[1] MUST BE ACTIVE CSR0[9] OVERRIDE TIE ACR[1] CSR0[8] NETWORK INTERRUPT ENABLE TRANSMIT TRANSMIT INTERRUPT SLOT TO NON-INTERRUPT NETWORK SLOT TO NETWORK Figure 5-2 Transmit Interrupt Logic Copyright 2007 5-11 VME6U HARDWARE REFERENCE...
  • Page 60 OPERATION The host issues a WRITE to SCRAMNet shared memory. If Override TIE CSR0[9] or ACR TIE ACR[1] is set and Network Interrupt Enable CSR0[8] is set, then the interrupt message is transmitted (INT = 1). Otherwise, the message is transmitted without the interrupt bit set (INT = 0).

  • Page 61: Figure 5-3 Receive Interrupt Logic

    OPERATION CSR1 NETWORK MESSAGE PACKET ERROR CSR0[7] CSR2[9] WRITE INT ON NATIVE OWN SLOT ERRORS CSR2[10] ENB INT ON Rx IN SLOT CSR8[10] RECEIVE OVERRIDE INTERRUPT MESSAGE CSR0[6] CSR9 OVERRIDE ERROR MASK BIT ACR[0] CSR0[5] MASK INTERRUPT TO MATCH HOST CSR0[3] PLACE HOST...

  • Page 62: Table 5-4 Interrupt Error/Status Conditions

    OPERATION 5.8.2 Network Error The second interrupt condition is designed to intercept network errors. CSR1 contains the following error conditions that may be masked by CSR9: Table 5-4 Interrupt Error/Status Conditions Interrupt Transmit FIFO Full Transmit FIFO Not Empty ⅞ Transmit FIFO Full (Not masked for errors)
  • Page 63 OPERATION 5.8.3 Interrupt Handling The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant seven bits of the 23-bit SCRAMNet interrupt address and CSR4 contains the remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion of memory).

  • Page 64: Table 5-5 General Purpose Counter/Timer Modes

    OPERATION EXAMPLE 1 – MEASURE TRANSACTION TIME Select a shared-memory address in node A and enable trigger 1 by setting ACR[2]. Select the same memory address in node B and enable trigger 2 by setting ACR[3]. Connect a wire from TRIG1 to an oscilloscope. Connect a wire from TRIG2 to the oscilloscope. Initiate a HOST WRITE to the node A memory address.

  • Page 65: Table 5-6 Data Filter Options

    OPERATION 5.10.2 Rollover/Reset A rollover/reset can generate an interrupt by setting Interrupt On General Purpose Counter/Timer Overflow Mask CSR9[12]. When this bit is set, an interrupt is generated to the host system whenever the counter register (CSR 13) rolls over or overflows. Interrupt On Errors mode CSR0[7] must be enabled in order for this to work properly.

  • Page 66: Figure 5-4 Data Filter Logic

    OPERATION DATA FILTER LOGIC NOTHING WRITE HOST DATUM SAME DATUM WRITE TO MEMORY READ SHARED MEMORY NETWORK RING NETWORK RING NETWORK LOGIC Figure 5-4 Data Filter Logic Copyright 2007 5-18 VME6U HARDWARE REFERENCE...
  • Page 67 OPERATION 5.11.2 HIPRO Mode WRITE The SCRAMNet network message is based on 32-bit longword data. If a host processor is only capable of 8- or 16-bit data transactions, then the SCRAMNet bandwidth is quartered or halved, respectively. For each 32-bit data transaction from the host, two 16- bit data transactions, or four 8-bit transactions will occur on the bus each requiring a SCRAMNet network WRITE.
  • Page 68 OPERATION 5.11.3 Loopback Modes Each node has a Monitor and Bypass mode, Wire Loopback mode, Mechanical Switch Loopback mode, and a Fiber-optic Loopback mode. These modes are used to check the node’s performance and to test transmit/receive circuitry. The loopback mode routes data that would normally be transmitted on to the network directly back to the node from different points.

  • Page 69: Figure 5-5 Monitor And Bypass Mode

    OPERATION MONITOR AND BYPASS MODE This mode permits the node to receive data only. Network data is not re-transmitted. Table 5-7 Monitor and Bypass Mode States State Register Setting Receive Enable CSR0[0] Transmit Enable CSR0[1] DON’T CARE Insert Enable CSR0[15] Enable Wire Loopback CSR2[7] Fiber Optic Bypass Switch...

  • Page 70: Figure 5-6 Wire Loopback Mode

    OPERATION WIRE LOOPBACK MODE The Wire loopback permits testing of the internal circuitry and needs no manual external modifications to work. In this mode, the transmitted signal does not leave the board. Table 5-8 Wire Loopback Mode States State Register Setting Receive Enable CSR0[0]...

  • Page 71: Figure 5-7 Mechanical Switch Loopback Mode

    OPERATION MECHANICAL SWITCH LOOPBACK MODE This mode permits testing of all circuitry up to and including a major portion of the Media Card. Table 5-9 Mechanical Switch Loopback Mode States State Register Setting Receive Enable CSR0[0] Transmit Enable CSR0[1] Insert Enable CSR0[1]5 Enable Wire Loopback CSR2[7]...

  • Page 72: Figure 5-8 Fiber-Optic Loopback Mode

    OPERATION FIBER-OPTIC LOOPBACK When this mode is invoked, the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network. Table 5-10 Fiber-optic Loopback Mode States State Register Setting Receive Enable...

  • Page 73: Table 5-11 Node Insert Mode

    OPERATION The optional Fiber Optic Bypass Switch must be installed for this to work. However, in the absence of the Fiber Optic Bypass Switch, fiber-optic cables could be run from the node’s transmitter output connectors to the receiver input connectors. This configuration, with Insert Node enabled, constitutes a Fiber-optic Loopback mode for stand-alone testing.

  • Page 74: Figure 5-9 Insert Mode

    OPERATION Fiber Optic Bypass Switch (Optional) Media Card Conv Conv MECHSWITCH Internal PLL and Data Recovery INSERT ENABLE WIRE LOOPBACK ENABLE ENABLE Figure 5-9 Insert Mode 5.11.5 VME Holdoff Mode To enable VME Holdoff, set CSR8[1] OFF. The VME Holdoff feature automatically slows down CPU data WRITEs to the SCRAMNet memory when the Transmit FIFO becomes full.
  • Page 75 OPERATION Figure 5-10 Quad Switch Copyright 2007 5-27 VME6U HARDWARE REFERENCE...
  • Page 76 OPERATION In the event that the Transmit FIFO becomes full, the hardware will automatically extend the next VME WRITE cycle until the Transmit FIFO empties at least one message. This prevents the loss of any data and is transparent to the user. 5.11.6 Write-Me-Last Mode The Write-Me-Last mode of operation allows the originating node to be the last node in the ring to have the data deposited to its memory.

  • Page 77: Figure 5-11 Interrupt Service Routine

    OPERATION CSR0 IMME and HIE must be set in order to set up interrupts. CSR1 Bits 0-15 contain various error and status conditions. Interrupts are re-armed whenever any value is written to CSR1. CSR4 Bits 0-15 contain the interrupt address bits A0-A15. CSR5 Bits 0-6 contain the interrupt address bits A22-A16.
  • Page 78 OPERATION This page intentionally left blank Copyright 2007 5-30 VME6U HARDWARE REFERENCE...
  • Page 79 A. A - SPECIFICATIONS APPENDIX A SPECIFICATIONS TABLE OF CONTENTS A.1 Hardware Specifications ........................A-1 A.2 Part Number ............................A-2 A.3 Board Dimensions..........................A-3 A.4 VMEbus Voltage Specification......................A-4 A.5 J8 Connector Pinout ..........................A-5 A.6 P2 SCRAMNet+ Pinout (Row A) ......................A-6 A.7 P2 SCRAMNet+ Pinout (Row C) ......................
  • Page 81 SPECIFICATIONS A.1 Hardware Specifications Hardware Compatibility:............VMEbus ANSI/IEEE std. P1014-1987 VMEbus Manufacturers Group Rev. C.3 Slave device Physical Dimensions: VME6U Card ............6.299" x 9.187" 6U Eurocard, one slot Weight: VME6U Card ............0.6175 lbs (W/O SIMMs and Media Card, W/face plate) Media Card, Fiber Optic...........
  • Page 82 SPECIFICATIONS A.2 Part Number The VME6U adapter part number is in the form: H-AS-D6VMEL2M-00 where: CODE DEFINITION Hardware Top Level Assembly Standard SCRAMNet+ 6VME 6U 16-BIT VME Memory (bytes) = 04 K = 128 K = 512 K = 2 M (LOW DENSITY) = 2 M (HIGH DENSITY) = 4 M = 8 M...
  • Page 83 SPECIFICATIONS A.3 Board Dimensions Figure A-1 VME6U Dimensions Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 84 SPECIFICATIONS A.4 VMEbus Voltage Specification VMEbus Voltage Specification Mnemonic Description Allowed Ripple/Noise Variation Below 10 MHz +5 V +5 V dc +0.25 V/-0.125 V 50 Mv +12 V * +12 dc power +0.60 V/-0.36 V 50 Mv -12 V * -12 dc power -0.60 V/+0.36 V 50 Mv...
  • Page 85 SPECIFICATIONS A.5 J8 Connector Pinout The Media Card is removed, and an adapter is installed connecting J302 and J8. This results in transferring the signals normally going to the Media Card to the J5 connector. When the four 9-pin headers are installed on J5, the signals pass out the P2 connector. P2A_MECHSW P2A_TX0 P2A_TX0...
  • Page 86 SPECIFICATIONS A.6 P2 SCRAMNet+ Pinout (Row A) NOTE: Row A is active only when the J5 jumpers are installed for the P2 Cabinet Kit. P2_E_PRE P2_E_CS P2_E_DIN P2_SP1 P2_E_DOUT P2_SP2 P2_E_CK P2_RX0 P2_RX1 P2_S_CLK P2_TRIGGER P2_S_DATA P2_S_DIR P2_F_RELAY P2_TX1 P2_TX0 P2_MECHSW CAB_VDD P2_VDD_A31...
  • Page 87 SPECIFICATIONS A.7 P2 SCRAMNet+ Pinout (Row C) NOTE: Row B is not shown. P2_GND_C1 P2_GND_C3 P2_GND_C5 P2_SP1 P2_GND_C7 P2_SP2 P2_GND_C9 P2_RX0 P2_RX1 CAB_GND P2_S_CLK P2_TRIGGER P2_S_DATA CAB_VDD P2_S_DIR P2_VDD_C23 P2_TX1 P2_TX0 P2_VDD_C29 P2_VDD_C31 NOTE: Unlabled pins are User Defined Figure A-4 P2 SCRAMNet+ Pinout - Row Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 88 SPECIFICATIONS A.7.1 Fiber Optic Bypass Switch Figure A-5 Fiber Optic Bypass Switch Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 89 SPECIFICATIONS Figure A-6 Housing Dimensions Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 90 SPECIFICATIONS This page intentionally left blank Copyright 2007 A-10 VME6U HARDWARE REFERENCE...
  • Page 91 B. B - CSR DESCRIPTIONS APPENDIX B CSR DESCRIPTIONS TABLE OF CONTENTS Table B-1 CSR0 - General SCRAMNet Enable and Reset ..................B-2 Table B-2 CSR1 - Error Indicators ..........................B-5 Table B-3 CSR2 - Node Control...........................B-7 Table B-4 CSR3 - Node Information ..........................B-9 Table B-5 CSR4 - Interrupt Address (LSP) ........................B-9 Table B-6 CSR5 - Interrupt Address and Status (MSP)....................B-9 Table B-7 CSR6 - Interrupt Vector (Memory Update) ....................B-10...
  • Page 93 CSR DESCRIPTIONS B.1 Description This section describes each Control/Status Register and the function of each bit. The name of each bit is indicative of its set state. The registers are described using bit 0 as the Least Significant Bit (LSB). For example: Inserting 0xA7C3 in a 16-bit register would set bits 0, 1, 6, 7, 8, 9, 10, 13, and 15 ON.
  • Page 94 CSR DESCRIPTIONS Table B-1 CSR0 Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Network Communications Mode - Bit 0 controls the receive enable, and Bit 1 controls the transmit enable. 00 None - In this mode, all communications between the node shared memory and the network is inhibited.
  • Page 95 CSR DESCRIPTIONS Table B-1 CSR0 (Continued) Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Auxiliary Control RAM Enable - When this bit is set, the ACR bytes are swapped in place of the corresponding least-significant byte of every four-byte word in SCRAMNet memory.
  • Page 96 CSR DESCRIPTIONS Table B-1 CSR0 (Continued) Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Enable Transmit Data Filter - When clear, the entire address space is not filtered and the node is capable of transmitting all messages written to the node shared memory by the host on the network.
  • Page 97 CSR DESCRIPTIONS Table B-2 CSR1 Bits Error Indicators (READ Only with WRITE/RESET for interrupts) Reading CSR1 will reset the latched error conditions by clearing bits 0,2,4,6,7,8,9,10,11,12,13. Transmit FIFO Full (Latched) - When this bit is set, the Transmit-FIFO-Full condition exists. This occurs when there is more data coming from the host to the network than the network can absorb.
  • Page 98 CSR DESCRIPTIONS Table B-2 CSR1 (continued) Bits Error Indicators (READ Only with WRITE/RESET for interrupts) Redundant Transmit/Receive Fault (Latched) - This bit is set if the currently selected optional redundant transceiver has faulted and reverted to the other link. The default value is ‘0’ General Purpose Counter/Timer Overflow (Latched) - This bit toggles a 16-bit counter/timer.
  • Page 99 CSR DESCRIPTIONS Table B-3 CSR2 Bits Node Control (READ/WRITE) These bits are related to lines connected through the MUX control port and are available to the host interface. They are not required to connect to anything Disable Fiber Optic Loopback - When this bit is ‘0’ (power up default), the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network.
  • Page 100 CSR DESCRIPTIONS Table B-3 CSR2 (continued) Bits Node Control (READ/WRITE) Variable Length Messages on Network - When ON, this bit enables variable length messages. It is used in conjunction with CSR2, bits 11, 14 and 15 to enable PLUS mode communication protocols (see below).
  • Page 101 CSR DESCRIPTIONS Table B-4 CSR3 Bits Node Information (READ ONLY) Node Number Count - These bits represent the total number of SCRAMNet nodes on the network. This value is dynamically determined by the hardware. The value ranges from 0 to 255 depending upon the number of nodes actually on the network.
  • Page 102 CSR DESCRIPTIONS Table B-7 CSR6 Bits Interrupt Vector (Memory Update) (READ/WRITE) Interrupt Vector - This host specific register stores the VMEbus interrupt vector for the interrupt generated by a Memory Update. This register must be pre-loaded with the vector before interrupt processing can occur. * 15-8 Reserved.
  • Page 103 CSR DESCRIPTIONS Table B-9 CSR8 Bits General SCRAMNet+ Extended Control Register ID Multiplex - When set to 1, CSR3 contains the T_AGE and RXID fields. Disable Holdoff - When set, this bit disables the HOLDOFF feature. These bits are used for programming the EEPROM. CSR Reset - Setting this bit will cause bus errors.
  • Page 104 CSR DESCRIPTIONS Table B-10 CSR9 Bits SCRAMNet Interrupt On-Error Mask* Transmit FIFO Full Mask Transmit FIFO not Empty Mask Transmit FIFO 7/8 Full Mask Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output. Interrupt FIFO Full Mask Protocol Violation Mask Carrier Detect Fail Mask Bad Message Mask...
  • Page 105 CSR DESCRIPTIONS Table B-11 CSR10 Bits SCRAMNet+ Replicated Shared Memory Address (LSW) SMA_ENABLE Shared Memory Address Enable. This bit enables the on-ASIC comparator for shared-memory access. 11-1 Always zero SMA12 SMA13 Shared Memory Address SMA14 SMA15 Table B-12 CSR11 Bits SCRAMNet+ Replicated Shared Memory Address (MSW) SMA16 SMA17...
  • Page 106 CSR DESCRIPTIONS Table B-13 CSR12 Bits SCRAMNet Virtual Paging Register Virtual Paging Enable. When ON, this bit enables Virtual Paging. Always zero VP_A12 VP_A13 VP_A14 VP_A15 VP_A16 Virtual Page number. The significance of this register is dependent on the VP_A17 memory size.
  • Page 107 CSR DESCRIPTIONS Table B-14 CSR13 Bits General Purpose Counter/Timer RD_COUNT[0] RD_COUNT[1] RD_COUNT[2] RD_COUNT[3] RD_COUNT[4] RD_COUNT[5] RD_COUNT[6] This is a General Purpose Counter/Timer register. It can be used to RD_COUNT[7] count trigger 1 and 2 events, count errors, or other events as RD_COUNT[8] programmed by CSR9, bits 13 and 14.
  • Page 108 CSR DESCRIPTIONS Table B-15 CSR14 Bits Reserved 15-0 Not Used Table B-16 CSR15 Bits VME Interrupt Priority Level (IRQ) External Control Status Register Not Used This is a 7-bit wide, host-specific, READ/WRITE register that holds the VME Interrupt Priority Level (IRQ). Bits reflect the Interrupt Priority Level.
  • Page 109 CSR DESCRIPTIONS Table B-17 CSR16 Bits HIPRO READ Control Bits Register (External Control Status Register) This is a 2-bit wide, High Performance (HIPRO) READ Control Bits Register. Only bits 1 and 0 are valid. Bit 1 Bit 0 HIPRO READ enabled HIPRO READ ACR enabled Bit 0 is CSR enabled.
  • Page 110 CSR DESCRIPTIONS This page intentionally left blank Copyright 2007 B-18 VME6U HARDWARE REFERENCE...
  • Page 111 C. C - CSR SUMMARY APPENDIX C CSR SUMMARY TABLE OF CONTENTS C.1 CSR0 - General SCRAMNet+ Enable and Reset ..................C-1 C.2 CSR1 - Error Indicators...........................C-2 C.3 CSR2 - Node Control ..........................C-3 C.4 CSR3 - Node Information ........................C-4 C.5 CSR4 - Interrupt Address (LSP)......................C-5 C.6 CSR5 - Interrupt Address (MSP) and Status (READ Only*) ..............C-6 C.7 CSR6 - Interrupt Vector (Memory Update) (R/W)..................C-6 C.8 CSR7 - Interrupt Vector (SCRAMNet+ Error) (R/W)................C-6...
  • Page 113 CSR SUMMARY C.1 CSR0 - General SCRAMNet Enable and Reset Function Name Receive Enable RX_ENB Transmit Enable TXEN Redundant TxRx Toggle Host Interrupt Enable Auxiliary Control RAM Enable ACRE Interrupt on Memory Mask Match Enable IMME Override RIE Flag Interrupt on Errors Network Interrupt Enable Override TIE Flag Enable Tx Data Filter...
  • Page 114 CSR SUMMARY C.2 CSR1 - Error Indicators Function Name Transmit FIFO Full TXFF Transmit FIFO Not Empty TXFNE Transmit FIFO 7/8 Full TXFAF (Always 0) Not Used Interrupt FIFO Full Protocol Violation Carrier Detect Failure Bad Message Receiver Overflow Transmit Retry TXRTY Transmit Retry Time-out Redundant TxRx Fault...
  • Page 115 CSR SUMMARY C.3 CSR2 - Node Control Function Name Available to Host Disable Fiber Optics Loopback FO_DIS Enable Wire Loopback EN_WR_LPB Disable Host to Memory Write DIS_H_M_WR Enable Write of Our Own Slot to Memory WOSEN Enable Interrupt on Receipt of Own Interrupt IOSEN Slot 1024 vs 256 variable size max (bytes)
  • Page 116 CSR SUMMARY C.4 CSR3 - Node Information Function Name Node Number Count* (Valid After a Transmission from the Node) NID0 NID1 NID2 Node ID Number* NID3 NID4 NID5 NID6 NID7 When ID_MUX bit CSR8[0] is set: Bits [7:0] are Transmit Age Bits [15:8] are Receive ID Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 117 CSR SUMMARY C.5 CSR4 - Interrupt Address (LSP) Function Name Always = 0 Always = 0 RFA2 RFA3 RFA4 RFA5 Interrupt FIFO Address Field (LSP) RFA6 RFA7 RFA8 RFA9 RFA10 RFA11 RFA12 RFA13 RFA14 RFA15 Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 118 CSR SUMMARY C.6 CSR5 - Interrupt Address (MSP) and Status (READ Only*) Function Name RFA16 RFA17 RFA18 Interrupt FIFO Address Field (MSP) RFA19 RFA20 RFA21 RFA22 13-7 Reserved Retry Bit in Interrupt FIFO (RF_RETRY) Interrupt FIFO Not Empty (~RX_F_E) Writing the Transmit Time-out value to CSR5 stores it in shadow memory. Do not set this value to ‘0’.
  • Page 119 CSR SUMMARY C.9 CSR8 - General SCRAMNet Extended Control Register Function Name 1 is CSR3=T_AGE & RXID fields ID_MUX Disable HOLDOFF feature DIS_HOLD Chip select to EEPROM CSR_CS0 Ext. Chip Select for AUX MICROWIRE CSR_CS1 peripheral MICROWIRE DOUT pin CSR_DOUT EEPROM program enable E_PRE CLK line to MICROWIRE port...
  • Page 120 CSR SUMMARY C.10 CSR9 - SCRAMNet Interrupt-On-Error Mask Function Name Transmit FIFO Full mask M_TX_F_F Transmit FIFO Not Empty mask M_TX_F_E Transmit FIFO 7/8 Full Mask M_TX_F_AF Internal 82 bit BIST shift register output BIST_STREAM Receiver FIFO Full Mask M_RX_F_F Protocol Violation mask M_PV Carrier Detect Fail mask...
  • Page 121 CSR SUMMARY C.11 CSR10 - SCRAMNet Shared Memory Address (LSW) Function Name Enable comparator for SM access SMA_ENABLE 11-1 Reserved SMA12 Shared Memory Address (LSW) SMA13 SMA14 SMA15 C.12 CSR11 - SCRAMNet Shared Memory Address (MSW) Function Name SMA16 SMA17 SMA18 SMA19 SMA20...
  • Page 122 CSR SUMMARY C.13 CSR12 - Virtual Paging Register (Refer to Chapter 5, Section 5.2.1, and Appendix B, page B-14) Function Name Enables Virtual Paging when set Always ‘0’ VP_A12 VP_A13 VP_A14 VP_A15 Virtual Page Number VP_A16 VP_A17 VP_A18 VP_A19 VP_A20 VP_A21 VP_A22 C.14 CSR13 - General Purpose Counter /Timer...
  • Page 123 CSR SUMMARY C.15 CSR14 - Reserved A 16-bit, READ Only Systran reserved register. C.16 CSR15 - VME Interrupt Priority Level (IRQ) A 7-bit, READ/WRITE register that holds the VME Interrupt Priority Level (IRQ). C.17 CSR16 - HIPRO Read Control Bits Register Function This is a 2-bit wide, High Performance (HIPRO) READ Control Bits Register.
  • Page 124 CSR SUMMARY This page intentionally left blank Copyright 2007 C-12 VME6U HARDWARE REFERENCE...
  • Page 125 D. D - CABINET KIT APPENDIX D CABINET KIT TABLE OF CONTENTS D.1 Options..............................D-1 D.2 Compact Cabinet Kit..........................D-1 D.3 Expanded Cabinet Kit ..........................D-2 D.4 Direct-attached P2 Cabinet Kit....................... D-3 FIGURES Figure D-1 Compact Cabinet Kit Connection....................D-1 Figure D-2 Expanded Cabinet Kit Connection .....................
  • Page 127 CABINET KIT D.1 Options Systran provides several cabinet kit options. These are described in detail in the SCRAMNet Network Cabinet Kit Hardware Reference (Doc. No. D-T-MR-CABKIT). D.2 Compact Cabinet Kit The Compact Cabinet Kit for the SCRAMNet Network provides fiber-optic or coax cable access to the node’s connections and maintains the shielding of the chassis.
  • Page 128 CABINET KIT D.3 Expanded Cabinet Kit The Expanded model shown in Figure D-2 has connections for up to two media cards providing the option of signal redundancy. This model also comes with a faceplate. The Expanded cabinet kit has a VME P2 cabling option. This permits connection to the cabinet kit board via the P2 backplane connection.
  • Page 129 CABINET KIT D.4 Direct-attached P2 Cabinet Kit The Direct-Attached P2 cabinet kit provides an interface with the SCRAMNet host board via the P2 connector on the back of the VME6U board. It attaches directly to the connector with no intermediate cable. The kit consists of a cabinet-kit board and a DIN 41612-connector shell and screws to adapt the backside of the VME backplane for connection to this board.
  • Page 130 CABINET KIT This page intentionally left blank Copyright 2007 VME6U HARDWARE REFERENCE...
  • Page 131 E. E - HOST TIMING ACCESS APPENDIX E HOST TIMING ACCESS TABLE OF CONTENTS E.1 Introduction .............................E-1 E.2 Dual-Port RAM Controller Module......................E-1 E.2.1 Contention ..........................E-1 E.3 Host Interface Logic to Shared Memory/CSR ..................E-2 E.3.1 ASIC-Internal CSR READ ....................E-3 E.3.2 ASIC-Internal CSR WRITE....................E-4 E.4 Host Interface Logic to Host Specific CSR .....................E-5 E.4.1 Host-Specific CSR READ ....................E-6 E.5 Access Times............................E-6...

  • Page 133: Introduction

    HOST ACCESS TIMING E.1 Introduction The SCRAMNet+ host access timing is comprised of three separate module timings. • Dual-Port RAM Controller (DPRC). • Host Interface Logic to shared memory/CSR. • Host Interface Logic to host-specific CSR. The first module allows shared memory to be updated by the high-speed serial network without utilizing valuable CPU bus bandwidth.

  • Page 134: Host Interface Logic To Shared Memory/Csr

    HOST ACCESS TIMING NOTE: The cases resulting in stretched cycles describe a very fast host bus condition and are not normal. In reality, SCRAMNet memory was designed and optimized for CPU data storage. Therefore CPU activities such as instruction fetches, instruction execution, and other miscellaneous activities will ensure the phenomenon of cycle stretching will rarely, if ever, occur.

  • Page 135: Asic-Internal Csr Read

    HOST ACCESS TIMING E.3.1 ASIC-Internal CSR READ The ASIC is typically configured through a number of control and status registers (CSR). The READ and WRITE cycles are not any different from any other ASIC resource cycles. The following is a READ cycle of an ASIC-internal CSR: AS (Address Strobe) and DS (Data Strobe) fall HREQ (Host Request) requested for a particular CSR (address) Wait for HACK (Host Acknowledge) to provide READ data...

  • Page 136: Asic-Internal Csr Write

    HOST ACCESS TIMING E.3.2 ASIC-Internal CSR WRITE This is a typical WRITE cycle of an ASIC-internal CSR: AS and DS fall HREQ requested for a particular CSR (address) Data accepted and ASIC asserts HACK Assert DTACK (Data Transfer Acknowledge) Requester (Master/CPU) de-asserts AS and DS (end of cycle) Figure E-3 is an example of a WRITE to an internal CSR.

  • Page 137: Host Interface Logic To Host Specific Csr

    HOST ACCESS TIMING E.4 Host Interface Logic to Host Specific CSR ASIC RESOURCES HOST LOGIC HOST DTACK SPECIFIC RESOURCES Figure E-4 Non-ASIC Resources The third module is the actual host logic needed to interface the non-ASIC resources (external host-specific CSR) to the host CPU as depicted in Figure E-4. The Interrupt Vector register is a non-ASIC resource.

  • Page 138: Host-Specific Csr Read

    HOST ACCESS TIMING E.4.1 Host-Specific CSR READ READ operations on the external CSRs do not go through normal ASIC data paths. Therefore, timings for this cycle vary from other CSR READ cycles. These external CSRs are not ASIC resources and therefore do not request ASIC cycles to READ from them.

  • Page 139: Typical Access Sequence

    HOST ACCESS TIMING E.5.1 Typical Access Sequence The following is the typical Host READ and Host WRITE sequence with no contention. READ AS and DS fall (Start of cycle) HREQ asserted HREQ_PEND (Host Request Pending) asserted (DPRC accepts request) DPRC READ shared memory and pass the data to Host-Interface Logic De-assert HREQ_PEND HACK Release bus (DTACK)
  • Page 140 HOST ACCESS TIMING CONFIGURATION The test was conducted with two nodes on a ring and an extremely fast host CPU as a host data generator. This fast CPU is theoretical since there is no CPU available today that is capable of maintaining the VME specification of 40 MB/sec. The two nodes were defined having their transmitters disabled, and their Interrupt FIFOs filled.

  • Page 141: Back-To-Back Host Reads

    HOST ACCESS TIMING E.5.3 Back-to-Back Host READs Figure shows access timing for a Back-to-back VME read. All timing shown is based on the fastest possible VME master (according to VME specification C.1) driving the bus, and the maximum bandwidth on the SCRAMNet Network ring.
  • Page 142 HOST ACCESS TIMING FIRST CYCLE 1. AS, DSx fall – Start of Cycle (80 ns delay to decode address). 2. HREQ asserted – READ request to DPRC. 3. Host interface logic sleeps until HACK is received from DPRC (Maximum READ Time) 4.

  • Page 143: Back-To-Back Host Writes

    HOST ACCESS TIMING E.5.4 Back-to-Back Host WRITEs Figure E-9 shows access timing for two back-to-back VME WRITEs as fast as possible according to the VME specification revision C1. The first cycle shows the normal buffered WRITE cycle and the second cycle shows a stretched WRITE cycle (maximum hold).
  • Page 144 HOST ACCESS TIMING Once the network transactions are cleared, the buffered data from the host WRITE can be written to shared memory which clears the WRITE buffer. This takes 240 ns from the request to the acknowledgment. DPRC has not yet written to shared memory 6.
  • Page 145 F. F - CONFIGURATION AIDS APPENDIX F CONFIGURATION AIDS...
  • Page 147 CONFIGURATION AIDS SCRAMNet CONTROL/STATUS REGISTERS REFERENCE SHEET CSR 0 CSR 2 CSR 4 CSR 6 always 0 RX ENB available to host data intrpt vector always 0 TX ENB available to host data intrpt vector REDUND LINK TOGGLE available to host RFA 2 data intrpt vector HOST INT ENB...
  • Page 148 CONFIGURATION AIDS CSR 8 CSR 10 CSR 12 CSR 14 SM ACCESS ENB VIRT PG ENB reserved AGE & RXID MUX reserved HOLDOFF DISABLE reserved always 0 CHP SELECT EEPROM reserved always 0 reserved always 0 reserved AUX MICROWIRE reserved MICROWIRE DOUT reserved always 0...
  • Page 149 SCRAMNet NETWORK CONFIGURATION DATA SHEET MEMORY NODE HOST MEMORY SCRAMNet ADDRESS ADDRESS MACHINE SIZE LEVEL SERIAL # & BUS & BUS...
  • Page 151 1. GLOSSARY GLOSSARY...
  • Page 153 GLOSSARY A16----------------------------------A type of module that provides or decodes an address on address lines A01 through A15. A24----------------------------------A type of module that provides or decodes an address on address lines A01 through A23. A32----------------------------------A type of module that provides or decodes and address on address lines A01 through A31.
  • Page 154 GLOSSARY HACK ------------------------------Host Acknowledge. HREQ ------------------------------Host Request. HREQ_PEND --------------------Host Request Pending. insert a node ----------------------The act of placing a node on a network for the purpose of transmitting and receiving messages. interrupt ---------------------------An event that changes the normal flow of instruction execution other than an exception or a branch, jump, case or call instruction.
  • Page 155 GLOSSARY protocol violation ----------------A signal error at the physical layer (fiber or coax) resulting from noise on the transmission lines or a result of hardware failure. This violation can be any one of the following: • Missing transition for two clock periods on either line •...
  • Page 156 GLOSSARY slave --------------------------------A functional module that detects DTB cycles initiated by a master and, when those cycles specify its participation, transfers data between itself and the master. slot ----------------------------------A position where a board can be inserted into a backplane. If the system has both a J1 and a J2 backplane (or a combination J1/J2 backplane) each slot provides a pair of 96-pin connectors.
  • Page 157 1. INDEX INDEX...
  • Page 159 INDEX connectors receiver input.......... 2-11, 5-25 SMA ..............4-10 access timing ........E-1, E-9, E-11 transmitter output ........2-11, 5-25 ACR.1-1, 2-4, 2-5, 2-6, 2-8, 2-10, 4-8, 5-8, 5-9, 5-10, control registers ..........5-3, 5-6 5-12, 5-15, 5-16, 5-19, B-3, B-8, B-17, C-11, F-1, control/status register.
  • Page 160 INDEX fiber optic loopback mode ........B-6 internal clock speeds..........A-1 fiber optics loopback interrupt disable ...............C-3 enable .............. 5-15 fiber-optic cable......4-10, 4-11, 5-3, 5-4 FIFO ..2-3, 2-6, 4-14, 5-7, 5-9, 5-12, 5-14, 5-15, B- fiber-optic cabling........2-9, 5-4, 5-10 2, B-3, B-4, B-5, B-9, B-12, C-1, C-2, C-5, E-8 fiber-optic loopback mode......
  • Page 161 INDEX light signal ............. 4-9 network interrupt enable ........B-3, C-1 long-link fiber..........3-5, 4-10 network time-out .......... 4-1, 4-14 longword..........B-8, B-17, C-11 node ID ........... 5-4, B-9, C-4, F-1 longword boundary......2-10, 5-5, 5-19 node identification ........4-1, 4-14 loopback mode.. 2-11, 5-4, 5-10, 5-20, 5-25, B-2, B-7 node latency......
  • Page 162 INDEX receiver pair ...........2-9, 4-11, 5-4 transmit redundant Rx/Tx fault.......... 5-14 FIFO ..............B-4 redundant transceivers ........4-2, B-6 transmit redundant TxRx toggle ..........C-1 FIFO ..............B-5 resolution bus switch ..........4-6 transmit enable............C-1 ring continuity ..........3-1, 5-25 transmit FIFO ............5-28 ring integrity ......

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