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Curtiss-Wright DTI-VME/S User Manual

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DTI-VME/S
User Manual
Document No. T-T-MU-DTXXVS##-A-0-A2

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  • Page 1 DTI-VME/S User Manual Document No. T-T-MU-DTXXVS##-A-0-A2...
  • Page 3 Curtiss-Wright Controls, Inc. reserves the right to make changes without notice. Curtiss-Wright Controls makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
  • Page 4 This product is intended for use in industrial, laboratory or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.

  • Page 5: Table Of Contents

    2.1 Step 1. Unpacking and Examining the Board................2-1 2.2 Step 2. Selecting The I/O Base Address...................2-2 2.3 Step 3. Installing The Board.....................2-2 2.4 Step 4. Interconnection to DTI-VME/S Boards or RTs............2-3 2.4.1 Pin 1 Command Strobe (Output) ................2-3 2.4.2 Pin 2 Subsystem Fail (Input) .................2-3 2.4.3 Pin 3 External Override (Input) ................2-3...
  • Page 6 6.3.1 Control Word ......................6-6 6.3.2 Message Status Pointer...................6-7 6.3.3 Data List Pointer.....................6-8 6.4 RT Registers..........................6-8 6.4.1 Control Register (00).....................6-8 6.4.2 RT Address Register (10)..................6-9 7. BUS MONITOR MODE OF OPERATION ....................7-1 7.1 Bus Monitor Message Blocks ....................7-1 Copyright 2004 DTI-VME/S...
  • Page 7 7.3.5 Control Register (00)....................7-4 7.3.6 High Priority Interrupt Register (07) and Standard Interrupt Register (09)……...7-4 7.3.7 Reset Timer Register (13) ..................7-4 7.3.8 Remote Terminal Address Register (10) ..............7-4 7.4 Collecting Data .........................7-4 7.5 Post-Run Processing .........................7-4 8. INDEX................................1 Copyright 2004 DTI-VME/S...
  • Page 8 TABLE OF CONTENTS This page intentionally left blank Copyright 2004 DTI-VME/S...

  • Page 9: Overview

    Emulation of multiple data buses. 1.2 Highly Flexible Configuration To meet a wide range of systems requirements, the DTI-VME/S allows the user to define the size of the dual-port RAM (16K, 32K, 48K, or 64K words) and the starting address of the memory block.

  • Page 10: Enhanced Bus Connection Capability

    These options are enabled via Configuration Registers 26, 27 and 28. (See Getting Started for details.) The dual-port RAM is accessible directly from the VME bus or from the DTI-VME/S. All accesses to the dual-port RAM must be in 16-bit word transfers.

  • Page 11: Bus Monitor Mode

    RT to monitor. (See the Registers section of this manual.) Using the registers and command structures, the DTI-VME/S processes a series of monitored messages without host intervention. The BM also detects response time out, long and short word count, bit count, Manchester II and parity errors.

  • Page 12: Specifications

    The 1553 logic contains the transceiver, transformers, and relays. The relays isolate or connect the 1553 bus, select transformer or direct coupled connection to the bus or terminates the bus. 1.10 Specifications Table 1-1 provides a list of specifications for the DTI-VME/S. Specifications Memory: 64K words of dual-port RAM...

  • Page 13: Quality Assurance

    OVERVIEW 1.11 Quality Assurance Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery.

  • Page 14: Ordering Process

    World Wide Web address: www.systran.com 1.13 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. •...

  • Page 15: Getting Started

    Once grounded, remove the board from the protective bag and place the board on the bag or any electrostatically-controlled surface. RSW3 RSW2 RSW1 Figure 2-1. DTI-VME/S Board Examine the board. If the board appears to be damaged, contact Curtiss-Wright Controls immediately. Copyright 2004 DTI-VME/S...

  • Page 16: Step 2. Selecting The I/O Base Address

    Locate an available slot in the host computer. Jumper the daisy-chained signal IACKIN*-IACKOUT* on all unu sed slots between the CPU and the DTI-VME/S, enabling the interrupt signal to be properly passed from the host. Remove the IACK jumper from the slot before inserting the DTI- VME/S.

  • Page 17: Step 4. Interconnection To Dti-Vme/S Boards Or Rts

    Pin 3 can also be used for multi- redundant applications. Upon receiving the Pin 3 signal, all current activity is aborted. pin may be connected to the RT command strobe Output of an adjacent DTI-VME/S when used. Copyright 2004...

  • Page 18: Pin 4 Ground

    The configuration registers must be programmed to meet the user system requirements before the DTI-VME/S is operational. The operation of these registers is described in the following sections. This information, combined with the definitions in the Registers section, provides the information required to write low-level software drivers for a VME host computer.

  • Page 19: Register 25: Bus Connection Relay Control

    2.6.1 Register 25: Bus Connection Relay Control Three bits in this register control relays that isolate the DTI-VME/S from the 1553 bus for self-test, connect an internal termination resistor to the DTI-VME/S and select a direct or transformer coupled connection to the bus.

  • Page 20: Register 26: Memory Size/Start Address/Bank Select

    This relay can isolate the DTI-VME/S from the 1553 bus. To isolate the DTI-VME/S from the 1553 bus, set the bit to 1 (the default value). When the bit is set to 0, the DTI-VME/S is connected to the 1553 bus. This relay is typically used only for powerup self-test of the DTI-VME/S board and doesn’t require disconnecting the board from any UUT.
  • Page 21 Because 128 KB of RAM is installed on all DTI-VME/S boards and VME address space is typically not a problem, the default selection is 128 KB of RAM starting at the base address.

  • Page 22: Register 27: Standard Address Select

    32-bit memory address, use Registers 27 and 28 to set the base starting address of dual-port RAM. NOTE: The DTI-VME/S occupies either a 24-bit or 32-bit memory address space at any given time. The board does not occupy both spaces simultaneously. Avoid overlapping the DTI-VME/S address space with another device in the A32 and A24 system address space.

  • Page 23: Register 28: Extended Address Select

    Seven bits in this register are used to perform the following: select the standard priority interrupt level, select the high priority interrupt level, and select the interrupt vector width. HIGH PRIORITY STANDARD INTERRUPT PRIORITY LEVEL INTERRUPT LEVEL Bits 7-15 Reserved. Copyright 2004 DTI-VME/S...

  • Page 24: Register 30: Standard Priority Interrupt Vector

    Registers 30 and 31 normally, but the upper byte is always read as 0x00FF. If the 16-bit vector is selected and the host performs an 8-bit interrupt acknowledge cycle, the DTI-VME/S does not respond and a bus error occurs.

  • Page 25: Register 31: High Priority Interrupt Vector

    7. Set the Start Enable Bit in the Control Register (Register 0). 8. Message implementation now begins by transmitting the transmit command stored in the Command Block. The DTI-VME/S waits to receive the status word book from the transmitting RT.

  • Page 26: Rt Operational Sequence With Interrupts

    7. Enable the desired bus and set the Start Enable Bit in Register 00. 8. The DTI-VME/S receives the incoming data words and stores them in memory as pointed to by the data list pointer. All incoming data is checked for validity.

  • Page 27: Bm Operational Sequence With Interrupts

    11. The DTI-VME/S, having encountered the Command Block Access Bit, asserts a standard interrupt and logs the event in the interrupt queue.
  • Page 28 GETTING STARTED This page intentionally left blank Copyright 2004 2-14 DTI-VME/S...

  • Page 29: Registers

    3.REGISTERS The DTI-VME/S contains 27 16-bit registers. Nine of these registers control interrupt handling. The following six interrupt registers, described in the Interrupts section, control operation: • Interrupt Queue Pointer Register (06) • High Priority Interrupt Enable Register (07) •...
  • Page 30 REGISTERS • Reset Timer Register (13) • Bus Monitor Control Register (14) • Bus Monitor Terminal Address Select Register (16) • Bus Monitor Terminal Address Select Register (17) NOTE: 1 = Set (Enable). 0 = Clear (Disable). Copyright 2004 DTI-VME/S...

  • Page 31: Control Register 00

    External Port Pin 3. Bit 10 RT/BM/BC - RT, BM or BC Select. Select operating mode of DTI-VME/S. BC = 1; RT/BM = 0. Bit 9 RTY OPPB - Retry on Opposite Bus. BC Mode - enables Retry on alternate bus. If you have enabled Bus A for multiple retries via Bits 5 and 6, these retries take place on Bus B.
  • Page 32 BC Mode - enables automatic RETRY on a received busy bit in the 1553 RT status response. Bit 0 ST EN - Start Enable. Start Enable (not READable) for RT/BM modes. BC Mode - starts/restarts a buslist execution. After any RESET, the RT, BM or buslist execution must be restarted via this bit. Copyright 2004 DTI-VME/S...

  • Page 33: Status Register 01 (Read Only)

    Indicates receiving a subsystem fail signal from the host subsystem on the SSYSF input (External Port). Bits 4-1 Reserved Bit 0 CM BK PG - (BC) Command Block/RT, BM. BC - Command Block execution in progress. RT/BM - in Operation. Copyright 2004 DTI-VME/S...

  • Page 34: Current Command Block Instruction Address (Bc) Subaddress Response Block

    RT's MIL-STD-553B Status Word. For example, Bit 0 of Register 03 corresponds to Bit 19 of the Status Word. The RT’s sync, RT Address and Parity Bits are not included. Bits 15-11 Reserved Bits 10-0 Polling Compare Bits. The bits to be compared with the Status Word. Copyright 2004 DTI-VME/S...

  • Page 35: Bit Word Register 04

    Bits 13-0 BIT Word. Contains the BIT word returned by the RT in response to Mode Code 19. The DTI-VME/S writes values to this register in response to either an Initiate Self-Test Mode Code (RT Mode) or a WRITE to Register 11. If the Bit Word needs to be modified, it can be read out, modified and re-written to this register.

  • Page 36: Interrupt Queue Pointer Register 06

    Contains the onboard RAM starting location of the Standard Priority Interrupt Queue (initialized by host). This register is updated by the DTI-VME/S with the address of the next entry in the queue when an interrupt block is written to the queue.

  • Page 37: High Priority Interrupt Status/Reset Register 08

    Bit 8 DAT OVR - Data Overrun. Data Overrun indicates that an internal DMA grant for access to the onboard RAM was not received by the DTI-VME/S within the allocated time required for a successful data transfer to memory. Bit 7 ILL CMD - Illogical Broadcast Command.

  • Page 38: Standard Priority Interrupt Enable Register 09

    INSTR - Instrumentation (RT). This function enables the Instrumentation Bits in the RT Status Word. Bit 14 BUSY2 - Busy. This bit sets the Busy Bit in the RT Status Word. It does not inhibit data transfers. Copyright 2004 3-10 DTI-VME/S...

  • Page 39: Bit Start Register 11 (Write Only)

    Bit 12 DBC - Dynamic Bus Control Acceptance (RT). Enabling this bit allows the DTI-VME/S to accept Dynamic Bus Control and to set the appropriate bit in the MIL-STD-1553B Status Word and the DTI-VME/S Status Register. Host intervention is required for the DTI-VME/S to take over as BC.

  • Page 40: Reset Timer Register 13 (Write Only)

    3.16 Register 15 Reserved 3.17 Bus Monitor Terminal Address Select (RT 0 - 15) 16 If Bit 13 of Register 14 is set, setting the appropriate bits in this register enables monitoring of the selected RT. Copyright 2004 3-12 DTI-VME/S...

  • Page 41: Bus Monitor Terminal Address Select (Rt 16 - 31) 17

    If Bit 13 of Register 14 is set, setting the appropriate bit in this register enables monitoring of the selected RT. 3.19 Master Reset Register 18 A READ of Register 18 initializes a Master Reset on the DTI-VME/S, clearing all sequencers and internal registers. Memory is not cleared. The READ data is not meaningful.

  • Page 42: Autodecrement Interrupt Counter Register 20

    It is cleared by a master reset or host system reset. Bits 14-9 Board Revision Level. These six bits reflect the revision level of the DTI-VME/S. Bit 8 EXC - Exceed Bit. This bit is set when 255 standard interrupts have been generated, but not processed, and another interrupt occurs (256th).

  • Page 43: Registers 21 Through 24 Reserved

    Bit 0 ISOBUS - Isolate Bus. This bit isolates the DTI-VME/S from the MIL STD 1553 bus for self-test. Write 0 = Connected to 1553 bus. Write 1 = Isolated from 1553 bus. Default = 1. The selected connection applies to Bus A and B.

  • Page 44: Memory Size/Start Address/Bank Select 26

    Write 11 = Bank 3 (upper 64 K Words). Default = 0. NOTE: The DTI-VME/S must be in an idle state during any bank switching operation. Bits 3 & 2 RAM Address Offset. These two bits can offset the address of the selected amount of dual port RAM. The address is offset from the base address selected by Registers 27 and 28.

  • Page 45: Standard Address Select 27

    NOTE: The amount of RAM selected is shared in dual-ported fashion with the DTI- VME/S. 3.25 Standard Address Select 27 This register represents the base address for standard (A24) address space. Reserved 3.26 Extended Address Select 28 This register represents the base address for extended (A32) address space. Reserved Copyright 2004 3-17 DTI-VME/S...

  • Page 46: Interrupt Level And Vector Width Selection 29

    Write 010 = Level 2. Write 011 = Level 3. Write 100 = Level 4. Write 101 = Level 5. Write 110 = Level 6. Write 111 = Level 7 (highest - non-maskable). Default = 2. Copyright 2004 3-18 DTI-VME/S...

  • Page 47: Standard Priority Interrupt Vector 30

    Register 29 is 0 (8-bit vector), the upper byte of response data is 0x00FF. The default address for this register is 0x0080. NOTE: If the 8-bit vector is selected in Register 29 (Bit 6 = 0), Bits 15- 8 of this register always read as 1s. Copyright 2004 3-19 DTI-VME/S...
  • Page 48 REGISTERS This page intentionally left blank Copyright 2004 3-20 DTI-VME/S...

  • Page 49: Interrupts

    4.INTERRUPTS 4.1 Standard and High Priority Interrupts The DTI-VME/S allows MIL-STD-1553B events to be defined as high priority interrupt, standard priority interrupt, or no interrupt. The main difference between standard interrupts and high priority interrupts is the method by which they are serviced. High priority interrupts are recorded in the registers and generally handled upon occurrence.

  • Page 50: Interrupt Level

    Address of the next standard priority interrupt entry in the queue 4.2 Interrupt Level The speed by which the VME host services a DTI-VME/S event interrupt depends on the priority level assigned to the interrupt. For example, since Level 7 has a higher priority than Level 1, an event interrupt assigned to interrupt Level of 7 is serviced before an event interrupt assigned to Interrupt Level 1.

  • Page 51: Interrupt Queue

    The pointer indicates the location of the corresponding Command Block instruction. RT Mode - The pointer indicates the location of the corresponding subaddress/mode code response block. BM Mode - The pointer indicates the location of the corresponding Bus Monitor record. Copyright 2004 DTI-VME/S...

  • Page 52: Operational Interrupt Registers

    To enable a particular event for high priority interrupt handling, set the corresponding bit to 1. Setting Bit 0 to 1 enables all standard interrupts to notify the host. See page 3-8 for a bit explanation of this register. FAIL FAIL Reserved Copyright 2004 DTI-VME/S...

  • Page 53: High Priority Interrupt Status/Reset Register 08

    1. To clear an event, a value of 1 is written to the corresponding bit. DTI-VME/S operation is suspended while generating a high priority interrupt until the corresponding status bit is reset by writing a 1 to that bit. See page 3-9 for a bit explanation of this register.

  • Page 54: Interrupt Counter Read/Clear Register 19

    INTERRUPTS 4.5.5 Interrupt Counter Read/Clear Register 19 The DTI-VME/S has a circular or standard interrupt queue that provides the ability to store up to 255 standard interrupt packets before writing over any packets. The number of standard interrupts in the interrupt queue at any time is recorded by Bits 0-7 of the interrupt counter.

  • Page 55: Bus Controller Mode Of Operation

    5.BUS CONTROLLER MODE OF OPERATION In the BC mode, the DTI-VME/S Command Block structure and internal registers provide the capability of defining, storing, and executing comprehensive lists of Command Block (or bus) instructions, which allow specification of subsequent instructions. Other BC features include: •...

  • Page 56: Bus Controller Structure

    If a bus message error is enabled as a high priority interrupt and a bus message occurs, the DTI-VME/S halts operation until the interrupt is serviced. If a bus message error is enabled as standard priority, the data is queued and operation does not halt.
  • Page 57 NOTE: If the intermessage timer is enabled and the Skip Bit is set, the timer provides the programmed delay before proceeding. If the current bus instruction exceeds the inter- message timer delay, the next message begins as if the timer was not enabled. Copyright 2004 DTI-VME/S...

  • Page 58: Command Word One

    (Figure 5-3). With top-to-bottom linkage, the tail pointer points to the next sequential Command Block’s head pointer. With bottom-to- top linkage the head pointer points to the previous sequential Command Block’s head pointer. Copyright 2004 DTI-VME/S...

  • Page 59: Mode Code/Broadcast Commands

    Mode Code/Broadcast transfers. 5.2.1 Mode Command With Data Word (Transmit) Functioning as a BC, the DTI-VME/S issues a transmit command to the RT using a mode code specified in MIL-STD 1553B. After command word validation, the RT transmits a status word, followed by one data word. The status word and data word transmit in one continuous fashion.

  • Page 60: Mode Command With Data Word (Broadcast)

    5.2.7 RT-to-RT Transfer (Broadcast) The DTI-VME/S issue a receive Command Word One with RT 31 (11111) in the RT address field, followed by a transmit command to another RT (RT “X”) using the selected broadcast of RT X. After command word validation, RT X transmits a status word, followed by the specified number of data words.

  • Page 61: Remote Terminal Mode Of Operation

    6.REMOTE TERMINAL MODE OF OPERATION In the RT mode, the DTI-VME/S emulates a MIL-STD 1553B RT with up to 30 data subaddresses and two mode code subaddresses or 31 data subaddresses and one mode code subaddress. Changing RT emulation from one RT number to another RT number is software selectable.

  • Page 62: Control Word

    RT storage area for 64K words of RAM before service is required is over 2,000 32 data word messages. Upon the completion of each valid message, the Index Field (Bits 6 through 0) is decremented by 1 unless the index equals 0. Copyright 2004 DTI-VME/S...

  • Page 63: Message Status Pointer

    Indicates when the message was recorded (in 64 microsecond increments). For example, if Bits 0 through 7 read 0000 0010 (binary), the message was completed 128 to 191 microseconds after the timer started. The timer is reset via Register 13. Copyright 2004 DTI-VME/S...

  • Page 64: Data List Pointer

    If the BC sends a receive command, the RT buffers data into a first-in/first-out indexed queue that stores up to 128 buffers per subaddress. Each buffer can store up to 32 data words. When a message is placed in the RT’s queue, the message is automatically time- tagged. Copyright 2004 DTI-VME/S...

  • Page 65: Rt Mode Code Response Block

    Interrupts may be generated when the buffer fills up. 6.3 RT Mode Code Response Block Frequently, the instruction sent to an RT takes the form of a mode code. Table 6-1 displays the MIL-STD 1553B mode codes supported by the DTI-VME/S. Associated Function...

  • Page 66: Control Word

    Message Error Bit set in the status. If via the Standard Interrupt Enable Register (09) Illegal Command events are enabled, Bit 13 is set and the RT transacts with mode code without data, a subaddress standard priority interrupt occurs. (This interrupt sets the Message Error Bit in the message status word). Copyright 2004 DTI-VME/S...

  • Page 67: Message Status Pointer

    This bit indicates that the SSYSF (subsystem failure) signal was asserted just before the status word transferred to memory. This signal corresponds to Pin 2 of the external port. Bit 14 Broadcast Message This bit indicates that the broadcast message was received at this subaddress. Copyright 2004 DTI-VME/S...

  • Page 68: Data List Pointer

    Set Bit 7 for Bus A. • Set Bit 8 for Bus B. • Clear Bit 10 for RT mode. See page 3-3 for a bit explanation of this register. BCST RT/BM STEN RETRY /STD DATA TIME OPPB RECOUNT Copyright 2004 DTI-VME/S...

  • Page 69: Rt Address Register (10)

    Bit 12 DBC - Dynamic Bus Control Acceptance (RT). Allows the DTI-VME/S to accept Dynamic Bus Control and set the appropriate bit in the 1553B Status Word and the Status Register. Host intervention is required for the DTI-VME/S to take over as BC.
  • Page 70 RTA PAR - RT Address Parity. This is an odd parity used with the RT Address. It ensures accurate recognition of the RT. Bits 4-0 RT Address Modify the RT Address by writing to these bits. Must be written after reset. Copyright 2004 6-10 DTI-VME/S...

  • Page 71: Bus Monitor Mode Of Operation

    7.BUS MONITOR MODE OF OPERATION As a bus monitor, the DTI-VME/S monitors all RTs or a select number of RTs and their subaddresses. Changing RT monitoring from one RT number to another is software- selectable. Using dual-port RAM, the DTI-VME/S monitors, time tags and stores over 1,000 messages of 32 data words each without host intervention.

  • Page 72: Control/Status Word

    7.1.3 Command Word Two Used during RT-to-RT transfers, contains the second command for RT-to-RT transfers. This word contains the transmitting RT address, subaddress and the word count. Command Word Two is not used in single RT transfers. Copyright 2004 DTI-VME/S...

  • Page 73: Data Pointer

    BUS MONITOR 7.1.4 Data Pointer The 16 bit Data Pointer points to the onboard RAM starting location of the DTI-VME/S's dual-port RAM, where the data buffer of the current message record block resides. The number of data words per message record block instruction is 32 or less. You must initialize the pointer each time you want to use it.

  • Page 74: Interrupt Queue Pointer Register (06)

    Look for the following important information in the Message Record Block: • Bit 15 of the control word is set and the block contains a message. Copyright 2004 DTI-VME/S...
  • Page 75 BUS MONITOR • Bit 14 of the control word is set and a message error has occurred. • Bit 12 of the control word is set and the message has been transmitted on Bus A. Copyright 2004 DTI-VME/S...

  • Page 77: Index

    8. INDEX INDEX Copyright 2004 INDEX 1 DTI-VME/S...
  • Page 79 Bus Monitor Terminal Address Select Registers 7- IACK jumpers ...........2-2 IACK Jumpers ..........2-2 Indexing ............1-1 Interconnection to DTI-VME/S Boards or RTs 2-3 Command Block 1-2, 2-11, 2-12, 2-13, 3-5, 3-6, 3- Intermessage Timer...........5-3 8, 3-9, 3-10, 4-2, 4-3, 5-1, 5-2, 5-3, 5-4, 5-5, 7- Interrupt Count Registers ........4-3...
  • Page 80 Registers 27 and 28........... 2-6 Variable Memory Space Allocation....1-1 Remote Terminal (RT)........1-1 Voltage..............1-4 Remote Terminal Address Register ..3-10, 7-4 Reset Command Register......3-11, 7-3 Reset Timer Register......3-2, 3-12, 7-4 Rotary Switches RS1, RS2 and RS3....2-2 Word Size............1-4 Copyright 2004 INDEX 4 DTI-VME/S...

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