Switching Characteristics - Cirrus Logic CS5550 Manual

SWITCHING CHARACTERISTICS

Master Clock Frequency
Master Clock Duty Cycle
CPUCLK Duty Cycle
Rise Times
(Note 9)
Fall Times
(Note 9)
Start-up
Oscillator Start-Up Time
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Timing
CS Falling to SCLK Rising
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Timing
CS Falling to SDI Driving
SCLK Falling to New Data Bit (hold time)
CS Rising to SDO Hi-Z
Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz.
8. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
9. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
10. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
8
Parameter
Internal Gate Oscillator (Note 7)
Any Digital Input Except SCLK
Any Digital Output
Any Digital Input Except SCLK
Any Digital Output
XTAL = 4.096 MHz (Note 10)
Pulse Width High
Pulse Width Low
Symbol
MCLK
(Note 8)
t
rise
SCLK
t
fall
SCLK
t
ost
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
CS5550
Min Typ Max
2.5 4.096 5
40 - 60
40 60
- - 1.0
- - 100
- 50 -
- - 1.0
- - 100
- 50 -
- 60 -
- - 2
200 - -
200 - -
50 - -
50 - -
100 - -
100 - -
- 20 50
- 20 50
- 20 50
Unit
MHz
%
%
µs
µs
ns
µs
µs
ns
ms
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS630F1