1. Manuals
  2. Brands
  3. Cirrus Logic Manuals
  4. Media Converter
  5. CS4953xx
  6. Hardware user manual

Cirrus Logic CS4953xx Hardware User Manual

32-bit audio dsp family
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
CS4953x
32-bit Audio DSP Family
CS4953xx
Har dware User s Manua l
This document contains information for a new product.
Preliminary Product Information
Cirrus Logic reserves the right to modify this product without notice.
Copyright 2008 Cirrus Logic, Inc.
JULY '08
DS732UM7
http://www.cirrus.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the CS4953xx and is the answer not in the manual?

Questions and answers

Related Manuals for Cirrus Logic CS4953xx

Summary of Contents for Cirrus Logic CS4953xx

  • Page 1 32-bit Audio DSP Family CS4953xx Har dware User s Manua l This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright 2008 Cirrus Logic, Inc. JULY ’08 DS732UM7 http://www.cirrus.com...
  • Page 2 Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, Cirrus Extra Surround, Cirrus Original Multichannel Surround, and Cirrus Original Sur- round are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

  • Page 3: Table Of Contents

    1.2 Functional Overview of the CS4953xx Chip ........
  • Page 4 CS4953xx Hardware Users Manual 3.2.2 I C Bus Dynamics ......................3-4 3.2.3 I2C Messaging........................3-7 3.2.3.1 SCP1_BSY Behavior ..................3-7 3.2.3.2 Performing a Serial I C Write ................3-8 3.2.3.3 I C Write Protocol ..................3-9 3.2.3.4 Performing a Serial I C Read ................3-9 3.2.3.5 I C Read Procedure ..................3-11...

  • Page 5: Figures

    9.8 Revision History............9-21 Figures Figure 1-1. CS4953xx Chip Functional Block Diagram .................1-2 Figure 2-1. Operation Mode Block Diagrams ....................2-2 Figure 2-2.
  • Page 6 Figure 9-10. Crystal Oscillator Circuit Diagram ...................9-13 Figure 9-11. 144-Pin LQFP Pin Layout .......................9-15 Figure 9-12. 128-Pin LQFP Pin Layout .......................9-16 Tables Table 2-1. Operation Modes..........................2-3 Table 2-2. SLAVE_BOOT message for CS4953xx ..................2-10 Table 2-3. HCMB_PARALLEL message for CS4953xx ................2-10 Copyright 2008 Cirrus Logic, Inc. DS732UM7...
  • Page 7 Table 2-5. HCMB_SPI message for CS4953xx ..................2-11 Table 2-6. GPIO Pins Available as EE_CS in HCMB..................2-12 Table 2-7. SOFT_RESET message for CS4953xx ..................2-12 Table 2-8. Boot Read Messages from CS4953xx ..................2-12 Table 2-9. Boot Command Messages for CS4953xx ..................2-13 Table 2-10. SOFTBOOT Message......................2-14 Table 2-11.
  • Page 8 CS4953xx Hardware Users Manual Table 9-9. Hardware Strap Pins ........................9-14 Table 9-10. Pin Assignments ........................9-17 viii Copyright 2008 Cirrus Logic, Inc. DS732UM7...

  • Page 9: Chapter 1. Introduction

    ICs. The CS4953xx is a 32-bit RAM-based processor that provides up to 150 MIPS of processing power and includes all standard codes in ROM. It has been designed with a generous amount of on-chip program and data RAM, and has all necessary peripherals required to support the latest standards in consumer entertainment products.

  • Page 10: Figure 1-1. Cs4953Xx Chip Functional Block Diagram

    Overview CS4953xx Hardware Users Manual Figure 1-1 illustrates the functional block diagram for the CS4953xx chip. CS4953xx DSPB Stereo Audio Input/DSD DAI1 DSPA Stereo Audio Input/DSD Peripheral Debug Stereo Audio Input/DSD Controller Controller Controller Stereo Audio Input/DSD Stereo Audio Input/DSD...
  • Page 11 The CS4953xx contains sufficient on-chip memory to support decoding of all major audio decoding algorithms available today. The CS4953xx supports a glueless SDRAM/Flash interface for increased all-channel delays. The memory interface also supports connection to an external 8- or 16-bit-wide EPROM or Flash memory for code storage, thus allowing products to be field upgraded as new audio algorithms are developed.

  • Page 12: Functional Overview Of The Cs4953Xx Chip

    CS4953xx Hardware Users Manual 1.2 Functional Overview of the CS4953xx Chip The CS4953xx chip supports a maximum clock speed of 150 MHz in a 144-pin LQFP or 128-pin LQFP package. A high-level functional description of the CS4953xx chip is provided in this section.

  • Page 13: Direct Stream Digital ® (Dsd) Controller

    (DSD) Controller The CS4953xx also has a DSD controller which allows the DSP to be integrated into a system that supports SACD audio. The DSD controller pins are shared with the DAI1 and DAI2 ports. The DSD port consists of a bit clock (DSD_CLK) and six DSD data inputs (DSD[5:0]).

  • Page 14: Sdram Controller

    1.2.14 Timers A 32-bit timer block runs off the CS4953xx DSP clock. The timer count decrements with each clock tick of the DSP clock when the timer is enabled. When the timer count reaches zero, it is re-initialized, and may be programmed to generate an interrupt to the DSP.

  • Page 15: Programmable Interrupt Controller

    Functional Overview of the CS4953xx Chip CS4953xx Hardware Users Manual 1.2.16 Programmable Interrupt Controller The Programmable Interrupt Controller (PIC) forces all incoming interrupts to be synchronized to the global clock, HCLK. The PIC provides up to 16 interrupts to the DSP Core. The interrupts are prioritized with interrupt 0 as the highest priority and interrupt 15 as the lowest priority.
  • Page 16 Functional Overview of the CS4953xx Chip CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc...

  • Page 17: Chapter 2. Operational Modes

    The CS4953xx can be either a slave device or a master device for the boot procedure. In Master Boot Mode, the CS4953xx is the master boot device and can automatically boot the application code from either serial or parallel external ROM (the slave boot device).

  • Page 18: Figure 2-1. Operation Mode Block Diagrams

    CS4953xx Hardware Users Manual P a ra lle l C o n tro l B u s M e m o ry B u s / S C P 2 E x te rn a l R O M / S y s te m H o s t E x t.

  • Page 19: Operational Mode Selection

    2.1 Operational Mode Selection The operational mode for the CS4953xx is selected by the values of the HS[4:0] pins on the rising edge of RESET. This value determines the communication mode used until the part is reset again. This value also determines the method for loading application code.

  • Page 20: Host Controlled Master Boot

    CS4953xx is valid. One feature that is of special note – the entire boot procedure for the CS4953xx can be made of a combination of slave boot and host-controlled master boot procedures. An example can be seen in...

  • Page 21: Performing A Host Controlled Master Boot (Hcmb)

    Slave Boot Procedures CS4953xx Hardware Users Manual 2.2.1.1 Performing a Host Controlled Master Boot (HCMB) Figure 2-2 shows the steps taken during a Host Controlled Master Boot (HCMB). The procedure is discussed in Section 2.2.1.1.1 START RESET (LOW) WRITE_* (HCMB_<MODE>)
  • Page 22 13. Read the BOOT_SUCCESS message. The host then reads a message from the appropriate communications port. Each.ULD file contains a checksum that is compared at the end of the boot process. The CS4953xx sends a BOOT_SUCCESS message to the host if the checksum is correct after the download.

  • Page 23: Slave Boot

    2.2.2 Slave Boot The Slave Boot procedure is a sequence in which the external host is the bus master and directly loads the CS4953xx application code. The system host controller has each of the five communication modes available, as specified in Table 2-1.

  • Page 24: Performing A Slave Boot

    Slave Boot Procedures CS4953xx Hardware Users Manual 2.2.2.1 Performing a Slave Boot Figure 2-3 shows the steps taken during a Host Controlled Master Boot (HCMB). The procedure is discussed in Section 2.2.2.1.1 START WRITE_*(SLAVE_BOOT) RESET# (LOW) NOTE 2 READ_*(MSG) SET HS[3:0] PINS FOR...
  • Page 25 14. Read the BOOT_SUCCESS message. The host then reads a message from the appropriate communications port. Each.ULD file contains a checksum that is compared at the end of the boot process. CS4953xx sends a BOOT_SUCCESS message to the host if the checksum is correct after the download.

  • Page 26: Boot Messages

    0x8000 0000 The SLAVE_BOOT message is used when the system host controller will send each .uld file directly to the CS4953xx. The SLAVE_BOOT message must be issued for each overlay image (.uld file) that is downloaded to the CS4953xx. Please see Section 2-3 "Slave Boot Sequence"...

  • Page 27: Host-Controlled Master Boot From I

    C clock is derived from the internal core clock. This clock can be divided down with the ‘c’ 12-bit divider variable. The command byte (the first byte to the I C ROM) can be defined by the ‘s’ variable. The CS4953xx control port used for the HCMB_I2C can be configured by the ‘p’ variable.

  • Page 28: Soft Reset

    ‘c’ 12-bit divider variable. The command byte (the first byte to the SPI ROM) can be defined by the ‘s’ variable. The CS4953xx control port used for the HCMB_SPI can be configured by the ‘p’...

  • Page 29: Master Boot Procedure

    Table 2-1. Once the rising edge of RESET has occurred, the CS4953xx will load a single overlay from address 0x0. It should be noted that the loaded overlay must reconfigure one of the control ports to be slave to the bus for a system host controller to configure the part.

  • Page 30: Softboot

    2.4 Softboot The O/S application code for the CS4953xx allows users to swap out one or more overlays during run time, without the need for re-download of the entire overlay stack. This is helpful for reducing the time required for switching between different types of incoming audio data streams.

  • Page 31: Softboot Procedure

    Step 4. If the message is not the SOFTBOOT_ACK message, the host should return to Step 2. 4. Load Overlays. Repeat the boot procedure used to originally load the overlays into the CS4953xx (for example, SLAVE_BOOT, HCMB_<MODE>), but only the overlays that need to be swapped should be loaded.

  • Page 32: Softboot Example

    Softboot CS4953xx Hardware Users Manual 2.4.2.2 Softboot Example Figure 2-6 contains an example softboot flow diagram. Section 2.4.2.3 provides a step-by-step description of the Softboot procedure using the Host Control Master Boot (HCMB) procedure that is most commonly used CS4593x systems.

  • Page 33: Softboot Example Steps

    CS4953xx until the APP_START message has been read. If the CS4953xx does not send an application start message, the host must return to Step 1. If the message read is any value other than APP_START, the system controller should abort.
  • Page 34 Softboot CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc 2-18...

  • Page 35: Chapter 3. Serial Control Port

    The serial control port configuration for an operating mode is determined by the state of special boot mode pins as the CS4953xx exits reset. The rising edge of the RESET pin samples the HS[4:0] pins to determine the communication mode and boot style. The CS4953xx O/S currently supports two serial control port configurations for host control: •...

  • Page 36: I 2 C Port

    C port has the ability to communicate directly with the other devices and is assigned a unique address whether it is a CPU, memory, or some other device. A block diagram of the CS4953xx I C Serial Control Port is...
  • Page 37 As seen in Figure 3-2, two serial ports are available on the CS4953xx. Each can be configured as either master or slave. For Audio applications, SCP1 is configured as a slave port and SCP2 is configured as a master port. SCP2 is used only in systems that are booting from serial EEPROM.

  • Page 38: Cs4953Xx Hardware Users Manual

    I2C Port CS4953xx Hardware Users Manual Table 3-1. Serial Control Port 1 I C Signals (Continued) LQFP-144 LQFP-128 Pin Name Pin Description Pin # Pin # Type C Control Port Bit Clock. In master mode, this pin serves as the serial control clock...

  • Page 39: Figure 3-4. I 2 C Address With Ack And Nack

    This byte must be a 7-bit I C slave address + R/W bit. The 7-bit I C address for the CS4953xx is 1000000b (0x80). The R/W bit is used to notify the slave if the current transaction is for the master to write data to the slave (R/W = 0) or read data from the slave (R/W = 1).

  • Page 40: Figure 3-5. Data Byte With Ack And Nack

    I2C Port CS4953xx Hardware Users Manual Start SCP1_CLK SCP1_SDA A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Data Byte Write Read Start SCP1_CLK SCP1_SDA A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W ACK Data Byte NACK Write Read M = Master Drives SDA S = Slave Drives SDA Figure 3-5.

  • Page 41: I2C Messaging

    3-4. Every I C transaction to the CS4953xx will involve 4-byte words used for control and application image download. A detailed description of the serial SPI communication mode is provided in this section. This includes: • A flow diagram and description for a serial I C write •...

  • Page 42: Scp1_Bsy Behavior

    C write cycle are met (see the CS4953xx datasheet for timing specifications). When writing to the CS4953xx, the same protocol described in this section will be used when writing single-word messages to the boot firmware, writing multiple-word overlay images to the boot firmware, and writing multiple-word messages to application firmware.

  • Page 43: I 2 C Write Protocol

    SCP1_CLK and release the data line, SCP1_SDA. 6. If the master has no more data words to write to the CS4953xx, then proceed to Step 8. If the master has more data words to write to the CS4953xx, then proceed to Step 7.

  • Page 44: Figure 3-9. I 2 C Read Flow Diagram

    I2C Port CS4953xx Hardware Users Manual START SCP1_IRQ (LOW)? SEND I2C START: DRIVE SCP1_SDA LOW WHILE SCP1_CLK IS HIGH WRITE ADDRESS BYTE 0x81 SCP1_SDA == EXIT (ERROR) ACK? READ DATA BYTE SEND ACK BYTES READ = 4? SCP1_IRQ LOW? SEND NACK...

  • Page 45: I 2 C Read Procedure

    4. After the address byte, the master must release the data line and provide a ninth clock for the CS4953xx DSP (slave) to acknowledge (ACK) receipt of the byte. The CS4953xx will drive the data line low during the ninth clock to acknowledge.
  • Page 46 Start SCP1_CLK SCP1_SDA 7-bit Address Data Byte 3 (MSB) Data Byte 2 Data Notes: The I C slave is always responsible for driving the ACK for the address byte. Figure 3-10. Sample Waveform for I C Write Functional TIming Note: The I2C slave is always responsible for driving the ACK for the address byte. Stop 7-bit Address Data Byte 3 (MSB)

  • Page 47: Scp1_Irq Behavior

    SCP1_IRQ is guaranteed to remain low (once it has gone low), until the falling edge of SCP1_CLK for the last bit of the last byte to be transferred out of CS4953xx (that is, the rising edge of SCP1_CLK before the ACK). If there is no more data to be transferred, SCP1_IRQ will go high at this point.

  • Page 48: Table 3-2. Serial Control Port Spi Signals

    SPI Port CS4953xx Hardware Users Manual Table 3-2 shows the signal names, descriptions, and pin number of the signals associated with the SPI Serial Control Port on the CS4953xx. Table 3-2. Serial Control Port SPI Signals LQFP-144 LQFP-128 Pin Name...

  • Page 49: Spi System Bus Description

    Data is transferred with the most-significant bit (MSB) first. For the CS4953xx slave SPI port, the first byte is an address byte that is always sent by the master after a Start condition. This address byte is an “I C-type”...

  • Page 50: Spi Messaging

    CS4953xx Hardware Users Manual If the SPI transaction is a write from master to the CS4953xx (R/W = 0, Address = 0x80), then the master will clock the SCP1_CLK signal and drive the SCP1_MOSI signal with data bytes for the CS4953xx to read. If the SPI transaction is a read to the master from the CS4953xx (R/W = 1, Address = 0x81), then the master will drive the SCP1_CLK signal and read the SCP1_MISO signal with the data bytes from the CS4953xx.

  • Page 51: Performing A Serial Spi Write

    4. If the master has no more data words to write to the CS4953xx, then proceed to Step 6. If the master has more data words to write to the CS4953xx, then proceed to Step 5.

  • Page 52: Performing A Serial Spi Read

    Information provided in this section is intended as a functional description indicating how an external device (Master) performs an SPI read from the CS4953xx (slave). The system designer must ensure that all timing constraints of the SPI read cycle are met (see the CS4953xx datasheet for timing specifications).

  • Page 53: Spi Read Protocol

    The serial clock should be held low so that eight transitions from low-to-high-to-low will occur for each byte. 5. If SCP1_IRQ is still low after 4 bytes, then proceed to Step 4 and read another 4 bytes out of the CS4953xx slave.

  • Page 54: Figure 3-19. Sample Waveform For Spi Read Functional Timing

    SCP1_CS SCP1_CLK SCP1_MOSI 7-bit Address Data Byte 3 (MSB) Data Byte 2 Figure 3-19. Sample Waveform for SPI Read Functional Timing SCP1_CS SCP1_CLK SCP1_MOSI 7-bit Address SCP1_MISO Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) SCP1_IRQ Figure 3-20.

  • Page 55: Scp1_Irq Behavior

    SCP1_IRQ is guaranteed to remain low (once it has gone low), until the rising edge of SCP1_CLK for the last bit of the last byte to be transferred out of CS4953xx. If there is no more data to be transferred, SCP1_IRQ will go high at this point.
  • Page 56 SPI Port CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc 3-22...

  • Page 57: Chapter 4. Parallel Control Port

    The CS4953xx is equipped with an 8-bit Parallel Control Port that can be used for host communication, providing faster control throughput for the system. The Parallel Control Port is capable of Intel, Motorola, and Multiplexed Intel communication modes.
  • Page 58 CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc...

  • Page 59: Chapter 5. Digital Audio Input Interface

    This data sheet presents most of the modes available with the CS4953xx hardware. However, not all of the modes are available with any particular piece of application code. The Application Code User’s Guide for the particular code being used should be referenced to determine if a particular mode is supported.

  • Page 60: Supported Dai Functional Blocks

    Note:Currently not supported in the O/S. The Bursty Data Input (BDI) port on the CS4953xx shares pins with the DAI port pins, and is used for input of bursty compressed audio data. The compressed data is clocked in with a bit clock (BDI_CLK). Bursty compressed...

  • Page 61: Table 5-2. Bursty Data Input (Bdi) Pins

    Compressed Data DAI_LRCLK2 DAI_SCLK2 Unit DAI1_DATA4 audio data input requires the use of a “throttle” signal, BDI_REQ to signal to the host that the CS4953xx is capable of accepting data. Table 5-2. Bursty Data Input (BDI) Pins LQFP-144 LQFP-128 Pin Name...

  • Page 62: Digital Audio Formats

    DAI ports are programmed for slave operation, where DAIn_LRCLK and DAIn_SCLK are inputs only. This subsection describes some common audio formats that CS4953xx supports. It should be noted that the input ports use up to 32-bit PCM resolution and 16-bit compressed data word lengths.

  • Page 63: Dai Hardware Naming Convention

    DAI Hardware Configuration CS4953xx Hardware Users Manual used to initialize the format (for example, I S, left justified, and others) for digital data inputs, as well as the data format and clocking options for the digital output port. 5.2.1 DAI Hardware Naming Convention...
  • Page 64 DAI Hardware Configuration CS4953xx Hardware Users Manual Table 5-3. Input Data Format Configuration (Input Parameter A) (Continued) A Value Data Format Hex Message 0x81800020 0xFEFF0000 0x81400020 0x00001F00 0x81800021 0xFEFF0000 0x81400021 0x00001F00 0x81800022 0xFEFF0000 Left Justified 24-bit 0x81400022 0x00001F00 0x81800023 0xFEFF0000...

  • Page 65: Table 5-4. Input Sclk Polarity Configuration (Input Parameter B)

    DAI Hardware Configuration CS4953xx Hardware Users Manual Table 5-4. Input SCLK Polarity Configuration (Input Parameter B) SCLK Polarity B Value Hex Message (Both DAI and CDI Port) 0x81800020 0xFFDFFFFF 0x81800021 0xFFDFFFFF 0x81800022 0 (default) Data Clocked in on SCLK Rising Edge...

  • Page 66: Table 5-6. Input Dai Mode Configuration (Input Parameter D)

    DAI Hardware Configuration CS4953xx Hardware Users Manual Table 5-6. Input DAI Mode Configuration (Input Parameter D) D Value Description HEX Message 0x81000025 DAI2_LRCLK/SCLK – Slave 0 (default) Compressed Data in on DAI_D4 0x1008D110 0x81000025 DAI1_LRCLK/SCLK - Slave Compressed Data in on DAI_D0...

  • Page 67: Chapter 6. Direct Stream Data (Dsd) Input Interface

    1’s and 0’s on a single line. There is no framing clock (LRCLK), and there is only one channel per line. The CS4953xx supports internal conversion of DSD data to PCM which can then be processed by the DSP.

  • Page 68: Figure 6-1. Dsd Port Block Diagram

    Description of Digital Audio Input Port when Configured for DSD Input CS4953xx Hardware Users Manual DSD0 DSD_DATA0 DSD1 DSD_DATA1 DSD2 DSD_DATA2 DSD3 DSD_DATA3 DSD_CLK DSD4 DSD_DATA4 DSD5 DSD_DATA5 Figure 6-1. DSD Port Block Diagram §§ DS732UM7 Copyright 2008 Cirrus Logic, Inc...

  • Page 69: Chapter 7. Digital Audio Output Interface

    Digital Audio Output Interface The CS4953xx has two output ports - Digital Audio Output port 1 & 2 (DAO1 & DAO2). Each port can output 8 channels of up to 32-bit PCM data. The Digital Audio Output ports are both implemented with a modified 3-wire Inter-IC Sound (I S) interface along with an oversampling master clock (MCLK).

  • Page 70: Supported Dao Functional Blocks

    Digital Audio Output Port Description CS4953xx Hardware Users Manual DAO1_LRCLK is the data framing clock whose frequency is equal to the sampling frequency for the DAO1 data outputs. DAO1_DATA[3:0] are the data outputs and are typically configured for outputting two channels of I S or left- justified PCM data.

  • Page 71: Dao Interface Formats

    Philips ® Digital Interface Format (S/PDIF), also known as IEC60958, or the AES/EBU interface format. Please see Figure 7-1 for a block diagram of the supported functional blocks for the DAO on the CS4953xx 7.1.3 DAO Interface Formats The DAO interface has 8 stereo data outputs that are fully configurable including support for I S, left-justified, and multichannel (one-line data mode) formats.

  • Page 72: One-Line Data Mode Format (Multichannel)

    Digital Audio Output Port Description CS4953xx Hardware Users Manual 7.1.3.3 One-line Data Mode Format (Multichannel) The CS4953xx is capable of multiplexing all digital audio outputs on one line, as illustrated in Figure 7-4. This mode is available only through special request. Please contact your local Cirrus representative for further details.

  • Page 73: Table 7-2. Output Clock Mode Configuration (Parameter A)

    Digital Audio Output Port Description CS4953xx Hardware Users Manual Table 7-2 shows values and messages for DAO output clock mode configuration parameters. Table 7-2. Output Clock Mode Configuration (Parameter A) DAO 1 & 2 Modes (MCLK, LRCLK and Hex Message...
  • Page 74 Digital Audio Output Port Description CS4953xx Hardware Users Manual Table 7-4. Output DAO_SCLK/LRCLK Configuration (Parameter C) (Continued) C Value DAO_SCLK Frequency Hex Message 0x8100003D DAO_MCLK = 256 FS 0x00037700 0x8100003E DAO1_SCLK = DAO_MCLK / 1 = 256 FS 0x00037700 DAO1_LRCLK = DAO1_SCLK / 256 = FS...

  • Page 75: Table 7-5. Output Data Format Configuration (Parameter D)

    Digital Audio Output Port Description CS4953xx Hardware Users Manual Table 7-4. Output DAO_SCLK/LRCLK Configuration (Parameter C) (Continued) C Value DAO_SCLK Frequency Hex Message 0x8100003D DAO_MCLK = 384 FS 0x00037211 0x8100003E DAO1_SCLK = DAO_MCLK / 4 = 96 FS 0x00037211 DAO1_LRCLK = DAO1_SCLK / 96 = FS...

  • Page 76: Table 7-6. Output Dao_Lrclk Polarity Configuration (Parameter E)

    Digital Audio Output Port Description CS4953xx Hardware Users Manual Table 7-5. Output Data Format Configuration (Parameter D) DAO Data Format Of DAO_DATA0, 1, 2 (or DAO_DATA0 for Multichannel Hex Message Value Modes) 0x81000030 0x00000000 0x81000031 0x00000000 0x81000032 0x00000000 0x81000033 0x00000000...

  • Page 77: S/Pdif Transmitter

    Digital Audio Output Port Description CS4953xx Hardware Users Manual 7.1.5 S/PDIF Transmitter Two S/PDIF transmitters are provided on the XMTA and XMTB pins that can output an IEC60958-compliant S/ PDIF stream. The modulation clock source for the S/PDIF transmitter is the clock present on the DAO_MCLK pin.
  • Page 78 Digital Audio Output Port Description CS4953xx Hardware Users Manual Table 7-10. DSP Bypass Config DAO_SCLK Polarity Hex Message 0x81000052 Route XMTB_IN to DAO2_DATA3/XMTB 0x0000000b 0x81000052 Disable DSP Bypass 0x00000003 §§ DS732UM7 Copyright 2008 Cirrus Logic, Inc 7-10...

  • Page 79: Chapter 8. External Memory Interfaces

    External Memory Interfaces 8.1 SDRAM Controller The CS4953xx supports a glueless external SDRAM interface to extend the data and/or program memory of the DSP during runtime. The CS4953xx SDRAM controller provides two-port access to X, Y, and P memory space, a four- word read buffer, and a double-buffered four-word write buffer.

  • Page 80: Flash Controller Interface

    SD_DQM0, SD_CAS, SD_RAS, SD_CLKOUT, SD_CLKIN, SD_CLKEN). SD_CS is the SDRAM chip select pin. The address and data pins are shared with the Flash interface. The CS4953xx supports SDRAMs from 2 Mbytes to 64 Mbytes with various row, bank, and column configurations. The size can be configured in the DynamicConfig0...
  • Page 81 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-1. SDRAM Interface Signals (Continued) LQFP- LQFP- Signal Name Signal Description 144 Pin 128 Pin Pin Type SD_WE SDRAM Write Enable Output SD_A0/EXT_A0 SDRAM/Flash Address 0 Output SD_A1/EXT_A1 SDRAM/Flash Address 1 Output...

  • Page 82: Configuring Sdram/Flash Parameters

    Note: All External Memory Interface config messages must be sent to DSPB. For more details on sending messages to DSP B refer to AN288, section 2.1.4 Refer to External Memory Interface in the CS4953xx data sheet for timing parameters that are summarized inTable 8-2.
  • Page 83 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-2. SDRAM/Flash Controller Parameters (Continued) Mnemonic Hex Message CRUSConfig Bit 31:9 = 0 = Reserved 0x8100005D Bit 8 = Pin Mapping, where: 0xHHHHHHHH 0 = Enable Flash and SDRAM Mapping Default: 0x00000000...
  • Page 84 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-2. SDRAM/Flash Controller Parameters (Continued) Mnemonic Hex Message DynamictAPR Configure the last data out to active command time. 0x81000065 Bit 31:4 = 0 = Reserved 0xHHHHHHHH Bit 3:0 = Tapr, where: Default 0x00000000 0x0 to 0xE = (n + 1) DSP clk cycles.
  • Page 85 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-2. SDRAM/Flash Controller Parameters (Continued) Mnemonic Hex Message DynamictXSR Configure the exit self refresh to active command time. Bit 31:5 = 0 = Reserved 0x8100006A Bit 4:0 = Txsr, where: 0xHHHHHHHH 0x0 to 0x1E = (n + 1) DSP clk cycles.
  • Page 86 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-2. SDRAM/Flash Controller Parameters (Continued) Mnemonic Hex Message StaticConfig0 (Not Supported) Bit 31:2 = 0 = Reserved 0x81000070 Bit 1:0 = Memory Bus Width, where: 0xHHHHHHHH 00 = SRAM Memory bus 8 bits wide.
  • Page 87 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual Table 8-2. SDRAM/Flash Controller Parameters (Continued) Mnemonic Hex Message StaticWaitWen1 EXT_CS falling to EXT_WE falling (t xmcswe 0x81000078 Bit 31:4 = 0 = Reserved 0XHHHHHHHH Bit 3:0 = Flash_WEN_CYCLE, where: Default 0x00000000 0000 = one DSP clk cycle between the assertion of chip select and write enable.
  • Page 88 SDRAM/Flash Controller Interface CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc 8-10...

  • Page 89: Chapter 9. System Integration

    R such that R = (Z – 15), where 15 represents the source impedance of the CS4953xx drivers. The typical connection diagrams show “0.1uF x 8” to indicate that 1 decoupling capacitor should be placed next to each power pin.

  • Page 90: Figure 9-1. Lqfp-144, I 2 C Control, Serial Flash, Sdram, 7 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-1. LQFP-144, I C Control, Serial FLASH, SDRAM, 7 DACs...

  • Page 91: Figure 9-2. Lqfp-144, Spi Control, Serial Flash, Sdram, 7 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-2. LQFP-144, SPI Control, Serial FLASH, SDRAM, 7 DACs...

  • Page 92: Figure 9-3. Lqfp-144, Spi Control, Serial Flash, Sdram, 8 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-3. LQFP-144, SPI Control, Serial FLASH, SDRAM, 8 DACs...

  • Page 93: Figure 9-4. Lqfp-144, I2C Control, Parallel Flash, Sdram, 8 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-4. LQFP-144, I C Control, Parallel Flash, SDRAM, 8 DACs...

  • Page 94: Figure 9-5. Lqfp-128, Spi Control, Parallel Flash, Sdram, 8 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-5. LQFP-128, SPI Control, Parallel Flash, SDRAM, 8 DACs...

  • Page 95: Figure 9-6. Lqfp-128, I 2 C Control, Serial Flash, Dsd Audio Input, Sdram, 7 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-6. LQFP-128, I C Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs...

  • Page 96: Figure 9-7. Lqfp-144, Spi Control, Serial Flash, Dsd Audio Input, Sdram, 7 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-7. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs...

  • Page 97: Figure 9-8. Lqfp-144, Spi Control, Serial Flash, Dsd Audio Input, Sdram, 7 Dacs

    For 16-Mbit parts, SD_BA0 is used as a bank select. For 64-Mbit and 128-Mbit parts SD_BA[1:0] is the 2-bit bank select. Note Figure 9-8. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs...

  • Page 98: Pin Description

    9.2.1.1 Power The CS4953xx Family of DSPs take two supply voltages — the core supply voltage (VDD) and the I/O supply voltage (VDDIO). There is also a separate analog supply voltage required for the internal PLL (VDDA). These pins are described in the following tables and descriptions.

  • Page 99: Ground

    9.2.2.1 Analog Power Conditioning In order to obtain the best performance from the CS4953xx’s internal PLL, the analog power supply VDDA must be as noise free as possible. A ferrite bead and two capacitors should be used to filter the VDDIO to generate VDDA.

  • Page 100: Pll

    9.2.3 PLL The internal phase locked loop (PLL) of the CS4953xx requires an external current reference resistor. The resistor is used to calibrate the PLL and must meet the tolerances specified below. The layout topology is shown in the typical connection diagrams.

  • Page 101: Control

    Figure 9-10. Crystal Oscillator Circuit Diagram 9.4 Control The CS4953xx supports 5 control interface protocols: SPI, I C, Motorola parallel, Intel parallel, and Multiplexed Intel parallel mode. All slave serial control modes between the DSP and the host microcontroller use the Serial Control Port 1 (SCP1) pins.

  • Page 102: Table 9-8. Reset Pin

    The specifications of the messaging protocol used by the O/S can be found in AN288, “CS4953xx Firmware User’s Manual”. The system designer only needs to read the subsection describing the communication mode being used.

  • Page 103: 144-Pin Lqfp Pin Assigments

    144-Pin LQFP Pin Assigments CS4953xx Hardware Users Manual 9.5 144-Pin LQFP Pin Assigments Figure 9-11 shows the 144-Pin LQFP Pin Layout. SD_A0, EXT_A0 GPIO9, PCP_A1 / A9 SD_A1, EXT_A1 GPIO8, PCP_A0 / A8 SD_A2, EXT_A2 GPIO7, PCP_AD7 / D7 GND4...

  • Page 104: 128-Pin Lqfp Pin Assigments

    128-Pin LQFP Pin Assigments CS4953xx Hardware Users Manual 9.6 128-Pin LQFP Pin Assigments Figure 9-12 shows the 128-Pin LQFP Pin Layout. SD_A0, EXT_A0 GPIO38, SCP2_CLK GPIO11, SCP2_MISO / SDA SD_A1, EXT_A1 GPIO10, SCP2_MOSI VDDIO5 SD_A2, EXT_A2 GPOI9, SCP1_IRQ GND4 GPIO8, SCP2_IRQ...

  • Page 105: Pin Assignments

    9.7 Pin Assignments Table 9-10 shows the names and functions for each pin. Table 9-10. Pin Assignments LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions...
  • Page 106 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions Serial PCM Audio Sample Rate Clock for the serial data pins: General Purpose Input/ 3.3V GPIO23...
  • Page 107 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 3.3V SD_D6 SDRAM Data Bit 6 EXT_D6 Flash Data Bit 6. BiDir (5V tol) 3.3V...
  • Page 108 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions GNDIO3 I/O ground 3.3V SD_D9 SDRAM Data Bit 9 EXT_D9 Flash Data Bit 9 BiDir...
  • Page 109 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 3.3V EXT_CS2 Chip Select 2 (5V tol) VDD4 Core power supply voltage 1.8V 3.3V SD_A4...
  • Page 110 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 3.3V EXT_A15 Flash Address Bit 15 (5V tol) VDD5 Core power supply voltage 1.8V 3.3V...
  • Page 111 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions VDD6 Core power supply voltage 1.8V General Purpose Input/ 3.3V BiDir/ GPIO35...
  • Page 112 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 1. SPI Mode Master Data Input/ Slave Data Output General Purpose Input/ 1.
  • Page 113 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 1. Parallel Control Port Data Bus General Purpose Input/ 1.
  • Page 114 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions General Purpose Input/ 3.3V GPIO2 1. UART_TXD 1. UART Output BiDir Output (5V tol)
  • Page 115 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions General Purpose Input/ 1. DAI1_DATA2 1. PCM Audio Input Data 2 3.3V GPIO13 BiDir...
  • Page 116 Table 9-10. Pin Assignments (Continued) LQFP LQFP Pullup -144 -128 Function 1 Description of Default Reset Secondary Functions Description of Secondary Pin # Pin # (Default) Function Type State Reset Functions 1. Digital Audio Output 3. 1. DAO2_DATA3 2. Outputs IEC60958/61937 General Purpose Input/ 3.3V GPIO26...

  • Page 117: Revision History

    C Control, Serial FLASH, DSD Audio Input, SDRAM, 7 DACs.” Modified description of May 7, 2008 firmware modules offered on the CS4953xx platform on page 1-3. Updated list of sample rates supported for the Digital Audio Port in Section 6.1, "Description of Digital Audio Input Port when Configured for DSD Input"...

  • Page 118: Ds732Um7 Copyright 2008 Cirrus Logic, Inc

    Revision History CS4953xx Hardware Users Manual DS732UM7 Copyright 2008 Cirrus Logic, Inc 9-30...

Table of Contents