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Cirrus Logic CS5550 Manual

Two-channel, low-cost a/d converter
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Two-channel, Low-cost A/D Converter
Features
Power Consumption <12 mW
- with VD+ = 3.3 V
Adjustable Input Range on AIN1
GND-referenced Signals with Single Supply
On-chip 2.5 V Reference (25 ppm/°C typ)
Simple Three-wire Digital Serial Interface
Power Supply Configurations
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
VA+
AIN1+
+
10x,50x
AIN1-
-
+
AIN2+
10x
-
AIN2-
VREFIN
x1
VREFOUT
AGND
http://www.cirrus.com
±
4th Order ∆Σ
Modulator
2nd Order ∆Σ
Modulator
Voltage
Reference
Copyright © Cirrus Logic, Inc. 2005
Description
The CS5550 combines two ∆Σ ADCs and a serial
interface on a single chip. The CS5550 has
on-chip functionality to facilitate offset and gain
calibration. The CS5550 features a bi-directional
serial interface for communication with a
microcontroller.
ORDERING INFORMATION:
CS5550-IS
CS5550-ISZ -40°C to +85°C, Lead-free
RESET
Calibration
Digital
Registers
Filter
Config
Register
Output
Digital
Registers
Filter
Clock
Generator
XIN XOUT CPUCLK
(All Rights Reserved)
CS5550
-40°C to +85°C
VD+
Serial
Interface
DGND
24-pin SSOP
24-pin SSOP
CS
SDI
SDO
SCLK
INT
MAR '05
DS630F1

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Summary of Contents for Cirrus Logic CS5550

  • Page 1 CS5550 Two-channel, Low-cost A/D Converter Features Description The CS5550 combines two ∆Σ ADCs and a serial Power Consumption <12 mW interface on a single chip. The CS5550 has - with VD+ = 3.3 V on-chip functionality to facilitate offset and gain ±...

  • Page 2: Table Of Contents

    2.1.1 High-Rate Digital Low-Pass Filters ..............10 2.1.2 Digital Compensation Filters ................10 2.1.3 Gain and Offset Adjustment ................10 2.2 Performing Measurements ....................10 2.3 CS5550 Linearity Performance ..................10 3. FUNCTIONAL DESCRIPTION ....................11 3.1 Analog Inputs ........................11 3.2 Voltage Reference ......................11 3.3 Oscillator Characteristics ....................

  • Page 3: List Of Figures

    FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

  • Page 4: Pin Description

    CS5550 1. PIN DESCRIPTION Crystal Out XOUT Crystal In CPU Clock Output CPUCLK Serial Data Input Positive Power Supply TSTO Test Output Digital Ground DGND TSTO Test Output Serial Clock SCLK Interrupt Serial Data Ouput RESET Reset Chip Select TSTO...

  • Page 5: Characteristics/Specifications

    CS5550 2. CHARACTERISTICS/SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over all Operating Conditions. • Typical characteristics and specifications are measured at nominal supply voltages and T = 25°C. • DGND = 0 V. All voltages with respect to 0 V.

  • Page 6: Voltage Reference

    Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS5550 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test.

  • Page 7: Digital Characteristics

    CS5550 5 V DIGITAL CHARACTERISTICS Parameter Symbol Unit High-Level Input Voltage All Pins Except XIN and SCLK and RESET 0.6 VD+ (VD+) - 0.5 SCLK and RESET 0.8 VD+ Low-Level Input Voltage All Pins Except XIN and SCLK and RESET SCLK and RESET 0.2 VD+...

  • Page 8: Switching Characteristics

    CS5550 SWITCHING CHARACTERISTICS Parameter Symbol Unit Master Clock Frequency Internal Gate Oscillator (Note 7) MCLK 4.096 Master Clock Duty Cycle CPUCLK Duty Cycle (Note 8) Rise Times Any Digital Input Except SCLK µs rise (Note 9) SCLK µs Any Digital Output...

  • Page 9: Figure 1. Cs5550 Read And Write Timing Diagrams

    CS5550 DS630F1...

  • Page 10: Theory Of Operation

    Table 2. Available range of ±0.1% output words represent a normalized value between -1 linearity, with default settings in the and +1. The unsigned data in the CS5550 output gain/offset registers. registers represent normalized values between 0 Table 2 lists the range of input levels (as a percent- and 1.

  • Page 11: Functional Description

    If higher accuracy/stability is required, an full-scale input voltage ranges. external reference can be used. Note that until the CS5550 is calibrated (see Cali- 3.3 Oscillator Characteristics bration) the accuracy of the CS5550 is not guaran- XIN and XOUT are the input and output of an in- teed to within 0.1%.

  • Page 12: Calibration

    AIN1/AIN2 Gain Registers must be set to default (1.0) before running the gain calibration(s), and the value in put signal is low enough that it causes the CS5550 the Offset Registers must be set to default (0) before to attempt to set either gain register higher than 4, running offset calibrations.

  • Page 13: Gain Calibration Sequence

    Status Register are re- voltage applied across the “+’ and “-” inputs, the turned to their inactive state. CS5550 determines the Gain Register value by av- eraging the Digital Output Register’s output signal values over one computation cycle (N samples) and then dividing this average into 1.

  • Page 14: Pcb Layout

    DCLK cycle (DCLK = MCLK / K). Place the analog-digital plane split immediately ad- jacent to the digital portion of the chip. 3.6 PCB Layout The CS5550 should be placed entirely over an an- alog ground plane with both the AGND and DGND DS630F1...

  • Page 15: Serial Port Overview

    CS5550. Commands that write to a register must be followed by 3 bytes of register data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute before the original read is completed).
  • Page 16 In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5550 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal.
  • Page 17 CS5550 4.1.7 Register Read/Write The Read/Write command informs the state machine that a register access is required. During a read operation, the addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the data is clocked into the input buffer and, and all 24 bits are transferred to the addressed register on the 24 SCLK.

  • Page 18: Serial Port Interface

    Register. The CS5550 will then acquire the ter initial power-on of the device. The CS5550 will serial data input from the (SDI) pin when the user then assume its active state. (The term active state, pulses the serial clock (SCLK) 24 times.

  • Page 19: Serial Port Initialization

    SCLK input. If this occurs, any attempt to clock valid CS5550 1) Power on the CS5550. (Or if the device is al- commands into the serial interface will result in ei- ready powered on, recycle the power.)

  • Page 20: Register Description

    CS5550 5. REGISTER DESCRIPTION 1. “Default**” => bit status after power-on or reset 2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits. 5.1 Configuration Register Address: 0 gain IMODE...

  • Page 21: Offset Registers

    CS5550 5.2 Offset Registers Address: 1 (Offset Register - AIN1) 3 (Offset Register - AIN2) ..Default** = 0.000 The Offset Registers are initialized to zero on reset, allowing the device to function and perform measurements. The register is loaded after one computation cycle with the offset when the proper input is applied and the Cal- ibration Command is received.

  • Page 22: Out1 And Out2 Output Registers

    CS5550 5.5 OUT and OUT Output Registers Address: 7 (AIN1 Output Register) 8 (AIN2 Output Register) ..These signed registers contain the last value of the measured results of AIN1 and AIN2. The results will be with- in the range of -1.0 ≤ AIN1,AIN2 < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (MSB has a negative weighting).

  • Page 23: Control Register

    CS5550 small to fit in the AIN Output Register. CRDY Conversion Ready. Indicates a new conversion is ready. OD1, OD2 Modulator oscillation detect. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the Input Voltage Range.

  • Page 24: Package Dimensions

    CS5550 6. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING ∝ END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE 0.084 2.13 0.002 0.006 0.010 0.05 0.13 0.25 0.064 0.068 0.074 1.62 1.73 1.88 0.009 0.015 0.22 0.38...