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24-bit ADC
Features
& Description
Chopper-stabilized Instrumentation
Amplifier, 64X
• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current
Digital Gain Scaling up to 40x
Delta-sigma Analog-to-digital Converter
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits
Scalable V
Input: Up to Analog Supply
REF
Simple Three-wire Serial Interface
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK)
Onboard Offset and Gain Calibration
Registers
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V
VA+
AIN1+
AIN1-
VA-
http://www.cirrus.com
with
C1
C2
VREF+
DIFFERENTIAL
64X
4
LATCH
A0
A1
Copyright Cirrus Logic, Inc. 2009
Ultra-low-noise Amplifier
General Description
The CS5530 is a highly integrated ΔΣ Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale,
process
applications.
To accommodate these applications, the ADC includes
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/√Hz @ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order ΔΣ modulator fol-
lowed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADC and a micro-
controller, the converter includes a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution
applications.
ORDERING INFORMATION
See page 35.
VREF-
PROGRAMMABLE
TH
ORDER ΔΣ
SINC FIR FILTER
MODULATOR
CLOCK
GENERATOR
OSC1
(All Rights Reserved)
control,
scientific,
for
weigh
scale
and
VD+
SERIAL
INTERFACE
CALIBRATION
SRAM/CONTROL
LOGIC
OSC2
CS5530
and
medical
process
control
CS
SDI
SDO
SCLK
DGND
NOV '09
DS742F3
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Summary of Contents for Cirrus Logic CS5530
- Page 1 24-bit ADC Ultra-low-noise Amplifier with Features & Description General Description The CS5530 is a highly integrated ΔΣ Analog-to-Digital Chopper-stabilized Instrumentation Converter (ADC) which uses charge-balance techniques Amplifier, 64X to achieve 24-bit performance. The ADC is optimized for • 12 nV/√Hz @ 0.1 Hz (No 1/f noise) measuring low-level unipolar or bipolar signals in weigh •...
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Page 2: Table Of Contents
CS5530 TABLE OF CONTENTS CHARACTERISTICS AND SPECIFICATIONS ..............4 ANALOG CHARACTERISTICS................4 TYPICAL NOISE-FREE RESOLUTION (BITS) ............6 5 V DIGITAL CHARACTERISTICS ................7 3 V DIGITAL CHARACTERISTICS ................7 DYNAMIC CHARACTERISTICS ................8 ABSOLUTE MAXIMUM RATINGS ................8 SWITCHING CHARACTERISTICS ................9 GENERAL DESCRIPTION .................... - Page 3 Figure 16. Z-Transforms of Digital Filters................27 Figure 17. On-chip Oscillator Model..................28 Figure 18. CS5530 Configured with a Single +5 V Supply ............. 29 Figure 19. CS5530 Configured with ±2.5 V Analog Supplies..........29 Figure 20. CS5530 Configured with ±3 V Analog Supplies............. 30 LIST OF TABLES Table 1.
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Page 4: Characteristics And Specifications
CS5530 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARCTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode) (See Notes 1 and 2.) - Page 5 CS5530 ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) Parameter Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode (VA-) + 1.6 (VA+) - 1.6 CVF Current on AIN+ or AIN- 1200 Input Current Noise pA/√Hz...
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Page 6: Typical Noise-Free Resolution (Bits)
CS5530 ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) CS5530-CS Parameter Unit Power Supplies DC Power Supply Currents (Normal Mode) Power Consumption Normal Mode (Note 7) Standby Sleep µW Power Supply Rejection (Note 8) DC Positive Supplies DC Negative Supply 7. -
Page 7: Digital Characteristics
CS5530 5 V DIGITAL CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.) Parameter Symbol Unit High-Level Input Voltage All Pins Except SCLK 0.6 VD+ SCLK (VD+) - 0.45 Low-Level Input Voltage... -
Page 8: Dynamic Characteristics
CS5530 DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Unit Modulator Sampling Rate MCLK/16 Filter Settling Time to 1/2 LSB (full-scale Step Input) Single Conversion mode (Notes 12, 13, and 14) 1/OWR Continuous Conversion mode, OWR < 3200 Sps 5/OWR + 3/OWR sinc5 Continuous Conversion mode, OWR ≥... -
Page 9: Switching Characteristics
CS5530 SWITCHING CHARACTERISTICS (VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C = 50 pF;... -
Page 10: Figure 1. Sdi Write Timing (Not To Scale)
CS5530 S D I M S B M S B -1 L S B S C L K Figure 1. SDI Write Timing (Not to Scale) S D O M S B M S B -1 LS B S C L K Figure 2. -
Page 11: General Description
For physical input capacitance see ‘Input Capacitance’ specification under 2.1 Analog Input Analog Characteristics. Figure 3 illustrates a block diagram of the CS5530. The front end includes a chopper-stabilized instru- mentation amplifier with a gain of 64X. VREF+ VREF- 1000 Ω... -
Page 12: Analog Input Span
Port Initialization sequence. This sequence re- 2.1.3 No Offset DAC sets the serial port to the command mode and is An offset DAC was not included in the CS5530 be- accomplished by transmitting at least 15 SYNC1 cause the high dynamic range of the converter command bytes (0xFF hexadecimal), followed by eliminates the need for one. -
Page 13: Figure 6. Cs5530 Register Diagram
Serial Interface SCLK Configuration Register (1 x 32) Power Save Select Command Reset System Register (1 × 8) Input Short Voltage Reference Select Output Latch Filter Rate Select Word Rate Unipolar/Bipolar Open Circuit Detect Figure 6. CS5530 Register Diagram DS742F3... -
Page 14: Command Register Descriptions
CS5530 2.2.2 Command Register Descriptions READ/WRITE OFFSET REGISTER D7(MSB) R/W (Read/Write) Write offset register. Read offset register. READ/WRITE GAIN REGISTER D7(MSB) R/W (Read/Write) Write gain register. Read gain register. READ/WRITE CONFIGURATION REGISTER D7(MSB) Function: These commands are used to read from or write to the configuration register. - Page 15 CS5530 SYNC0 D7(MSB) Function: End of the serial port re-initialization sequence. NULL D7(MSB) Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. DS742F3...
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Page 16: Serial Port Interface
CS5530 2.2.3 Serial Port Interface The CS5530’s serial interface consists of four con- SCLK, Serial Clock, is the serial bit-clock which trol lines: CS, SDI, SDO, SCLK. Figure 7 details controls the shifting of data to or from the ADC’s the command and data word timing. -
Page 17: Reading/Writing On-Chip Registers
“normal mode”, is entered after power is ap- the configuration register that can be set when ini- plied. In this mode, the CS5530 typically consumes tiating a reset (i.e. a second write command is need- 35 mW. The other two modes are referred to as the ed to set other bits in the Configuration Register power save modes. -
Page 18: Output Latch Pins
CS5530 φ Fine φ Fine φ Coarse φ Coarse VREF VREF C = 7 pF C = 14pF ≤ 16 mV ≤ 8 mV i = fV i = fV MCLK MCLK VRS = 1; 1 V ≤ V ≤ 2.5 V ≤... -
Page 19: Configuration Register Description
CS5530 2.3.10 Configuration Register Description D31(MSB) D30 WR0 UP/BP OCD PSS (Power Save Select)[31] Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive). PDW (Power Down Mode)[30] Normal Mode Activate the power save select mode. RS (Reset System)[29] Normal Operation. - Page 20 CS5530 WR3-WR0 (Word Rate) [14:11] The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will scale linearly with the clock frequency used. The very first conversion using continuous conversion mode will last longer, as will conversions done with the single conversion mode. See the section on Performing Conversions and Tables 1 and 2 for more details.
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Page 21: Calibration
2.4.1 Calibration Registers where the binary numbers have a value of either The CS5530 converter has an offset register that is zero or one (b is the binary value of bit D29). used to set the zero point of the converter’s transfer While gain register settings of up to 64 - 2 function. -
Page 22: Performing Calibrations
CS5530 2.4.4 Performing Calibrations represent ground and full-scale. When a system off- set calibration is performed, a ground referenced sig- To perform a calibration, the user must send a com- nal must be applied to the converter. Figure 10 mand byte with its MSB=1, and the appropriate illustrates system offset calibration. -
Page 23: Limitations In Calibration Range
When the device is used without calibration, the 2.5 Performing Conversions uncalibrated gain accuracy is about ±1 percent. The CS5530 offers two distinctly different conver- Note that the gain from the offset register to the sion modes. The paragraphs that follow detail the output is 1.83007966 decimal, not 1. -
Page 24: Continuous Conversion Mode
CS5530 SCLKs are required to clock out the last conversion Table 1. Conversion Timing for Single Mode before the converter returns to command mode. Clock Cycles The number of clock cycles a continuous conver- (WR3-WR0) FRS = 0 FRS = 1... -
Page 25: Using Multiple Adcs Synchronously
SDI and SCLK). The CS5530 output data conversions in binary for- mat when operating in unipolar mode and in two's 4) A start conversion command must be sent to all complement when operating in bipolar mode. -
Page 26: Conversion Data Output Descriptions
CS5530 2.7.1 Conversion Data Output Descriptions CS5530 (24-BIT CONVERSIONS) D31(MSB) D30 Conversion Data Bits [31:8] These bits depict the latest output conversion. OF (Over-range Flag Bit) [2] Bit is clear when over-range condition has not occurred. Bit is set when input signal is more positive than the positive full-scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full-scale (bipolar mode). -
Page 27: Digital Filter
CS5530 2.8 Digital Filter The CS5530 has a linear phase digital filter which except for the 3200 Sps and 3840 Sps (MCLK = is programmed to achieve a range of output word 4.9152 MHz) rate. The Z-transforms of the two fil- rates (OWRs) as stated in the Configuration Regis- ters are shown in Figure 16. -
Page 28: Clock Generator
2.9 Clock Generator 2.10 Power Supply Arrangements The CS5530 includes an on-chip inverting amplifi- The CS5530 is designed to operate from single or er which can be connected with an external crystal dual analog supplies and a single digital supply. -
Page 29: Figure 18. Cs5530 Configured With A Single +5 V Supply
AIN1+ Serial 2 AIN1- Data Interface SCLK 7 A0 8 A1 VA - DGND Figure 18. CS5530 Configured with a Single +5 V Supply +2.5 V +3 V ~ +5 V Analog Digital 0.1 µF 0.1 µF Supply Supply Optional... -
Page 30: Figure 20. Cs5530 Configured With ±3 V Analog Supplies
Optional OSC2 VREF+ Clock Source VREF- 4.9152 MHz OSC1 22 nF CS5530 AIN1+ Serial 2 AIN1- Data Interface SCLK 7 A0 8 A1 VA - DGND -3 V Analog Supply Figure 20. CS5530 Configured with ±3 V Analog Supplies DS742F3... -
Page 31: Getting Started
Calibrations or conversions can then be performed before the start of the processor’s ADC initializa- as appropriate. tion code. Next, since the CS5530 does not provide 2.12 PCB Layout a power-on-reset function, the user must first ini- For optimal performance, the CS5530 should be tialize the ADC to a known state. -
Page 32: Pin Descriptions
CS5530 3. PIN DESCRIPTIONS DIFFERENTIAL ANALOG INPUT AIN1+ DIFFERENTIAL ANALOG INPUT AIN1- CS5530 AMPLIFIER CAPACITOR CONNECT VREF+ VOLTAGE REFERENCE INPUT AMPLIFIER CAPACITOR CONNECT VREF- VOLTAGE REFERENCE INPUT POSITIVE ANALOG POWER DGND DIGITAL GROUND NEGATIVE ANALOG POWER POSITIVE DIGITAL POWER LOGIC OUTPUT (ANALOG) -
Page 33: Measurement And Reference Inputs
CS5530 Measurement and Reference Inputs AIN1+, AIN1- – Differential Analog Input Differential input pins into the device. VREF+, VREF- – Voltage Reference Input Fully differential inputs which establish the voltage reference for the on-chip modulator. C1, C2 – Amplifier Capacitor Inputs Connections for the instrumentation amplifier’s capacitor. -
Page 34: Package Drawings
CS5530 5. PACKAGE DRAWINGS 20 PIN SSOP PACKAGE DRAWING ∝ END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW NOTE INCHES MILLIMETERS 0.084 2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 0.009 0.015 0.22 0.38 0.272 0.295 6.90... -
Page 35: Ordering Information
CS5530 6. ORDERING INFORMATION Model Number Bits Channels Linearity Error (Max) Temperature Range Package ±0.003% CS5530-IS -40°C to +85°C 20-pin 0.2" Plastic SSOP ±0.003% CS5530-ISZ -40°C to +85°C 20-pin 0.2" Plastic SSOP, Lead Free 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION... - Page 36 CLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
- Page 37 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic CS5530-ISZ CS5530-ISZR...
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