Table of Contents
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System Features
• Enhanced oversampling DAC architecture
— 32-bit resolution
— Up to 384-kHz sampling rate
— Low clock jitter sensitivity
— Auto mute detection
• Integrated high performance outputs
— 130-dB dynamic range (A-weighted)
— –108-dB total harmonic distortion + noise (THD+N)
— 110-dB interchannel isolation
• Headphone detection
— Headphone plug-in detection
®
— Popguard
technology eliminates pop noise
• Integrated PLL
— Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/
19.2-, 12-/24-, and 13-/26-MHz system MCLK rates
— Reference clock sourced from XTI/MCLK pin
— System clock output
• Mono mode support
• I
2
C control—up to 1 MHz
Interrupt
Sources
CLKOUT
XTAL
XTO
OSC
XTI/MCLK
SCLK1
LRCK1
SDIN1
DSDCLK/SCLK2
DSDB/LRCLK2
DSDA/SDIN2
http://www.cirrus.com
130-dB, 32-Bit High-Performance DAC
TSO
Digital Core
Interpolation
PLL
Interpolation
ASP
DoP to
DSD
XSP/DSD
Engine
Audio
Interface
Register /Hardware
Control Port Level Translator
Configuration
ADR
Copyright Cirrus Logic, Inc. 2015–2016
(All Rights Reserved)
• Direct Stream Digital (DSD
— Patented DSD processor
– On-chip 50-kHz filter to meet Scarlet Book Super
Audio Compact Disk (SACD) recommendations
– Matched PCM and DSD analog output levels
– Nondecimating volume control with 0.5-dB step size
and soft ramp
– DSD and Pulse-code modulation (PCM) mixing for
alerts
— Dedicated DSD and DoP pin interface
• Serial audio input path
— Five selectable digital filter responses
– Low-latency mode minimizes pre-echo
– 110 dB of stopband attenuation
— Supports sample rates from 32 to 384 kHz
— I
2
S, right-justified, left-justified, TDM, and
DSD-over-PCM (DoP) interface
— Master or slave operation
— Volume control with 0.5-dB step size and soft ramp
— 44.1 kHz deemphasis and inverting feature
• 40-pin QFN or 42-ball CSP package option
Applications
• Smart phones, tablets, portable media players, laptops,
digital headphones, powered speakers, AVR, home
theater systems, Blu-ray/DVD/SACD players and pro
audio
Interface
Internal
Supply (VL)
Supply (VD)
+1.8V
+1.8V
FILT +
Digital LDOs
Reference
Filter and
Multibit
Volume
Control
Modulator
Filter and
Multibit
Volume
Control
Modulator
DSD
Processor
SDA
SCL
RESET
CS4399
®
) path
Analog Supply
(VA,VCP)
Battery Supply
FILT-
+1.8V
Internal
Voltage
Charge Pump
VCP_FILT+
VA
DAC and Filter
-VA
VCP_FILT -
VCP_FILT+
VA
DAC and Filter
-VA
VCP_FILT -
Popguard®
HPDETECT
Circuitry
(VP)
FLYC_VCP
FLYP_VCP
FLYN _VCP
VCP_FILT+
VCP_FILT -
FLYP_VA
FLYN_VA
-VA
AOUTA
REFA
AOUTB
REFB
HP_DETECT
DS1113F1
DEC '16
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Related Manuals for Cirrus Logic CS4399
Summary of Contents for Cirrus Logic CS4399
- Page 1 LRCK1 REFB VCP_FILT - SDIN1 DoP to DSDCLK/SCLK2 XSP/DSD DSDB/LRCLK2 Engine Audio Processor Interface DSDA/SDIN2 Popguard® HPDETECT HP_DETECT Circuitry Register /Hardware Control Port Level Translator Configuration RESET Copyright Cirrus Logic, Inc. 2015–2016 DS1113F1 (All Rights Reserved) DEC ‘16 http://www.cirrus.com...
- Page 2 PLL allows for maximum clocking flexibility in any system. Popguard ® technology eliminates output transients upon power-up or power-down events. The CS4399 is available in a commercial-grade 42-ball WLCSP or 40-pin QFN package for operation from –10°C to +70°C. DS1113F1...
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Page 3: Table Of Contents
3 Characteristics and Specifications ..... 11 5.6 CS4399 Analog Output and Filtering ....49 Table 3-1. -
Page 4: Pin Assignments And Descriptions
CS4399 1 Pin Assignments and Descriptions 1 Pin Assignments and Descriptions 1.1 40-Pin QFN (Top-Down, Through-Package View) SDIN1 DSDB/LRCK2 RESET FILT+ FILT– FLYP_VCP GNDA FLYC_VCP –VA HP_DETECT Top-Down (Through Package ) View 40-Pin QFN Package FLYP_VA VCP_FILT+ Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram... -
Page 5: 42-Ball Wlcsp (Top-Down, Through-Package View)
CS4399 1.2 42-Ball WLCSP (Top-down, Through-Package View) 1.2 42-Ball WLCSP (Top-down, Through-Package View) SCLK1 XTI/MCLK DSDA/ SDIN1 SDIN2 DSDCLK/ CLKOUT LRCK1 SCLK2 DSDB/ GNDD RESET LRCK2 FILT+ FILT– FLYP_VCP VCP_FILT+ REFB REFA GNDA –VA FLYC_VCP GNDCP GNDCP HP_DETECT FLYP_VA FLYN_VCP VCP_FILT–... -
Page 6: Pin Descriptions
I Software Clock (I²C). Serial control interface clock used to clock — — Hysteresis control data bits into and out of the CS4399. on CMOS input XTI/MCLK I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input Weak —... - Page 7 CS4399 1.3 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) WLCSP Power Internal Digital I/O Digital I/O Pin Name Pin Description Pin # Ball Supply Connection Driver Receiver Ground GNDD I Digital and I/O Ground. Ground for the I/O and core logic. GNDA, —...
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Page 8: Electrostatic Discharge (Esd) Protection Circuitry
1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS4399 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device. - Page 9 CS4399 1.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) Signal Name ESD Domain Topology (See * in Topology Figures for Pad) VA/–VA FLYN_VA FLYP_VA FILT+ FILT– GNDA Substrate –VA VP/GNDCP RESET VCP_FILT+/VCP_FILT– Domain VP/GNDCP Domain VCP_FILT+ VP/VCP_FILT– FLYP_VCP...
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Page 10: Typical Connection Diagram
CS4399 2 Typical Connection Diagram 2 Typical Connection Diagram Battery +1.8 V (3.0 V—5.25 V) 0.1 µF 0.1 µF 4.7 µF FILT+ 0.1 µF 15 µF +1.8 V Audio CLKOUT 2.2 µF 2.2 µF Devices 15 µF FILT- FLYP_VA XTI / MCLK 2.2 µF... -
Page 11: Characteristics And Specifications
1.Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 2.The maximum over/undervoltage is limited by the input current. 3.Table 1-1 lists the power supply domain in which each CS4399 pin resides. 4.VCP_FILT± is specified in Table 3-13. - Page 12 Fig. 2-1 shows CS4399 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA = VCP = 1.8 V;...
- Page 13 Click/pop during PDN_HP enable or disable A-weighted — — –60 1.This table also applies to external VCP_FILT supply mode: CS4399 power up procedure is per description in Section 5.10.1; EXT_VCPFILT = 1; VCP_ FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1;...
- Page 14 CS4399 3 Characteristics and Specifications Table 3-5. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Cont.) Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.
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Page 15: Filter Response
CS4399 3 Characteristics and Specifications 6. For Single-Speed Mode, the measurement bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the measurement bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the measurement bandwidth is from stopband to 1.34 Fs. -
Page 16: Characteristics
Fig. 2-1 shows CS4399 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V;... -
Page 17: Characteristics
Fig. 2-1 shows CS4399 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; VL = VA = VD = 1.8 V, VP = 3.6 V; When testing PSRR, PCM input test signal held low (all zero data); T +25°C;... - Page 18 Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; T = +25°C;...
- Page 19 = +25°C; SDA load capacitance equal to maximum value of C = 400 pF; minimum SDA pull-up resistance, R Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with P(min) the specified load capacitance. Parameter...
- Page 20 = +25°C; SDA load capacitance equal to maximum value of C = 400 pF; minimum SDA pull-up resistance, R Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with P(min) the specified load capacitance. Parameter...
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Page 21: Functional Description
4.1.3 Audio Interfaces and Supported Formats There are two serial input ports on the CS4399, the audio serial port (ASP) and the auxiliary serial port (XSP). The ASP on the CS4399 supports I S, TDM, and DoP (DSD over PCM) formats up to a 384-kHz sample rate. The XSP on the CS4399 supports the DoP format up to a 352.8-kHz sample rate. - Page 22 Power Down The CS4399 has a register byte to power down individual components on the chip. Before any change can be applied to an individual component (except PLL), the block must be powered down first. For the PLL, changes can be applied after PLL_START is cleared.
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Page 23: Analog Outputs
CS4399 4.2 Analog Outputs 4.2 Analog Outputs The CS4399 provides an analog output that is derived from the digital audio input ports. This section describes the general flow of the analog outputs. 4.2.1 Analog Output Signal Flow The CS4399 signal flow is shown in Fig. -
Page 24: Class H Output
The internal charge pump is the central component of the two-mode Class H technology implemented in the CS4399. The charge pump receives its input voltage from the voltage present on the VCP or VP pin. From this input voltage, the charge pump creates the differential rail voltages supplied to the output stages.The charge pump can supply two sets of... - Page 25 If ADPT_PWR is set to 001 or 010, the rail voltages supplied to the amplifiers are held to ±VP_LDO or ±VCP, respectively. The rail voltages supplied to the output stages are held constant, regardless of the output signal level. The CS4399 outputs simply operate in a traditional Class AB configuration.
- Page 26 External VCP_FILT Supply Mode To bypass the CS4399 Class-H charge-pump circuit, provide external VCP_FILT± supply with the following conditions: • When CS4399 is operating, apply +3.0 V with ±5% accuracy to VCP_FILT+ and apply –3.0 V with ±5% accuracy to VCP_FILT–. •...
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Page 27: Headphone Presence Detect
EXT_VCPFILT 8 ms Figure 4-6. External VCP_FILT Power-Up Sequence For powering up CS4399 in this mode, the recommended sequence must be followed. This assumes that the CS4399 starts from the status where VCP_FILT± pin are presented with Hi-Z. 1. Set EXT_VCPFILT. - Page 28 4.4.1.1 Headphone Detect Methods CS4399 can detect the presence or absence of a plug. For a headphone-presence detect, a sense pin is connected to a terminal on the receptacle such that, if no plug is inserted, the pin is floating. If a plug is inserted, the pin is shorted to the tip (T) terminal.
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Page 29: Clocking Architecture
4.5 Clocking Architecture 4.5.1 Master Clock (MCLK) Sources The MCLK is required by the CS4399 to operate any functionality associated with control, serial-port operation, or data conversion. Depending on the setting of MCLK_SRC_SEL (see 74), the MCLK can be provided by one of following methods: •... - Page 30 CS4399 4.5 Clocking Architecture When the MCLK is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise mask shown in Fig. 4-11. Its frequency must be one of the nominal MCLK_INT frequencies (22.5792 or 24.576 MHz), and its duty cycle must be between 45% to 55%.
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Page 31: Clock Output And Fractional-N Pll
4.5.1.1 Internal RC Oscillator As described in Section 4.5.1, the CS4399 includes an internal RC oscillator that can be used as a clock source for peripheral circuit such as control port or charge pump. 4.6 Clock Output and Fractional-N PLL The CS4399 clock output can be used as a master clock for other data-conversion or signal-processing components, which requires synchronous timing to the CS4399. - Page 32 Fractional-N PLL The CS4399 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL can be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/MCLK pin (crystal-generated or external-feed).
- Page 33 CS4399 4.6 Clock Output and Fractional-N PLL Table 4-4 lists common settings with XTAL input as PLL reference. Table 4-4. PLL Configuration for Typical Use Case (XTAL as the PLL Reference) XTAL PLL_REF_PREDIV PLL_REF_PREDIV PLL_ PLL_ PLL_CAL_ PLL_DIV_FRAC PLL_OUT_DIV (MHz)
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Page 34: Filtering Options
To accommodate the increasingly complex requirements of digital audio systems, the CS4399 incorporates selectable filters in different playback modes. Note that when switching between filter options, the CS4399 output needs to be powered down in accordance with the sequence specified in Section 5.7.1... - Page 35 When the CS4399 serial port is a timing slave, its SCLK and LRCK I/Os are always inputs and are thus unaffected by the xSP_3ST control.
- Page 36 CS4399 4.8 Audio Serial Port (ASP) Fig. 4-17 Fig. 4-18 show the serial port clocking architecture. ASP_SCPOL_OUT p. XSP_SCPOL_OUT p. 81 Internal MCLK ASP_M/SB p. XSP_M/SB p. 81 SCLK ASP_N_LSB p. 77/XSP_N_LSB p. 80 N[13:0] ASP_N_MSB p. 78/XSP_N_MSB p. 80 ASP_M_LSB p.
- Page 37 CS4399 4.8 Audio Serial Port (ASP) The LRCK-high width (xSP_LCHI) controls the number of SCLK periods for which the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in single SCLK periods, from a minimum of one period to a maximum of the LRCK period minus one (and an absolute maximum of 768 SCLK periods).
- Page 38 CS4399 4.8 Audio Serial Port (ASP) Fig. 4-21 shows how LRCK frame start delay (xSP_FSD) controls the number of SCLK periods delay from the LRCK synchronization edge to the start of frame data. FSD = 101 FSD = 100 FSD = 011...
- Page 39 CS4399 4.8 Audio Serial Port (ASP) Table 4-7. Serial Port Clock Generation—Supported Configurations for 32-bits and 4 Channels SCLKs per LRCK Frame LRCK/FSYNC Frequency (MHz) xSP_N[15:0] xSP_M[15:0] Rate (kHz) xSP_LCPR + 1 xSP_LCPR[10:0] 22.5792 32.000 44.100 48.000 88.200 96.000 176.400 24.576...
- Page 40 CS4399 4.8 Audio Serial Port (ASP) • If xSP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-23 for an example in 50/50 mode. The TDM Mode behaves similarly. LRCK xSP_STP = 0 SCLK...
- Page 41 CS4399 4.8 Audio Serial Port (ASP) 4.8.9 Serial Port Status Each serial port has five status bits. Each bit is sticky and must be read to be cleared. The status bits have associated mask bits to mask setting the INT pin when the status bit sets. A brief description of each status bit is shown in Table 4-8.
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Page 42: Dsd Interface
DSD data, with the first or oldest bit in Slot t0. It is required that markers are provided continuously when the DoP interface is enabled, or a random sustained DC voltage asserts on loads from CS4399 outputs. - Page 43 DSD data signals. Note that phase modulation mode is supported only for DSD 64•Fs data rate. The CS4399 can detect overmodulation errors in the DSD data that do not comply to the SACD specification. Setting INV_ DSD_DET enables detection of overmodulation errors. This condition is reported through the DSD_INVAL_A_INT and DSD_INVAL_B_INT status bits.
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Page 44: Dsd And Pcm Mixing
PCM samples at 44.1 kHz. After the ASP subclocks are running, set MIX_PCM_PREP to indicate to the CS4399 that the PCM mixing event is imminent. After 1.6 ms, MIX_PCM_DSD can be safely set to initiate the mixing process. -
Page 45: Control Port Operation
However, to avoid potential interference problems, control port pins must remain static if no operation is required. The control port operates using a I C interface with the CS4399 acting as a slave device. Device communication must not begin until t (refer to Table 3-17) after power conditions are ready and RESET is released. - Page 46 Fast Mode (FM), with a bit rate of up to 400 kbit/s • Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s SDA is a bidirectional data line. Data is clocked into and out of the CS4399 by the SCL clock. Fig. 4-29, Fig.
- Page 47 CS4399 4.12 Control Port Operation For write operations, the data bytes following the MAP byte are written to the CS4399 register addresses pointed to by the last received MAP address, plus however many autoincrements have occurred. Fig. 4-29 shows a write pattern with autoincrementing.
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Page 48: Applications
Data-path logic is in the MCLK_INT domain, where MCLK_INT is expected to be 22.5792 or 24.576 MHz. For clocking scenarios in which the external system MCLK provided to CS4399 is neither 22.5792 nor 24.576 MHz, the PLL must be turned on to provide the desired internal MCLK. At start up, the system uses RCO as the internal MCLK for PLL programming over I C and switches to the PLL output after it settles. -
Page 49: Alert Mixing Shutdown
CS4399 5.4 Alert Mixing Shutdown 2. Power up and verify communication with CS4399. If there is no communication, it is possible that the crystal did not start. Check power rails and load capacitance and try again. 3. Clear PDN_CLKOUT in the Power Down Control (0x20000) register. This sets the clock output at MCLK_INT/2 frequency from CLKOUT pin. - Page 50 CS4399 5.7 Audio Output Power Down Sequences 5.7.1 PCM Power Down Sequence Example 5-1. PCM Power Down Sequence EGISTER IELDS ALUE ESCRIPTION Pop-free power down 0x10010 0x99 0xC0002 0x12 0xC000E 0x02 0xC0009 0x12 Mute PCM Path Signal Control 1. 0x90003...
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Page 51: Audio Output Power-Up Initialization
CS4399 5.8 Audio Output Power-Up Initialization Example 5-2. DSD Power Down Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 11 Mute DSD Processor Path Signal Control 1. 0x70002 data(0x70002) OR (0x03) Reserved DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTEBEQA DSD_MUTE_A Mute channel A DSD_MUTE_B Mute channel B 12 Wait time delay. -
Page 52: Audio Output Power-Up Sequence
CS4399 5.9 Audio Output Power-Up Sequence 5.8.2 DSD Power-Up Initialization Example 5-4. DSD Power-Up Initialization EGISTER IELDS ALUE ESCRIPTION DSD Power-Up Initialization 0x10010 0x99 0x10025 0x01 0x1002E 0x00 0xC0006 0x01 0xC0002 0x12 0xC0009 0x00 0xC0003 0x1E 0xC0005 0x20 5.9 Audio Output Power-Up Sequence An example of the power-up sequence for PCM and DSD are shown in Ex. - Page 53 CS4399 5.9 Audio Output Power-Up Sequence 5.9.2 DSD Power-Up Sequence Example 5-6. DSD Power-Up Sequence EGISTER IELDS ALUE ESCRIPTION Run DSD power-up initialization sequence in 5-4. Power on appropriate interface.Power Down Control. 0x20000 data (0x20000) For DoP on XSP, HH = 7F.
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Page 54: Example Sequences
CS4399 5.10 Example Sequences 5.10 Example Sequences This section provides recommended instruction sequences for standard CS4399 operations. 5.10.1 Power-up Sequence to I S Playback 5-7, a 22.5792-MHz crystal is used, ASP is set to I S master at 44.1 kHz, and full-scale output is 1.732 Vrms. - Page 55 CS4399 5.10 Example Sequences Example 5-7. Startup to I S Playback (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION 16 Configure ASP clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB Set ASP port to be master ASP_SCPOL_OUT Configure clock polarity for I...
- Page 56 CS4399 5.10 Example Sequences Example 5-7. Startup to I S Playback (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION 28 Configure Headphone HP Detect. 0xD0000 0x04 detect HPDETECT_CTRL HP detect disabled HPDETECT_INV HP detect input is not inverted HPDETECT_RISE_DBC_TIME Tip sense rising debounce time set to 0 ms...
- Page 57 CS4399 5.10 Example Sequences Example 5-8. Startup to DSD Playback (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL Power up XTAL driver PDN_PLL PDN_CLKOUT Reserved Apply DSD power-up initialization in Ex.
- Page 58 CS4399 5.10 Example Sequences Example 5-8. Startup to DSD Playback (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Configure DSD Interface DSD Interface Configuration. 0x70003 0x00 Reserved 0000 0 DSD_M/SB DSD is clock slave DSD_PM_EN Function is disabled DSD_PM_SEL Function is disabled Configure DSD path Signal DSD Processor Path Signal Control 2.
- Page 59 CS4399 5.10 Example Sequences 5.10.3 Power-Up Sequence to DoP Playback with PLL 5-9, an external 19.2-MHz MCLK is used with a PLL to generate an internal MCLK or 22.5792 MHz, and the ASP is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz.
- Page 60 CS4399 5.10 Example Sequences Example 5-9. DoP Playback with PLL (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION 19 Set ASP numerator ASP Numerator 1. 0x40010 0x03 ASP_N_LSB 0x03 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011...
- Page 61 CS4399 5.10 Example Sequences Example 5-9. DoP Playback with PLL (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION 31 Configure DSD interface DSD Interface Configuration. 0x04 0x70003 Reserved 0000 0 DSD_M/SB DSD is clock master DSD_PM_EN Function is disabled DSD_PM_SEL Function is disabled 32 Configure DSD Path Signal Control 2 DSD Processor Path Signal Control 2.
- Page 62 CS4399 5.10 Example Sequences Example 5-9. DoP Playback with PLL (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION 44 Set MCLK source and frequency System Clocking Control. 0x10006 0x05 Reserved 0000 0 MCLK_INT MCLK Frequency is set to 22.5792 MHz MCLK_SRC_SEL MCLK Source is set to PLL 45 Wait for at least 150 µs.
- Page 63 MCLK. It makes the following assumptions: • The CS4399 is already powered up and out of reset. • MCLK is sourced directly from external clock input (Direct MCLK). MCLK_INT is 22.5792 MHz, and the sample rate is an integer divide of MCLK.
- Page 64 CS4399 5.10 Example Sequences Example 5-11. Sequence for Headphone Detection (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Wait for interrupt. Check if HPDETECT_PLUG_INT or HPDETECT_UNPLUG_INT is set in the Interrupt Status 1 register (0xF0000). 5.10.6 DoP and PCM Mixing Ex. 5-12 shows steps necessary to mix DoP and PCM.
- Page 65 CS4399 5.10 Example Sequences Example 5-12. DoP and PCM Mixing (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Configure XSP Frame XSP Frame Configuration. 0x40029 0x0A Reserved XSP_STP Configure XSP port to accept I S input XSP_5050 XSP_FSD Set XSP Channel Location XSP Channel 1 Location.
- Page 66 CS4399 5.10 Example Sequences Example 5-12. DoP and PCM Mixing (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HP Detect enabled HPDETECT_INV HP detect input is not inverted HPDETECT_RISE_DBC_TIME Tip Sense rising debounce time set to 0 ms...
- Page 67 CS4399 5.10 Example Sequences Example 5-12. DoP and PCM Mixing (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Configure ASP Clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB Set ASP port to be Master ASP_SCPOL_OUT Set output SCLK polarity ASP_SCPOL_IN Input SCLK polarity is don’t care...
- Page 68 CS4399 5.10 Example Sequences Example 5-12. DoP and PCM Mixing (Cont.) STEP TASK EGISTER IELDS ALUE ESCRIPTION Enable ASP Power Down Control. 0x20000 0x24 PDN_XSP PDN_ASP Enable ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved Enable PCM/DoP mix Configure DSD Volume DSD Volume A.
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Page 69: Register Quick Reference
CS4399 6 Register Quick Reference 6 Register Quick Reference Notes: Default values are shown below the bit field names. The default values in all reserved bits must be preserved. Table 6-1. Register Quick Reference Address Function 0x01 0000 Device ID A and B... - Page 70 CS4399 6 Register Quick Reference Table 6-1. Register Quick Reference (Cont.) Address Function Reserved 0x04 0005– — 0x04 000F 0x04 0010 ASP Numerator 1 ASP_N_LSB p. 77 0x04 0011 ASP Numerator 2 ASP_N_MSB p. 78 0x04 0012 ASP Denominator 1 ASP_M_LSB p.
- Page 71 CS4399 6 Register Quick Reference Table 6-1. Register Quick Reference (Cont.) Address Function 0x06 0001 XSP Channel 2 XSP_RX_CH2 Location p. 83 Reserved 0x06 0002– — 0x06 0009 0x06 000A XSP Channel 1 Size — XSP_RX_ XSP_RX_ XSP_RX_CH1_RES and Enable...
- Page 72 CS4399 6 Register Quick Reference Table 6-1. Register Quick Reference (Cont.) Address Function 0x0F 0000 Interrupt Status 1 DAC_OVFL_ HP_DETECT_ HP_DETECT_ XTAL_ XTAL_ PLL_READY_ PLL_ERROR_ PDN_DONE_ (Read Only) PLUG_INT UNPLUG_INT READY_INT ERROR_INT p. 90 0x0F 0001 Interrupt Status 2 ASP_OVFL_...
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Page 73: Register Descriptions
CS4399 7 Register Descriptions 7 Register Descriptions All registers are read/write, except for the device’s ID, revision, and status registers, which are read only. The following tables describe bit assignments. The default state of each bit after a power-up sequence or reset is listed in each bit description. - Page 74 CS4399 7.1 Global Registers Bits Name Description MCLK_SRC_ Select the source of internal MCLK. 00 Direct MCLK/XTAL Mode 01 PLL Mode 10 (Default) RCO Mode 11 Reserved 7.1.6 Serial Port Sample Rate Address 0x1000B — ASP_SPRATE Default Bits Name Description —...
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Page 75: Pll Registers
CS4399 7.2 PLL Registers 7.1.9 Power Down Control Address 0x20000 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT — Default Bits Name Description PDN_XSP XSP input path power control. Configures XSP SDIN path power state. 0 Powered up. 1 (Default) Powered down. - Page 76 CS4399 7.2 PLL Registers 7.2.2 PLL Setting 2 Address 0x30002 PLL_DIV_FRAC_0 Default Bits Name Description PLL_DIV_ PLL fractional portion of divide ratio LSB. There are 3 bytes of PLL feedback divider fraction portion and this is LSB byte; FRAC_0 e.g., 0xFF means (2 + …+2...
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Page 77: Asp And Xsp Registers
CS4399 7.3 ASP and XSP Registers 7.2.8 PLL Setting 8 Address 0x3001B — PLL_MODE — Default Bits Name Description — Reserved PLL_MODE 500/512 factor used in PLL frequency calculation equation, 4-1. 0 No bypass 1 (Default) Bypass — Reserved 7.2.9... - Page 78 CS4399 7.3 ASP and XSP Registers 7.3.3 ASP Numerator 2 Address 0x40011 ASP_N_MSB Default Bits Name Description ASP_N_MSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide numerator MSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency.
- Page 79 CS4399 7.3 ASP and XSP Registers 7.3.8 ASP LRCK Period 1 Address 0x40016 ASP_LCPR_LSB Default Bits Name Description ASP_LCPR_ The value in this register cannot be changed while the serial port is powered up. ASP LRCK period, in units of ASP_SCLK periods stored in ASP_LCPR_MSB/LSB.
- Page 80 CS4399 7.3 ASP and XSP Registers Bits Name Description ASP_FSD ASP frame start delay (units of ASP_SCLK periods). 000 0 delay 001 0.5 delay 010 (Default) 1.0 delay 101 2.5 delay 110–111 Reserved 7.3.12 XSP Numerator 1 Address 0x40020 XSP_N_LSB...
- Page 81 CS4399 7.3 ASP and XSP Registers 7.3.16 XSP LRCK High Time 1 Address 0x40024 XSP_LCHI_LSB Default Bits Name Description XSP_LCHI_ The value in this register cannot be changed while the serial port is powered up. XSP LRCK high duration, in units of XSP_SCLK periods stored in XSP_LCHI_LSB/MSB. This value must be less than XSP_LCPR.
- Page 82 CS4399 7.3 ASP and XSP Registers Bits Name Description XSP_SCPOL_ XSP SCLK input polarity (pad to logic). 0 Normal 1 (Default) Inverted XSP_LCPOL_ XSP LRCK output drive polarity. 0 (Default) Normal 1 Inverted XSP_LCPOL_ XSP LRCK input polarity (pad to logic).
- Page 83 CS4399 7.3 ASP and XSP Registers Bits Name Description ASP_RX_ ASP RX channel n active phase. Valid only in 50/50 mode (ASP_5050 = 1). CHn_AP 0 (Default when n = 1) In 50/50 mode, channel data is input when LRCK/FSYNC is low...
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Page 84: Dsd Registers
CS4399 7.4 DSD Registers 7.4 DSD Registers 7.4.1 DSD Volume B Address 0x70000 DSD_VOLUME_B Default Bits Name Description DSD_ Digital volume control registers for DSD processor channel B. It allows independent control of the signal level in 1/2 dB VOLUME_B increments from 0 dB. - Page 85 CS4399 7.4 DSD Registers 7.4.4 DSD Interface Configuration Address 0x70003 — DSD_M/SB DSD_PM_EN DSD_PM_SEL Default Bits Name Description — Reserved DSD_M/SB DSD clock master or Slave Mode. 0 (Default) Slave Mode 1 Master Mode DSD_PM_EN DSD phase modulation mode. Can only be used when DSD_SPEED = 0 (64•Fs).
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Page 86: Analog Output And Pcm Registers
CS4399 7.5 Analog Output and PCM Registers Bits Name Description MIX_PCM_ Enable PCM stream mixing into DSD stream. This bit must be set only after MIX_PCM_PREP is enabled. Disable this bit prior to disabling MIX_PCM_PREP bit. This mode requires DSD_EN to be enabled and DSD_PRC_SRC set to receive DSD through either the DSD interface or XSP. - Page 87 CS4399 7.5 Analog Output and PCM Registers 7.5.2 PCM Filter Option Address 0x90000 FILTER_ PHCOMP_ — HIGH_PASS DEEMP_ON SLOW_FASTB LOWLATB Default Bits Name Description FILTER_ Fast and slow filter selection. SLOW_ 0 (Default) Fast filter is selected. FASTB 1 Slow filter is selected.
- Page 88 CS4399 7.5 Analog Output and PCM Registers 7.5.5 PCM Path Signal Control 1 Address 0x90003 PCM_RAMP_ PCM_VOL_ PCM_ PCM_SZC PCM_AMUTE PCM_MUTE_A PCM_MUTE_B DOWN BEQA AMUTEBEQA Default Bits Name Description PCM_RAMP_ Soft volume ramp-down before filter mode change. A mute is performed before filter mode change and an unmute is DOWN performed after executing the filter mode change.
- Page 89 CS4399 7.5 Analog Output and PCM Registers 7.5.7 Class H Control Address 0xB0000 — ADPT_PWR HV_EN EXT_VCPFILT Default Bits Name Description — Reserved ADPT_PWR Adaptive power adjustment. Configures how power to line output amplifiers adapts to the output signal level.
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Page 90: Interrupt Status And Mask Registers
CS4399 7.6 Interrupt Status and Mask Registers Bits Name Description HPDETECT_ HPDETECT unplug debounce status. Setting HPDETECT_INV reverses the meaning of this bit. UNPLUG_ 0 (Default) Condition is not present 1 Condition is present — Reserved 7.6 Interrupt Status and Mask Registers 7.6.1... - Page 91 CS4399 7.6 Interrupt Status and Mask Registers Bits Name Description ASP_ ASP RX no LRCK. NOLRCK_INT 0 Condition is not present 1 Condition is present — Reserved 7.6.3 Interrupt Status 3 Address 0xF0002 XSP_OVFL_ XSP_ERROR_ XSP_LATE_ XSP_EARLY_ XSP_ — NOLRCK_INT...
- Page 92 CS4399 7.6 Interrupt Status and Mask Registers Bits Name Description DOP_ON_INT The DoP decoder is powered up. 0 Condition is not present 1 Condition is present 7.6.5 Interrupt Mask 1 Address 0xF0010 HPDETECT_ HPDETECT_ XTAL_READY_ XTAL_ DAC_OVFL_ PLL_READY_ PLL_ERROR_ PDN_DONE_...
- Page 93 CS4399 7.6 Interrupt Status and Mask Registers Bits Name Description ASP_ ASP_NOLRCK_ mask. NOLRCK_ 0 Unmasked INT_ MASK 1 (Default) Masked — Reserved 7.6.7 Interrupt Mask 3 Address 0xF0012 XSP_ XSP_OVFL_ XSP_ERROR_ XSP_LATE_ XSP_EARLY_ NOLRCK_INT_ — INT_MASK INT_MASK INT_MASK INT_MASK...
- Page 94 CS4399 7.6 Interrupt Status and Mask Registers 7.6.8 Interrupt Mask 5 Address 0xF0014 DSD_ DSD_ DSD_RATE_ DOP_MRK_ DSD_STUCK_ DSD_INVAL_ DSD_INVAL_ DOP_ON_INT_ SILENCE_A_ SILENCE_B_ ERROR_INT_ DET_INT_ INT_MASK A_INT_MASK B_INT_MASK MASK INT_MASK INT_MASK MASK MASK Default Bits Name Description DSD_STUCK_ DSD_STUCK_INT mask.
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Page 95: Pcb Layout Considerations
8.4 QFN Thermal Pad The CS4399 comes in a compact QFN package, the underside of which reveals a large metal pad that serves as a thermal relief to provide maximum heat dissipation. This pad must mate with an matching copper pad on the PCB and must be electrically connected to ground. -
Page 96: Performance Plots
CS4399 9 Performance Plots 9 Performance Plots 9.1 Digital Filter Response 9.1.1 Combined Filter Response—Single Speed (Fs = 32 kHz, Slow Roll-Off) 0.02 0.015 −20 0.01 −40 −60 0.005 −80 −100 −0.005 −120 −0.01 −140 −160 −0.015 −180 −0.02 0 0.05 0.1 0.15... - Page 97 CS4399 9.1 Digital Filter Response 9.1.2 Combined Filter Response—Single Speed (Fs = 32 kHz, Fast Roll-Off) 0.02 0.015 −20 0.01 −40 −60 0.005 −80 −100 −0.005 −120 −0.01 −140 −160 −0.015 −180 −0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45...
- Page 98 CS4399 9.1 Digital Filter Response 9.1.3 Combined Filter Response—Single Speed (Fs = 44.1 and 48 kHz, Slow Roll-Off) 0.02 0.015 −20 0.01 −40 −60 0.005 −80 −100 −0.005 −120 −0.01 −140 −160 −0.015 −180 −0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35...
- Page 99 CS4399 9.1 Digital Filter Response 9.1.4 Combined Filter Response—Single Speed (Fs = 44.1 and 48 kHz, Fast Roll-Off) 0.02 0.015 −20 0.01 −40 −60 0.005 −80 −100 −0.005 −120 −0.01 −140 −160 −0.015 −180 −0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35...
- Page 100 CS4399 9.1 Digital Filter Response 9.1.5 Combined Filter Response—Double Speed (Slow Roll-Off) 0.02 −20 0.01 −40 −60 −80 −0.01 −100 −120 −0.02 −140 −0.03 −160 −180 −0.04 0.05 0.15 0.25 Frequency (Normalized to Fs) Frequency (Normalized to Fs) Figure 9-25. Passband Ripple Figure 9-26.
- Page 101 CS4399 9.1 Digital Filter Response 9.1.6 Combined Filter Response—Double Speed (Fast Roll-Off) 0.06 −20 −40 0.04 −60 −80 0.02 −100 −120 −140 −0.02 −160 −180 −0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (Normalized to Fs) Frequency (Normalized to Fs) Figure 9-31.
- Page 102 CS4399 9.1 Digital Filter Response 9.1.7 Combined Filter Response—Quad Speed (Slow Roll-Off) 0.01 −20 −40 −60 −0.01 −80 −100 −0.02 −120 −0.03 −140 −160 −0.04 −180 −0.05 0.05 0.15 0.25 Frequency (Normalized to Fs) Frequency (Normalized to Fs) Figure 9-37. Passband Ripple Figure 9-38.
- Page 103 CS4399 9.1 Digital Filter Response 9.1.8 Combined Filter Response—Quad Speed (Fast Roll-Off) 0.03 0.02 −20 0.01 −40 −60 −80 −0.01 −100 −0.02 −120 −0.03 −140 −160 −0.04 −180 −0.05 0.05 0.15 0.25 Frequency (Normalized to Fs) Frequency (Normalized to Fs) Figure 9-43.
- Page 104 CS4399 9.1 Digital Filter Response 9.1.9 Combined Filter Response—Octuple Speed 0.01 −20 −0.01 −40 −0.02 −60 −0.03 −0.04 −80 −0.05 −100 −0.06 −120 −0.07 −140 −0.08 −160 −0.09 −180 −0.1 0.02 0.04 0.06 0.08 0.12 Frequency (Normalized to Fs) Frequency (Normalized to Fs) Figure 9-49.
- Page 105 CS4399 9.1 Digital Filter Response −0.2 −0.2 Time (µs) Time (µs) Figure 9-55. Impulse Response Figure 9-56. Step Response 9.1.11 Combined Filter Response—Double Speed (NOS = 1) −0.5 −20 −40 −1 −60 −1.5 −80 −2 −100 −2.5 −120 −140 −3 −160...
- Page 106 CS4399 9.1 Digital Filter Response 9.1.12 Combined Filter Response—Quad Speed (NOS = 1) −0.5 −20 −40 −1 −60 −1.5 −80 −2 −100 −2.5 −120 −140 −3 −160 −3.5 −180 −4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45...
- Page 107 CS4399 9.1 Digital Filter Response −0.2 −0.2 Time (µs) Time (µs) Figure 9-67. Impulse Response Figure 9-68. Step Response 9.1.14 High-pass Filter and Deemphasis −1 −5 −2 −3 −10 −4 −5 −15 −6 −20 −7 −8 −25 −9 −10 −30 0 0.05...
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Page 108: Package Dimensions
CS4399 10 Package Dimensions 10 Package Dimensions 10.1 40-Pin QFN Package Dimensions Figure 10-1. 40-Pin QFN Package Drawing Table 10-1. 40-Pin QFN Package Dimensions Millimeters Description Minimum Nominal Maximum Total thickness 0.75 Stand off 0.035 0.05 Mold thickness — 0.55 —... -
Page 109: 42-Ball Wlcsp Package Dimensions
CS4399 10.2 42-Ball WLCSP Package Dimensions 10.2 42-Ball WLCSP Package Dimensions Ball A1 Ball A1 Location Indicator Wafer Back Side Side View Bump Side Notes: • Controlling dimensions are in millimeters. • Dimensioning and tolerances per ASME Y 14.5M-1994. • The Ball A1 position indicator is for illustration purposes only and may not be to scale. -
Page 110: Thermal Characteristics
Table 14-1. Revision History Revision Changes Initial release DEC ‘16 Important: Please check with your Cirrus Logic sales representative to confirm that you are using the latest revision of this document and to determine whether there are errata associated with this device. DS1113F1... - Page 111 “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties.
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