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Single Phase Bi-Directional Power/Energy IC
Features
!
Energy Data Linearity: ±0.1% of Reading
over 1000:1 Dynamic Range.
On-Chip Functions: (Real) Energy, I ∗ V,
!
I
and V
, Energy-to-Pulse Conversion
RMS
RMS
!
Smart "Auto-Boot" Mode from Serial
EEPROM Enables Use without MCU.
!
AC or DC System Calibration
!
Mechanical Counter/Stepper Motor Driver
!
Meets Accuracy Spec for IEC 687/1036, JIS
!
Power Consumption <12 mW
!
Interface Optimized for Shunt Sensor
!
V vs. I Phase Compensation
!
Ground-Referenced Signals with Single
Supply
!
On-chip 2.5 V Reference (MAX 60 ppm/°C
drift)
!
Simple Three-Wire Digital Serial Interface
!
Watch Dog Timer
!
Power Supply Monitor
!
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3.3 V to +5 V
VREFIN
VREFOUT
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
VA+
IIN+
PGA
x10,x50
IIN-
th
4
Order
πΓ
Modulator
VIN+
x10
nd
VIN-
2
Order
πΓ
Modulator
x1
Voltage
Power
Reference
Monitor
VA-
PFMON
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Description
The CS5460A is a highly integrated ∆Σ Analog-to-Digital
Converter (ADC) which combines two ∆Σ ADCs, high
speed power calculation functions, and a serial interface
on a single chip. It is designed to accurately measure
and calculate: Real (True) Energy, Instantaneous Pow-
er, I
, and V
RMS
RMS
metering applications. The CS5460A interfaces to a
low-cost shunt resistor or transformer to measure cur-
rent, and resistive divider or potential transformer to
measure voltage. The CS5460A features a bi-directional
serial interface for communication with a micro-control-
ler and a pulse output engine for which the average
pulse frequency is proportional to the real power.
CS5460A has on-chip functionality to facilitate AC or DC
system-level calibration.
The "Auto-Boot" feature allows the CS5460A to function
'stand-alone' and to initialize itself on system power-up.
In Auto-Boot Mode, the CS5460A reads the calibration
data and start-up instructions from an external EE-
PROM. In this mode, the CS5460A can operate without
a microcontroller, in order to lower the total bill-of-mate-
rials cost, when the meter is intended for use in
high-volume/residential metering applications.
ORDERING INFORMATION:
CS5460A-BS -40°C to +85°C
RESET
High Pass
Watch Dog
Filter
Timer
Digital
Filter
Power
Calculation
Engine
Control /
(Energy
Serial
I * V
Interface
I
,V
)
RMS
RMS
Digital
Filter
Energy-to-
Pulse
High Pass
Converter
Filter
System
Clock
Calibration
/K
Clock
Generator
SRAM
XIN
XOUT CPUCLK
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
CS5460A
for single phase 2- or 3-wire power
24-pin SSOP
VD+
MODE
CS
SDI
SDO
SCLK
INT
EDIR
EOUT
DGND
OCT '01
DS284PP4
1
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Related Manuals for Cirrus Logic CS5460A
Summary of Contents for Cirrus Logic CS5460A
- Page 1 XOUT CPUCLK DGND This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. OCT ‘01 Copyright Cirrus Logic, Inc. 2001 P.O. Box 17847, Austin, Texas 78760 DS284PP4...
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Page 2: Table Of Contents
(electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. - Page 3 CS5460A 4.3.3 Which EEPROMs Can Be Used? ............... 31 4.4 Interrupt and Watchdog Timer ..................33 4.4.1 Interrupt ....................... 33 4.4.1.1 Clearing the Status Register ............... 33 4.4.1.2 Typical use of the INT pin ..............33 4.4.1.3 INT Active State .................. 34 4.4.1.4 Exceptions ..................
- Page 4 Figure 15. CS5460A Auto-Boot Configuration: Automatic Restart After Power Failure ....33 Figure 16. Oscillator Connection ....................35 Figure 17. VREFOUT Voltage vs. Temperature characteristic for a typical CS5460A sample..35 Figure 18. System Calibration of Gain..................39 Figure 19.
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Page 5: Characteristics And Specifications
CS5460A 1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS = -40° C to +85° C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz, K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.) - Page 6 (frequency = 60Hz) is imposed onto the +5V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Then the CS5460A is commanded to ’continuous computation cycles’ data acquisition mode, and digital output data is collected for the channel under test.
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Page 7: Vrefout Reference Output Voltage
CS5460A VREFOUT REFERENCE OUTPUT VOLTAGE Parameter Symbol Unit Reference Output Output Voltage REFOUT +2.4 +2.6 VREFOUT Temperature Coefficient (Note 12) T ppm/°C VREFOUT ∆V Load Regulation (Output Current 1 µA Source or Sink) Reference Input Input Voltage Range VREFIN +2.4 +2.5... -
Page 8: Digital Characteristics
CS5460A 3.3 V DIGITAL CHARACTERISTICS = -40° C to +85° C; VA+ = 5 V ±10%, VD+ = 3.3 V ±10%; VA-, DGND = 0 V) (See Notes 3, 4, and 13) Parameter Symbol Unit High-Level Input Voltage All Pins Except XIN, XOUT, SCLK, and RESET 0.6 VD+... -
Page 9: Switching Characteristics
CS5460A SWITCHING CHARACTERISTICS = -40° C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF)) -
Page 10: Figure 1. Cs5460A Read And Write Timing Diagrams
CS5460A Figure 1. CS5460A Read and Write Timing Diagrams DS284PP4... -
Page 11: Figure 2. Cs5460A Auto-Boot Sequence Timing
MODE (Input) (Input) (Output) SCLK (Output) (Output) STOP LAST 8 BITS (Input) Data from EEPROM Figure 2. CS5460A Auto-Boot Sequence Timing... -
Page 12: General Description
SPI™ and Microwire™ compat- ible. The serial port has a Schmitt Trigger input on The CS5460A is a CMOS monolithic power mea- its SCLK (serial clock) and RESET pins to allow surement device with a real power/energy compu- for slow rise time signals. -
Page 13: Digital Compensation Filters
2.1.5 Overall Filter Response Energy Register. RMS calculations are also per- formed on the data using the last N instantaneous When the CS5460A is driven with a 4.096 MHz voltage/current samples, and these results can be clock (K=1), the composite magnitude response read from the RMS Voltage Register and the RMS (over frequency) of the voltage channel’s input fil-... -
Page 14: Figure 3. Data Flow
Table 1 conveys the typical relationship between CS5460A. As an illustration, in any of the signed the differential input voltage (across the “+” and output registers, the maximum register value is “-”... -
Page 15: Cs5460A Linearity Performance
A/D conversion. After any time nel, when its PGA is set for 10x gain) is 250mV that these bits are asserted by the CS5460A, they (nominal). If the gain registers of both channels must be cleared (by the user) before they can be as-... -
Page 16: Single Computation Cycle (C=0)
Section 3.1). This commands instructs the est sine wave voltage signal that can be presented CS5460A to perform conversions in ‘single com- across the inputs, with no saturation of the inputs, putation cycle’ data acquisition mode. Based on is (typically) 250mV / sqrt(2) = ~176.78 mV the value in the Cycle Count Register, a single (RMS), which is at ~70.7% of full-scale. -
Page 17: Basic Application Circuit Configurations
‘potential transformer’) with very little Configurations roll-off/phase delay, even at the higher harmonics. Figure 6 shows the CS5460A connected to a ser- A current transformer is then used to sense the line vice to measure power in a single-phase 2-wire sys- current. -
Page 18: Serial Port Overview
Request for a read requires an in- The CS5460A's serial port incorporates a state ma- ternal register transfer to the transmit buffer, while chine with transmit/receive buffers. The state ma-... -
Page 19: Figure 8. Typical Connection Diagram (One-Phase 3-Wire)
The CS5460A is initialized and fully operational in an internal register. The user should refer to the its active state upon power-on. After a power-on, “Commands”... -
Page 20: Commands (Write Only)
CS5460A 3.1 Commands (Write Only) All command words are 1 byte in length. Commands that write to a register must be followed by 3 bytes of register data. Commands that read from registers initiate 3 bytes of register data. Commands that read data can be ‘chained’... - Page 21 In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5460A out of sleep state requires more time than waking the device out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal.
- Page 22 CS5460A 3.1.7 Register Read/Write This command informs the state machine that a register access is required. On reads the addressed register is load- ed into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred to the addressed register on the 24 SCLK.
-
Page 23: Serial Port Interface
0, the SDI, SDO, and SCLK pins have the would transmit the command (0x40) to initiate a following functionality: write to the Configuration Register. The CS5460A will then acquire the serial data input from the SDI Serial Data In (input pin), is the user-generat-... -
Page 24: System Initialization
12 MCLK cycles after RESET is de-asserted. After a hardware or software 1) Power on the CS5460A. (Or if the device is al- reset, the internal registers (some of which may ready powered on, recycle the power.) drive output pins) will be reset to their default values 2) Hardware Reset. -
Page 25: Cs5460A Power States
CS5460A out of sleep state or stand-by state, 1) Power on the CS5460A. (Or if the device is al- successful wake-up of the device will be insured if ready powered on, recycle the power.) -
Page 26: Functional Description
DC voltage level of 250 mV across the volt- the CS5460A inputs when the line-voltage and age/current channels will cause full-scale readings line-current are at 220 V and 15 A. We call these of 1.0 in the CS5460A Instantaneous Voltage and values V and V Vnom Inom. - Page 27 CS5460A rent inputs are set at V and V , we want the ation, the nominal line voltage and current do not Vnom Inom pulse rate to be at ‘IR’ = 100 pulses per second. IR determine the appropriate pulse-rate setting. In- will be some percentage of PR.
-
Page 28: Pulse Output For Normal, Stepper Motor And Mechanical Counter Format
EOUT and EDIR pins is illus- one pulse, the CS5460A will issue a “burst” of one trated in Figure 10. These are active-low pulses or more pulses on EOUT (and also possibly on with very short duration. -
Page 29: Mechanical Counter Format
(for a given calibration). pulse, one of the output pins (either EOUT or 4.2.2 Mechanical Counter Format EDIR) changes state. When the CS5460A must is- Setting the MECH bit in the Control Register to ‘1’ sue another energy pulse, the other output changes and the STEP bit to ‘0’... -
Page 30: Auto-Boot Mode Using Eeprom
The CS5460A has a MODE pin. When the MODE change any of the default register values (if de- pin is set to logic low, the CS5460A is in normal sired) and begin conversions. operating mode, called host mode. This mode de-... -
Page 31: Which Eeproms Can Be Used
RESET pin from active state to inac- K=1. tive state (low to high) will cause the CS5460A to drive the CS pin low, and after this, to issue the stan- 44 7F C4 A9 ;Write value of 0x7FC4A9 to... - Page 32 RESET pin in attempt to allow the CS5460A to The auto-boot sequence is terminated by writing a reboot after a sudden loss of power, followed by a ‘1’...
-
Page 33: Interrupt And Watchdog Timer
V A - D G N D smooth power-down, as well as a proper power-up/reset during D G N D AG N D and after a power black-out or brown-out event. Figure 15. CS5460A Auto-Boot Configuration: Automatic Restart After Power Failure DS284PP4... -
Page 34: Int Active State
To properly clear the WDT (Watch Dog Timer) bit of the Status Register, first read the Energy Regis- The CS5460A can be driven by a clock ranging ter, then clear the bit in the Status Register. from 2.5 to 20 MHz. The user must appropriately set the K divider value such that MCLK/K will be 4.4.2 Watch Dog Timer... -
Page 35: Analog Inputs
VREFOUT Voltage vs. Temperature characteristic for a typical CS5460A sample is shown in Figure 17. Note the general shape of this characteristic is Figure 16. Oscillator Connection Figure 17. VREFOUT Voltage vs. Temperature characteristic for a typical CS5460A sample. DS284PP4... -
Page 36: Calibration
CS5460A sample is derived from that Temperature characteristic (for any particular sample’s individual VREFOUT Voltage vs. Tem- CS5460A sample), which indicates the drift of the perature characteristic. Using the data from the device’s energy registration drift over temperature, sample’s VREFOUT Voltage vs. Temperature using either the registration of the device’s ener-... -
Page 37: The Calibration Registers
These regis- the DC offset calibration sequence, the AC gain ters are updated by the CS5460A after either an AC and DC gain calibration sequences perform the or DC gain calibration sequence has been executed. -
Page 38: Calibration Signal Input Level
The calibration sequenc- neous voltage level that needs to be measured es will not run if the CS5460A is running in either across the inputs (including the maximum of the two available acquisition modes. -
Page 39: Description Of Calibration Algorithms
AC offset register value will be subtracted 4.8.7 Description of Calibration Algorithms from the square of each successive voltage sample The computational flow of the CS5460A’s AC and in order to nullify the AC offset that may be inher- DC gain/offset calibration sequences are illustrated ent in the voltage-channel signal path. -
Page 40: Dc Offset Calibration Sequence
The inputs should be grounded during DC off- the “+’ and “-” inputs, the CS5460A determines the set calibration. The DC offset value is added to the Voltage Channel Gain Register value by averaging signal path to nullify the DC offset in the system. -
Page 41: Duration Of Calibration Sequence
After DC Gain Calibration (Vgain Register changed to 1.0870) 4.8.9 Is Calibration Required? 230 mV 0.9999... DC Signal The CS5460A does not have to be calibrated. After Instantaneous Voltage INPUT Register Values CS5460A is powered on and then reset, the device SIGNAL is functional. -
Page 42: Order Of Calibration Sequences
DC gain calibration is performed specified in Table 2, the exact reference voltage (on either channel) of a CS5460A sample while ap- and current levels to which this linearity is refer- plying a DC signal whose value is less than the in- enced will vary from sample to sample. -
Page 43: Calibration Tips
CS5460A. Voltage channel, then the DC offset register value for the and current transformers, as well as other sen-... -
Page 44: Time-Base Calibration Register
(i.e., there is zero input on the current channel), the channels of the CS5460A. In this condition, any current channel may still register a very small phase delay between the measured voltage and cur-... -
Page 45: Input Protection - Current Limit
VA- pin) these protection diodes will turn on in- whose frequency is higher than one-half of the side the CS5460A. But in order to prevent exces- sampling frequency (the Nyquist frequency). The sive current levels from flowing through the... -
Page 46: Input Filtering
VIN+ pin does not need referenced above and below the CS5460A’s an additional, separate, dedicated protection resis- ground reference voltage. Such a differential bipo- tor. - Page 47 CS5460A’s phase compensa- the voltage/current channel input anti-aliasing fil- tion bits (see Phase Compensation), in order to...
- Page 48 CS5460A to calibration of the current channel. realize its relatively good CMRR performance in the frequency-range of interest.
- Page 49 “0000000”, the inter- off frequency of the voltage channel’s input filter nal filtering stages of the CS5460A will impose an will be 14870 Hz. The difference in the two cutoff additional delay on the (fundamental frequency frequencies is due to the difference in the input im- component of the) voltage signal of 0.0215 de-...
-
Page 50: Protection Against High-Voltage And/Or High-Current Surges
4.15 Improving RFI Immunity put filter capacitors (discussed in the previous sec- tions) may not be sufficient to protect the CS5460A During EMC acceptance testing of the user’s pow- from such high-frequency voltage/current surges. -
Page 51: Figure 24. Input Protection For Single-Ended Input Configurations
Finally, note that inside the value of C5 should be the same as C3, (and so the CS5460A, the Vin+, Vin-, Iin+, and Iin- pins have designer may have to re-calculate the desired value all been buffered with ~10pF of internal capaci- of C3, since the addition of C5 will change the tance (to VA-) in attempt to improve the device’s... -
Page 52: Pcb Layout
CS5460A 4.16 PCB Layout For optimal performance, the CS5460A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device con- nected to the analog plane. Note: Refer to the CDB5460A Evaluation Board for... -
Page 53: Register Description
State Machine Configuration Register (1 × 24) Mask Register (1 × 24) Figure 25. CS5460A Register Diagram Note: ** “default” => bit status after software or hardware reset 2. Note that all registers can be read from, and written to. - Page 54 CS5460A Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle. When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin.
-
Page 55: Current Channel Dc Offset Register And Voltage Channel Dc Offset Register
CS5460A 5.2 Current Channel DC Offset Register and Voltage Channel DC Offset Register Address: 1 (Current Channel DC Offset Register) 3 (Voltage Channel DC Offset Register) ..Default** = 0.000 The DC offset registers are initialized to zero on reset, allowing the device to function and perform measure- ments. -
Page 56: Pulse-Rate Register
CS5460A 5.5 Pulse-Rate Register Address: 6 ..Default** = 32000.00Hz The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of real (billable) energy. The register’s smallest valid value is 2 but can be in 2 increments. -
Page 57: Power Offset Register
First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cy- cle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be asserted at the end of the calibration. - Page 58 CS5460A The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.
-
Page 59: Control Register
CS5460A CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz. EDIR Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative. EOUT Indicates that enough positive/negative energy has been reached within the internal EOUT En- ergy Accumulation Register (not accessible to user) to mandate the generation of one or more pulses on the EOUT pin (if enabled, see Configuration Register). -
Page 60: Pin Description
CS should be changed when SCLK is low. Mode Select MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial EEPROM to receive commands and settings. When at logic low, the CS5460A assumes normal “host mode”... - Page 61 CS5460A Voltage VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter. Reference Output Voltage VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip modulator.
-
Page 62: Package Dimensions
CS5460A 7. PACKAGE DIMENSIONS 24L SSOP PACKAGE DRAWING ∝ END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE 0.084 2.13 0.002 0.006 0.010 0.05 0.13 0.25 0.064 0.068 0.074 1.62 1.73 1.88 0.009 0.015 0.22 0.38... - Page 63 • Notes •...
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