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Asus AAEON PICO-APL4-SEMI User Manual
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Asus AAEON PICO-APL4-SEMI User Manual

Asus AAEON PICO-APL4-SEMI User Manual

Pico-semi system
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PICO-APL4-SEMI
Pico-SEMI System
rd
User's Manual 3
Ed
Last Updated: February 10, 2025

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Summary of Contents for Asus AAEON PICO-APL4-SEMI

  • Page 1 PICO-APL4-SEMI Pico-SEMI System User’s Manual 3 Last Updated: February 10, 2025...

  • Page 2: Copyright Notice

    Copyright Notice This document is copyrighted, 2025. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgements All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Celeron® and Pentium® are registered trademarks of Intel Corporation ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity PICO-APL4-SEMI If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A2 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 外壳 ○...
  • Page 10 China RoHS Requirement (EN) Name and content of hazardous substances in product AAEON System QO4-381 Rev.A2 Hazardous Substances Part Name 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB Assemblies × ○ ○ ○ ○ ○ Connector and ×...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................5 Chapter 2 – Hardware Information ..................6 Dimensions ....................... 7 Jumpers and Connectors ..................11 List of Jumpers ......................14 2.3.1 Auto Power Button Enable/Disable Selection (JP1) ......14 2.3.2 Clear CMOS Jumper (JP2) ..............14 List of Connectors ....................
  • Page 12 AMI BIOS Setup ..................... 32 Setup Submenu: Main ..................33 Setup Submenu: Advanced ................. 34 3.4.1 Trusted Computing ................. 35 3.4.2 CPU Configuration .................. 37 3.4.3 Hardware Monitor ................... 38 3.4.4 SIO Configuration ................... 39 3.4.4.1 Serial Port 1 Configuration............40 3.4.4.2 Serial Port 2 Configuration ............41 3.4.5 GPIO Port Configuration ...............
  • Page 13 Appendix D – Quick Installation Guide ................66 Drive Installation ....................67 D.1.1 M.2 2230 Card Installation ..............68 D.1.2 M.2 2280 Card Installation ..............69 Preface XIII...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor PICO-SEMI Processor Intel® Pentium® Processor N4200 (4C/4T, 1.1 GHz, up to 2.5 GHz, TDP 6W) Intel® Celeron® Processor N3350 (2C/2T, 1.1 GHz, up to 2.4 GHz, TDP 6W) Chipset Intel® SoC Memory Type Onboard DDR3L 1866, Single Channel, Non-ECC BIOS UEFI Wake on LAN...
  • Page 16 Display Controller Intel® HD Graphics 500/505 LVDS/eDP Display Interface HDMI 1.4b x 1 (up to 3840 x 2160 @30Hz) Multiple Display Audio Codec Audio Interface Speaker External I/O Ethernet 10/100/1000Base RJ-45 x 2 (Realtek RTL8111H-CG) USB 3.2 Gen 1 x 2 Serial Port COM 1: RS-232 x 1 (Optional) COM 2: RS-232/422/485 x 1 (Ring/+5V/+12V) (Optional)
  • Page 17 Internal I/O Front Panel HDD LED, PWR LED, Power Button, Buzzer, Reset Other Expansion Mini PCIe/ mSATA M.2 2280 B-Key x 1 (SATA + USB 2.0) M.2 2230 E-Key x 1 (PCIe 3.0 [x1] + USB 2.0) Other Environmental & Certification Operating Temperature 32°F ~ 122°F (0°C ~ 50°C) with 0.5 m/s airflow Storage Temperature...

  • Page 18: Block Diagram

    Block Diagram Chapter 1 – Product Specifications...

  • Page 19: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 20: Dimensions

    Dimensions System Chapter 2 – Hardware Information...

  • Page 21: Component Side

    Board Component Side Com ponent Side Chapter 2 – Hardware Information...

  • Page 22: Solder Side

    Solder Side Solder Side Chapter 2 – Hardware Information...
  • Page 23 Rear I/O Configuration Phoenix DC Jack Chapter 2 – Hardware Information...

  • Page 24: Jumpers And Connectors

    Jumpers and Connectors System Chapter 2 – Hardware Information...
  • Page 25 Board Com ponent Side Chapter 2 – Hardware Information...
  • Page 26 Solder Side Chapter 2 – Hardware Information...

  • Page 27: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Auto Power Button Enable/Disable Selection Clear CMOS Jumper 2.3.1 Auto Power Button Enable/Disable Selection (JP1) 1 2 3 Enable/AT Disable/ATX (Default) Note: When disabled, the power button of CN3 (1-2) will be used to power on the...

  • Page 28: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function COM Port 2 COM Port 1 Front Panel Connector M.2 2230 E-Key Slot M.2 2280 B-Key Slot SPI Flash Programming Port CN11 HDMI Port...

  • Page 29: Com Port 2 (Cn1)

    2.4.1 COM Port 2 (CN1) RS-232 Pin Name Signal Type Signal Level DCD2 DSR2 RTS2 CTS2 DTR2 RI2/+5V/+12V +5V/+12V RS-485 Pin Name Signal Type Signal Level RS485_ D2- RS485_D2+ NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...

  • Page 30: Com Port 1 (Cn2)

    RS-485 Pin Name Signal Type Signal Level RS-422 Pin Name Signal Type Signal Level RS422_TX2- RS422_TX2+ RS422_RX2+ RS422_RX2- NC/+5V/+12V +5V/+12V Note: COM 2 RS-232/422/485 can be set by BIOS setting. Default is RS-232. Note: Pin 8 function can be changed by BOM. 2.4.2 COM Port 1 (CN2) RS-232...

  • Page 31: Front Panel Connector (Cn3)

    RS-232 Pin Name Signal Type Signal Level RTS1 CTS1 DTR1 2.4.3 Front Panel Connector (CN3) Pin Name Pin Name PWR_BTN- PWR_BTN+ HDD_LED- HDD_LED+ BUZZER- BUZZER+ PWR_LED- PWR_LED+ H/W RESET- H/W RESET+ 2.4.4 M.2 2230 E-Key Slot (CN4) Pin Name Signal Type Signal Level +3.3VSB +3.3V...
  • Page 32 Pin Name Signal Type Signal Level +3.3VSB +3.3V USB_D- DIFF PCIE_TX+ DIFF PCIE_TX- DIFF PCIE_RX+ DIFF PCIE_RX- DIFF Chapter 2 – Hardware Information...
  • Page 33 Pin Name Signal Type Signal Level PCIE_REF_CLK+ DIFF PCIE_REF_CLK- DIFF PCIE_RST# +3.3V PCIE_CLK_REQ# +3.3V W_DISABLE2# +3.3V PCIE_WAKE# +3.3V W_DISABLE1# +3.3V +3.3VSB +3.3V +3.3VSB +3.3V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 34: 2280 B-Key Slot (Cn5)

    2.4.5 M.2 2280 B-Key Slot (CN5) Pin Name Signal Type Signal Level +3.3V +3.3V +3.3V +3.3V USB_D+ DIFF USB_D- DIFF SSD_DAS# +3.3V DEVSLP +1.8V Chapter 2 – Hardware Information...
  • Page 35 Pin Name Signal Type Signal Level SATA_RX+ DIFF SATA_RX- DIFF SATA_TX- DIFF SATA_TX+ DIFF +3.3V +3.3V Chapter 2 – Hardware Information...

  • Page 36: Spi Flash Programming Port (Cn9)

    Pin Name Signal Type Signal Level +3.3V +3.3V +3.3V +3.3V 2.4.6 SPI Flash Programming Port (CN9) Pin Name Signal Type Signal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI SPI_CS Chapter 2 – Hardware Information...

  • Page 37: Hdmi Port (Cn11)

    2.4.7 HDMI Port (CN11) Pin Name Signal Type Signal Level TMDS_DAT2+ DIFF TMDS_DAT2- DIFF TMDS_DAT1+ DIFF TMDS_DAT1- DIFF TMDS_DAT0+ DIFF TMDS_DAT0- DIFF TMDS_CLK+ DIFF TMDS_CLK- DIFF DDC_CLK DDC_DATA HPLG_DETECT 2.4.8 Battery (CN12) Pin Name Signal Type Signal Level +3.3V 3.3V Chapter 2 –...

  • Page 38: Lan Port 1 (Cn13)

    2.4.9 RJ-45 LAN Port 1 (CN13) Pin Name Signal Type Signal Level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF 2.4.10 RJ-45 LAN Port 2 (CN14) ACT/LINK SPEED Pin Name Signal Type Signal Level MDI0+ DIFF...

  • Page 39: Usb 3.0 Ports 0 And 1 (Cn15)

    Pin Name Signal Type Signal Level MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF 2.4.11 USB 3.0 Ports 0 and 1 (CN15) Pin Name Signal Type Signal Level +5VSB USB0_D- DIFF USB0_D+ DIFF USB0_SSRX− DIFF USB0_SSRX+ DIFF USB0_SSTX−...

  • Page 40: Dc Power Jack (Optional) (Cn18)

    Pin Name Signal Type Signal Level USB1_SSTX− DIFF USB1_SSTX+ DIFF 2.4.12 +12V DC Power Jack (Optional) (CN18) Pin Name Signal Type Signal Level +12V +12V 2.4.13 Port 80 Debug Port (CN22) Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V...
  • Page 41 Pin Name Signal Type Signal Level LCLK I2C0_SDA +3.3V I2C0_SCL +3.3V SERIRQ +3.3V Chapter 2 – Hardware Information...

  • Page 42: Electrical Specifications For I/O Ports

    Electrical Specifications for I/O Ports Reference Signal Name Rate Output COM Port 2 +5V/+12V +5V/0.5A or +12V/0.5A M.2 2230 E-Key Slot +3.3VSB +3.3V/2A M.2 2280 B-Key Slot +3.3V +3.3V/2.5A USB Ports 0 and 1 CN15 +5VSB +5V/1A (per channel) Chapter 2 – Hardware Information...

  • Page 43: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 44: System Test And Initialization

    System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal. The system can usually continue the boot up sequence with non-fatal errors.

  • Page 45: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. Entering Setup Power on the computer and press <Del>or <ESC>...

  • Page 46: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 47: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 48: Trusted Computing

    3.4.1 Trusted Computing Options Summary Security Device Support Disable Enable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disable Enable Optimal Default, Failsafe Default...
  • Page 49 Options Summary Platform Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or disable Platform Hierarchy. Storage Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Storage Hierarchy. Endorsement Hierarchy Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Endorsement Hierarchy. TPM2.0 UEFI Spec Version TCG_1_2 TCG_2...

  • Page 50: Cpu Configuration

    3.4.2 CPU Configuration Options Summary C-States Disabled Enabled Optimal Default, Failsafe Default Enable/Disable C States. EIST™ Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Intel SpeedStep. Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Turbo Mode. Intel Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 51: Hardware Monitor

    Options Summary Enable/Disable CPU VT-d. Power Limit 1 Enable Disabled Optimal Default, Failsafe Default Enabled Enable/Disable Power Limit 1. 3.4.3 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 52: Sio Configuration

    3.4.4 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 53: Serial Port 1 Configuration

    3.4.4.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 54: Serial Port 2 Configuration

    3.4.4.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 55: Gpio Port Configuration

    3.4.5 GPIO Port Configuration Options Summary GPIO Port* Output Input Set GPIO as Input or Output. Output Level High Optimal Default, Failsafe Default Set output level when GPIO pin is Output. Chapter 3 – AMI BIOS Setup...

  • Page 56: Power Management

    3.4.6 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off RTC wake system from S5 Disable Optimal Default, Failsafe Default Fixed Time Fixed Time: System will wake on the hr::min::sec specified.

  • Page 57: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 58: North Bridge

    3.5.1 North Bridge Chapter 3 – AMI BIOS Setup...

  • Page 59: South Bridge

    3.5.2 South Bridge Options Summary M.2 PCI Express Root Port Disable Enable Optimal Default, Failsafe Default Auto Control the PCI Express Root Port. AUTO: To disable unused root port automatically for the most optimum power savings. Enable: Enable PCIe root port. Disable: Disable PCIe root port.

  • Page 60: Setup Submenu: Security

    Setup Submenu: Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.

  • Page 61: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable/Disable showing boot logo. Monitor Mwait Disable Enabled Auto Optimal Default, Failsafe Default Enable/Disable Monitor Mwait. To install Linux OS, please set this item to disable. Ipv4 PXE Support Disabled Optimal Default, Failsafe Default Enabled...

  • Page 62: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 63: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 64: Driver Download/Installation

    Driver Download/Installation Drivers for the PICO-APL4-SEMI can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/pico-itx-boards-pico-apl4-semi Download the driver(s) you need and follow the steps below to install them. Install Chipset Driver Open the Chipset Driver folder and open the SetupChipset.exe file Follow the instructions Drivers will be installed automatically Install Graphics Driver...
  • Page 65 Install Audio Driver Open the Audio Driver folder and open the 0006-64bit_Win7_Win8_Win81_Win10_R279.exe file Follow the instructions Driver will be installed automatically Install TXE Driver Open the ME & TXE Driver folder and open the SetupTXE.exe file Follow the instructions Driver will be installed automatically Install Peripheral Driver Open the ME &...

  • Page 66: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 67: Watchdog Timer Registers

    Watchdog Timer Registers Table 1: Watchdog Relative IO Address Default Value Note I/O Base I/O Base address for Watchdog operation. 0x2E Address This address is assigned by SIO LDN7 Table 2: Watchdog Relative Register Table Register Offset BitNum Value Note Enable/Disable Watchdog time out output via WDTRST#...

  • Page 68: A.2 Watchdog Sample Program

    A.2 Watchdog Sample Program ****************************************************************************** // WDT I/O operation relative definition (Please reference to Table 1) #define WDTAddr 0x510 // WDT I/O base address Void WDTWriteByte(byte Register, byte Value); byte WDTReadByte(byte Register); Void WDTSetReg(byte Register, byte Bit, byte Val); // Watch Dog relative definition (Please reference to Table 2) #define DevReg 0x00 // Device configuration register #define WDTRstBit 0x80 // Watchdog WDTRST# (Bit7)
  • Page 69 ******************************************************************************* // Procedure : AaeonWDTEnable VOID EnterSIOconfig IOWriteByte (IoConfAddr,0x87); IOWriteByte (IoConfAddr,0x87); VOID ExitSIOconfig IOWriteByte (IoConfAddr,0xAA); VOID SetWDT IOWriteByte (IoConfAddr,0x2B); IOWriteByte(IoConfAddr+1, (IOReadByte(IoConfAddr+1)&0xFC)); // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable(1); // Procedure : AaeonWDTConfig AaeonWDTConfig (byte Counter, BOOLEAN Unit) VOID // Disable WDT counting WDTEnableDisable( // Clear Watchdog Timeout Status WDTClearTimeoutStatus();...
  • Page 70 WDTSetBit( TimerReg, UnitBit, Unit // WDT output mode set to pulse WDTSetBit( TimerReg, ModeBit, ModeVal // WDT output mode set to active low WDTSetBit( TimerReg, PolarityBit, PolarityVal // WDT output pulse width is 25ms WDTSetBit( TimerReg, PSWidthBit, PSWidthVal // Watchdog WDTRST# Enable WDTSetBit( DevReg, WDTRstBit, WDTRstVal WDTClearTimeoutStatus()

  • Page 71: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 72: I/O Address Map

    I/O Address Map Appendix B – I/O Information...

  • Page 73: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 74: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 75 Appendix B – I/O Information...
  • Page 76 Appendix B – I/O Information...

  • Page 77: Appendix C - Mating Connectors

    Appendix C Appendix C – Mating Connectors...

  • Page 78: List Of Mating Connectors And Cables

    List of Mating Connectors and Cables The table notes mating connectors and available cables. Conn Mating Connector Function Available Cable Cable P/N Label Vendor Model no CN1 COM Port #2 Conn JST SHR-09V-S-B Serial Port Cable 1701090122 CN2 COM Port #1 Conn JST SHR-09V-S-B Serial Port Cable 1701090122 50247-010H0...

  • Page 79: Appendix D - Quick Installation Guide

    Appendix D Appendix D – Quick Installation Guide...

  • Page 80: Drive Installation

    Drive Installation Loosen the screws on the chassis. Appendix D – Quick Installation Guide...

  • Page 81: D.1.1 M.2 2230 Card Installation

    D.1.1 M.2 2230 Card Installation Loosen the screws on the MB, insert the M.2 2230 card into the socket at an angle of approximately 30 degrees. Push down the M.2 2230 card until it is attached. Place the screw above the card to ensure the is card in position, then fasten the screw, affixing the card onto the MB.

  • Page 82: D.1.2 M.2 2280 Card Installation

    D.1.2 M.2 2280 Card Installation Loosen the screws on the MB, insert the M.2 2280 card into the socket at an angle of approximately 30 degrees. Push down the M.2 2280 card until it is attached. Place the screw above the card to fix the card on the position then fasten the screw on the MB.