Intersil ISLVERSALDEMO3Z Manual

Demonstration board

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ISLVERSALDEMO3Z

The ISLVERSALDEMO3Z demonstration board

provides power management for the AMD Space

Grade Versal AI Edge Adaptive SOC

using Renesas' Radiation Tolerant Power

Management devices. The Versal system requires

various supply rails, including the core, digital, analog,

and DDR memory. The ISLVERSALDEMO3Z

provides all these rails for the user to evaluate the

performance against the Versal DC and AC electrical

specifications.

Power Supply Specifications

▪ +12V

±10% (Banana Jack Connectors)

12V

5VBUS1

ISL73007

5VBUS2

ISL73007

Figure 1. AMD Space Grade Versal AI Edge XQRVE2302 Power Management Block Diagram

R34UZ0029EU0101 Rev.1.01

Oct 17, 2024

XQRVE2302

VCCO_50x, VCCO_HDIO

1.8V-3.3V/3A

ISL73007

VCCO_XPIO

1.0V-1.5V/3A

ISL73007

VCCINT, VCC_RAM,

VCC_SOC, VCC_I/O,

VCC_PMC, VCC_PSFP,

2Ph PWM

VCC_PSLP

Controller w/

0.8V/50A

PMBus (x1)

ISL73041 (x1)

ISL70020 (x4)

VCCAUX, VCCAUX_PMC

VCCAUX_SMON

ISL73007

VGTYP_AVCC,

0.88V/700mA

Low Noise LDO

VGTYP_AVCCAUX,

1.5V/50mA

Low Noise LDO

VGTYP_AVTT,

ISL71001

VDD, 1.2V/3A

ISL73005

VTT, 0.6V/1A

VPP, 2.5V/1A

Demonstration Board Manual

Features

▪ Fully qualified radiation tolerant power solution

• All power management devices are qualified to

Renesas Rad Tolerant Screening and QCI Flow

(R34TB0004EU)

▪ Designed to power AMD's Versal AI Edge Adaptive

SoC, XQRVE2302

▪ Includes regulators for all XQRVE2302 rails, DDR4

memory and general +5V bus

▪ Power supply sequencing for power up and down

for increased system reliability

▪ All DC-DC switching converters are clock

synchronized

1.5V/1.1A

1.2V/6A

VDD/VDDQ

DDR4/

VTT

LPDDR4

VPP

AMD

Versal

AI Edge

Page 1

Table of Contents

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Summary of Contents for Intersil ISLVERSALDEMO3Z

Page 1 (R34TB0004EU) various supply rails, including the core, digital, analog, ▪ Designed to power AMD’s Versal AI Edge Adaptive and DDR memory. The ISLVERSALDEMO3Z SoC, XQRVE2302 provides all these rails for the user to evaluate the performance against the Versal DC and AC electrical ▪...
Page 2: Table Of Contents
ISLVERSALDEMO3Z Demonstration Board Manual Contents Functional Description ..............3 Power Tree .
Page 3: Functional Description
1. The power management solution is developed for the Minimum Rails application of the AMD Versal XQRVE2302.The ISLVERSALDEMO3Z demonstration board operates on a +12V DC power supply. Two front end DC/DC regulators provide two +5.0V system rails that power all the other POL DC/DC regulators, the Quad Clock Generator chips, and some minor supporting circuitry.
Page 4: Renesas Power Management Solution
ISLVERSALDEMO3Z Demonstration Board Manual Table 1. AMD Space Grade Versal AI Edge XQRVE2302 Power Management Specifications Power Current Renesas Rail Voltage Rail Name DC Tol AC Tol Sequencing Demand Solution 5.0V 5VBUS1 ISL73007 5.0V 5VBUS2 ISL73007 VCCO_500, VCCO_501, +3%/-5% for 3.3V, 1.8V, 2.5V or 3.3V...
Page 5: Adjustable Output Voltages
The AMD Versal XQRVE2302 specifies different operating voltage on certain digital rails; for example, the VCCO_XPIO and VCCO_50x rails can be set for different digital logic I/O levels required by the user. The ISLVERSALDEMO3Z includes the necessary jumpers to change the feedback resistors to set the different output voltage.
Page 6: Output Voltage Monitor Test Points And Load Transient Generators
Output Voltage Monitor Test Points and Load Transient Generators The ISLVERSALDEMO3Z provides test points for monitoring the output voltage and terminals to apply an external load current. Most output rails also provide an on-board transient load step generator. The on-board transient load generator can be turned on by an on-board switch (SW) to automatically generate load steps.
Page 7 Figure 8 show the input connection to all the transient load generator controls on the ISLVERSALDEMO3Z. The load comprises multiple parallel 2W-rated, 2512-sized resistors. Note: The VGTYP_AVCCAUX uses a single 1/8W-rated, 0805-sized resistor. The transient load generator is intended for pulse load operation only where the frequency and duty cycle of the load do not exceed the power dissipation of the resistors.
Page 8 ISLVERSALDEMO3Z Demonstration Board Manual Figure 3. ISL73007_VCCO_50X_HDIO Load Generator Input Orientation Figure 4. ISL73007_VCCO_XPIO Load Generator Input Orientation R34UZ0029EU0101 Rev.1.01 Page 8 Oct 17, 2024...
Page 9 ISLVERSALDEMO3Z Demonstration Board Manual Figure 5. VCCINT Load Generator Input Orientation Figure 6. ISL73007_VCCAUX Load Generator Input Orientation R34UZ0029EU0101 Rev.1.01 Page 9 Oct 17, 2024...
Page 10 ISLVERSALDEMO3Z Demonstration Board Manual Figure 7. VGTYP_AVCC Load Generator Input Orientation Figure 8. VGTYP_AVCCAUX Load Generator Input Orientation R34UZ0029EU0101 Rev.1.01 Page 10 Oct 17, 2024...
Page 11: V/40A Core Rail Design
PMBus, one ISL71441M GaN FET Driver, and four ISL70020SEH 40V GaN FETs in the bump die package. Each PWM Controller is a dual-phase IC but only one phase is being used for the ISLVERSALDEMO3Z to reduce the overall footprint of the VCCINT rail.
Page 12: Power Sequence And Monitoring
ISLVERSALDEMO3Z Demonstration Board Manual Power Sequence and Monitoring The two ISL70321SEH quad rail sequencers handle the power sequencing and monitoring of all supply rails. When a sequence up or down is initiated, the supply rails are enabled or disabled in a sequence, shown in...
Page 13: Power Led Indicators
Figure 13. Power LED Indicator 12V Power Supply and Sequencing Initialization The +12VDC power supply to the ISLVERSALDEMO3Z is provided by banana jack inputs to the board. Back-to-back PMOS FETs prevent reverse current flow back to the power supply. Mechanical switch SW801 turns the power on and off for the board.
Page 14: Switching Converter Clock Synchronization
ISLVERSALDEMO3Z Demonstration Board Manual Switching Converter Clock Synchronization All the DC/DC converters on the ISLVERSALDEMO3Z are clock synchronized with two Quad Clock Generators configured as a Clock controller and Clock target. The circuit generates 0V to 5V clocks at various frequencies and phases to the different rails.
Page 15: Bus Current Sensing And Kill Comparator
ISLVERSALDEMO3Z Demonstration Board Manual 1.10 +12V Bus Current Sensing and KILL Comparator The total +12V bus supply current to the Versal rails can be monitored as a voltage (ADC_ISENSE) through the ISL70100 current-sense amplifier. The circuit converts 0A to 25A to an output voltage of 0V to 2.25V. The output...
Page 16: All Voltage Rail Monitoring
ISLVERSALDEMO3Z Demonstration Board Manual ▪ R975 is the bottom resistor in the comparator non-inverting input voltage divider reference in volts. Renesas recommends using the 10kΩ installed by default. ▪ R977 is the hysteresis resistor in ohms. Make this resistor 5 to 50 times larger than R975.
Page 17: Board Design
+ Local Load Transient VDD, DDR VTT ISL73007 5V Generator Generator Generator BUS1 Figure 20. Board Layout For the ISLVERSALDEMO3Z schematic diagram, bill of materials, and board layout files, download the design files from the website. R34UZ0029EU0101 Rev.1.01 Page 17 Oct 17, 2024...
Page 18: Typical Performance Graphs
ISLVERSALDEMO3Z Demonstration Board Manual Typical Performance Graphs Figure 22. Power-Down Sequencing, Ch1-8 Figure 21. Power-Up Sequencing, Ch1-8 Figure 24. Power-Down Sequencing, Ch9-13 Figure 23. Power-Up Sequencing, Ch9-13 Figure 25. VCCINT Rail 24A Load Step Transient with Figure 26. ISL73007_VCCO_50X_HDIO 1.8V Rail 1.11A ±17mV Compliance Window...
Page 19 ISLVERSALDEMO3Z Demonstration Board Manual Figure 27. ISL73007_VCCO_50X_HDIO 2.5V Rail 2.78A Figure 28. ISL73007_VCCO_50X_HDIO 3.3V Rail 3.67A Load Step with ±125mV Compliance Window Load Step with +99mV/-165mV Compliance Window Figure 30. ISL73007_VCC_XPIO 1.2V Rail 3A Load Step Figure 29. ISL73007_VCC_XPIO 1V Rail 2.5A Load Step with ±60mV Compliance Window...
Page 20 ISLVERSALDEMO3Z Demonstration Board Manual Figure 33. VCCINT Rail Steady State Ripple at 25A with Figure 34. ISL73007_VCCO_50X_HDIO 1.8V Rail Steady ±17mV Compliance Window State Ripple at 3A with ±90mV Compliance Window Figure 35. ISL73007_VCCO_50X_HDIO 2.5V Rail Steady Figure 36. ISL73007_VCCO_50X_HDIO 3.3V Rail Steady State Ripple at 3A with ±75mV Compliance Window...
Page 21 ISLVERSALDEMO3Z Demonstration Board Manual Figure 39. ISL73007_VCCO_XPIO 1.5V Rail Steady State Figure 40. ISL73007_VCCAUX 1.5V Rail Steady State Ripple at 3A with ±75mV Compliance Window Ripple at 3A with ±30mV Compliance Window Figure 41. VGTYP_AVCC 0.88V Rail Steady State Noise Figure 42.
Page 22: Ordering Information
ISLVERSALDEMO3Z Demonstration Board Manual Figure 45. Quad Clock Generator Target Synchronization Clocks Ordering Information Part Number Description ISLVERSALDEMO3Z Rad Tolerant Power Management Demonstration Board Revision History Revision Date Description Changed ACAP to Adaptive SOC or left blank throughout. Changed VC2302 to XQRVE2302.
Page 23 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS.

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