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Intersil CDP1802BCE Manual

Cmos 8-bit microprocessors
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TM
March 1997
Features
• Maximum Input Clock Maximum Frequency Options
At V
= 5V
DD
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 3.2MHz
- CDP1802BC . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MHz
• Maximum Input Clock Maximum Frequency Options
At V
= 10V
DD
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . 6.4MHz
• Minimum Instruction Fetch
At V
= 5V
DD
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs
- CDP1802BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs
• Any Combination of Standard RAM and ROM Up to
65,536 Bytes
• 8
Bit Parallel Organization With Bidirectional Data Bus
-
and Multiplexed Address Bus
• 16 x 16 Matrix of Registers for Use as Multiple
Program Counters, Data Pointers, or Data Registers
• On
Chip DMA, Interrupt, and Flag Inputs
-
• Programmable Single
• 91 Easy
to
Use Instructions
-
-

Ordering Information

PART NUMBER
5V - 3.2MHz
CDP1802ACE
CDP1802ACEX
CDP1802ACQ
CDP1802ACD
CDP1802ACDX
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
1-888-INTERSIL or 321-724-7143
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Execute Times
-
Bit Output Port
-
5V - 5MHz
TEMPERATURE RANGE
CDP1802BCE
CDP1802BCEX
CDP1802BCQ
-
CDP1802BCDX
CDP1802A, CDP1802AC,
CMOS 8-Bit Microprocessors
Description
The CDP1802 family of CMOS microprocessors are 8-bit
register oriented central processing units (CPUs) designed
for use as general purpose computing or control elements in
a wide range of stored program systems or products.
The CDP1802 types include all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili-
tate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchro-
nous interface to memories and external controllers for I/O
devices, and minimizes the cost of interface controllers. Fur-
ther, the I/O interface is capable of supporting devices oper-
ating in polled, interrupt driven, or direct memory access
modes.
The CDP1802A and CDP1802AC have a maximum input
clock frequency of 3.2MHz at V
CDP1802AC are functionally identical. They differ in that the
CDP1802A has a recommended operating voltage range of
4V to 10.5V, and the CDP1802AC a recommended operat-
ing voltage range of 4V to 6.5V.
The CDP1802BC is a higher speed version of the
CDP1802AC, having a maximum input clock frequency of
5.0MHz at V
= 5V, and a recommended operating voltage
DD
range of 4V to 6.5V.
PACKAGE
o
o
-40
C to +85
C
PDIP
Burn-In
o
o
-40
C to +85
C
PLCC
o
o
-40
C to +85
C
SBDIP
Burn-In
3-3
CDP1802BC
= 5V. The CDP1802A and
DD
PKG. NO.
E40.6
E40.6
N44.65
D40.6
D40.6
1305.2
File Number

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Summary of Contents for Intersil CDP1802BCE

  • Page 1: Ordering Information

    Burn-In D40.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1305.2 File Number 1-888-INTERSIL or 321-724-7143 Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved...

  • Page 2: Top View

    CDP1802A, CDP1802AC, CDP1802BC Pinouts 40 LEAD PDIP (PACKAGE SUFFIX E) 44 LEAD PLCC 40 LEAD SBDIP (PACKAGE SUFFIX D) (PACKAGE TYPE Q) TOP VIEW TOP VIEW CLOCK WAIT XTAL CLEAR DMA IN DMA OUT INTERRUPT 44 43 42 41 40 BUS 7 BUS 6 BUS 7...

  • Page 3: Block Diagram

    CDP1802A, CDP1802AC, CDP1802BC Block Diagram I/O REQUESTS MEMORY ADDRESS LINES I/O FLAGS CONTROL CLEAR WAIT MA7 MA5 MA3 MA1 CLOCK CLOCK LOGIC XTAL STATE CODES CONTROL AND Q LOGIC TIMING LOGIC SYSTEM TIMING TO INSTRUCTION DECODE REGISTER R(0).1 R(0).0 ARRAY R(1).1 R(1).0 INCR/...

  • Page 4: Test Conditions

    CDP1802A, CDP1802AC, CDP1802BC Absolute Maximum Ratings Thermal Information θ θ DC Supply Voltage Range, (V Thermal Resistance (Typical, Note 4) C/W) C/W) (All Voltages Referenced to V Terminal) PDIP ......CDP1802A.
  • Page 5 CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at T = -40 C to +85 C, Except as Noted CDP1802AC, TEST CONDITIONS CDP1802A CDP1802BC (NOTE 1) (NOTE 1) PARAMETER SYMBOL UNITS µA Quiescent Device Current µA Output Low Drive (Sink) Current 0, 5 (Except XTAL) 0, 10 µA...
  • Page 6 CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at T = -40 C to +85 C, Except as Noted (Continued) CDP1802AC, TEST CONDITIONS CDP1802A CDP1802BC (NOTE 1) (NOTE 1) PARAMETER SYMBOL UNITS Input Capacitance Output Capacitance NOTES: 1. Typical values are for T = +25 C and nominal V 2.
  • Page 7 CDP1802A, CDP1802AC, CDP1802BC ±5%, Except as Noted (Continued) Dynamic Electrical Specifications = -40 C to +85 C, C = 50pF, V TEST CDP1802A, CONDITIONS CDP1802AC CDP1802BC (NOTE 1) (NOTE 1) PARAMETER SYMBOL UNITS Clock to State Code Clock to Q Clock to N (0 - 2) MINIMUM SET UP AND HOLD TIMES Data Bus Input Set Up...
  • Page 8 CDP1802A, CDP1802AC, CDP1802BC ±5%, Except as Noted (Continued) Dynamic Electrical Specifications = -40 C to +85 C, C = 50pF, V TEST CDP1802A, CONDITIONS CDP1802AC CDP1802BC (NOTE 1) (NOTE 1) PARAMETER SYMBOL UNITS EF1-4 Set Up EF1-4 Hold (Note 2) Minimum Pulse Width Times CLEAR Pulse Width (Note 2)

  • Page 9: Timing Waveforms

    CDP1802A, CDP1802AC, CDP1802BC Timing Specifications as a function of T(T = 1/f ) at T = -40 to +85 C, Except as Noted CLOCK CDP1802A, TEST CONDITIONS CDP1802AC CDP1802BC (NOTE 1) (NOTE 1) PARAMETERS SYMBOL UNITS Required Memory Access Time Ad- 5T-375 5T-250 5T-225...
  • Page 10 CDP1802A, CDP1802AC, CDP1802BC Timing Waveforms (Continued) CLOCK MEMORY HIGH ORDER LOW ORDER ADDRESS ADDRESS BYTE ADDRESS BYTE (MEMORY READ CYCLE) (MEMORY WRITE CYCLE) DATA FROM CPU TO BUS STATE CODES N0, N1, N2 (I/O EXECUTION CYCLE) DATA LATCHED IN CPU DATA FROM BUS TO CPU DMA SAMPLED (S1, S2, S3)
  • Page 11 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) CLOCK MACHINE CYCLE n CYCLE (n + 1) CYCLE (n + 2) CYCLE HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS HIGH ADD LOW ADDRESS FIGURE 5. GENERAL TIMING WAVEFORMS INSTRUCTION FETCH (S0) EXECUTE (S1)
  • Page 12 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) INSTRUCTION FETCH (S0) EXECUTE (S1) FETCH (S0) EXECUTE MEMORY READ CYCLE MEMORY READ CYCLE MEMORY READ CYCLE MWR (HIGH) MEMORY OUTPUT VALID VALID VALID OUTPUT ALLOWABLE MEMORY ACCESS OUTPUT OUTPUT “DON’T CARE”...
  • Page 13 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) CLOCK MACHINE CYCLE n CYCLE (n + 1) CYCLE INSTRUCTION FETCH (S0) EXECUTE (S1) N0 - N2 N = 9 - F MEMORY OUTPUT VALID OUTPUT ALLOWABLE MEMORY ACCESS DATA VALID DATA FROM INPUT DEVICE (NOTE 1)
  • Page 14 CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) CLOCK MACHINE CYCLE n CYCLE (n+1) CYCLE (n+2) CYCLE INSTRUCTION FETCH (S0) EXECUTE (S1) DMA (S2) DMA-IN MEMORY OUTPUT VALID OUTPUT VALID DATA FROM INPUT DEVICE DATA BUS (NOTE 1) MEMORY READ CYCLE MEMORY READ, WRITE...

  • Page 15: Performance Curves

    CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued) CLOCK MACHINE CYCLE n CYCLE (n + 1) CYCLE (n + 2) CYCLE INSTRUCTION FETCH (S0) EXECUTE (S1) INTERRUPT (S3) INTERRUPT (NOTE 1) (INTERNAL) IE MEMORY OUTPUT VALID OUTPUT MEMORY READ, WRITE MEMORY READ CYCLE NON-MEMORY CYCLE...

  • Page 16: Current Characteristics

    CDP1802A, CDP1802AC, CDP1802BC Performance Curves (Continued) , DRAIN-TO-SOURCE VOLTAGE (V) = 5V = 25 , GATE-TO-VOLTAGE = -5V = 10V -10V = 5V = 10V , AMBIENT TEMPERATURE = -40 C TO +85 100 125 , LOAD CAPACITANCE (pF) FIGURE 17. TYPICAL TRANSITION TIME vs LOAD CAPACI- FIGURE 18.

  • Page 17: Signal Descriptions

    CDP1802A, CDP1802AC, CDP1802BC Performance Curves (Continued) = -40 C TO +85 = 25 = 5V ∆t = 10V ∆t , GATE-TO-SOURCE = 5V = 5V = 10V ∆C , ∆ LOAD CAPACITANCE (pF) , DRAIN-TO-SOURCE VOLTAGE (V) NOTE: ANY OUTPUT EXCEPT XTAL FIGURE 21.
  • Page 18 CDP1802A, CDP1802AC, CDP1802BC INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests) memory does not have a three-state high-impedance output, MRD is useful for driving memory/bus separator gates. It is These inputs are sampled by the CPU during the interval also used to indicate the direction of data transfer during an between the leading edge of TPB and the leading edge of I/O instruction.
  • Page 19 CDP1802A, CDP1802AC, CDP1802BC The three paths, depending on the nature of the instruction, Data Pointers may operate independently or in various combinations in the The registers in R may be used as data pointers to indicate a same machine cycle. location in memory.
  • Page 20 CDP1802A, CDP1802AC, CDP1802BC Interrupt Servicing pressed during the initialization cycle. The next cycle is an S0, S1, or an S2 but never an S3. With the use of a 71 instruction Register R(1) is always used as the program counter when- followed by 00 at memory locations 0000 and 0001, this feature ever interrupt servicing is initiated.

  • Page 21: Operation

    CDP1802A, CDP1802AC, CDP1802BC loaded into D, and R(N) is incremented by 1. IDLE • DMA • INT FORCE S1 S1 RESET (LONG BRANCH, LONG SKIP, NOP, ETC.) S1 EXECUTE S1 INIT INT • DMA DMA • IDLE • INT S2 DMA S3 INT DMA •...
  • Page 22 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION MNEMONIC CODE OPERATION M(R(X)) XOR D → D EXCLUSIVE OR M(R(P)) XOR D → D; R(P) + 1 → R(P) EXCLUSIVE OR IMMEDIATE M(R(X)) AND D → D M(R(P)) AND D → D; R(P) + 1 → R(P) AND IMMEDIATE SHIFT D RIGHT, LSB(D) →...
  • Page 23 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION MNEMONIC CODE OPERATION IF EF1 =1, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF1 = 1 (EF1 = V IF EF1 = 0, M(R(P)) → R(P).0, ELSE R(P) + 1 → R(P) SHORT BRANCH IF EF1 = 0 (EF1 = V IF EF2 = 1, M(R(P)) →...
  • Page 24 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION MNEMONIC CODE OPERATION 0 → Q RESET Q T → M(R(X)) SAVE (X, P) → T; (X, P) → M(R(2)), THEN P → X; R(2) - 1 → R(2) PUSH X, P TO STACK MARK M(R(X)) →...
  • Page 25 CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION MNEMONIC CODE OPERATION NOTES: (For Table 1) 1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF. After an add instruction: DF = 1 denotes a carry has occurred DF = 0 Denotes a carry has not occurred After a subtract instruction: DF = 1 denotes no borrow.
  • Page 26 CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES DATA MEMORY STATE SYMBOL OPERATION ADDRESS LINES NOTES 0 → I, N, Q, X, P; 1 → lE RESET XXXX 0000 → R Initialize, Not Programmer XXXX Accessible...
  • Page 27 CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) DATA MEMORY STATE SYMBOL OPERATION ADDRESS LINES NOTES (X, P) → T, MR2; P → X; MARK Fig. 7 R2 - 1 → R2 0 →...
  • Page 28 Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

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