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Theory
of
Operation—
DC
S01
THEORY
OF
OPERATION
Introduction
This
section
of
the
manual
contains
an
electrical
description
of
the
circuits
in
the
DC
501
100
MHz
Counter.
A
block diagram
is
shown
in
Fig. 2-1,
and
complete
schematics
are
given
on
pullout pages
in
the
Servicing
Information
section.
BLOCK DIAGRAM
DESCRIPTION
Signals to
be counted
are
applied
via
the
EXT
INPUT
connector
or
via
pin
16A
at
the
rear interface,
attenuators,
and
a
coupling capacitor to the
signal-shaping
circuit.
This
circuit
conditions the input
signal
and produces an output
suitable to drive
the
first
decade
counter.
The
time-base
circuit
gerterates
the
signals
which
deter
mine
when
the
raunter
is
allowed to
count
(GATE),
when
the
readout
display
is
updated
(LATCH),
artd
when
the
counter
is
cleared
or
reset
(CLEAR,
CLEAR,
or
RESET).
The
generation and the
time
relationship
between
these
signals
are
determined
by
the
front-panel
MEASUREMENT
INTERVAL. DISPLAY
TIME,
Manual Gate
START/STOP,
and
RESET
controls.
The
decade
counter
units receive
the
shaped
input
signal
when
the gate
is
"open". Each
DCU
corresponds
to
one
of
the
display
LED's. Immediately
upon
closure of the
GATE,
the
LATCH
locks the
sample
taken
into
the storage
register.
If
the
sample
taken exceeds the seven
available
display
digits,
the excessive
count
spills
over
arxi
is
Irxlicated
by
the
OVERFLOW
LED
on
the
front panel.
Before
a
new
sample
of
the
input
signal
is
taken, the time-base
circuit
sends
in
a
CLEAR
pulse to
reset
ail
the
DCU's
to zero.
The
multiplexing
circuit
scans the latches of the storage
register at
a 2-kilohertz
rate,
enabling
each
latch
ar>d
its
corresponding
display
LED
sequentially
on
a time-shared
basis.
The
BCD
output
of the storage
register
is
decoded
and
the correct
combination
of
LED
segments
is
lighted
to
di^lay any
digit
between 0 and
9.
Also, the
decoder and
display-multiplexing
circuit
provides leading-zero suppres-
sion
if
the display
is
within the
display-register capacity.
Decimal
point location
is
a
function of the
MEASURE-
MENT
INTERVAL
switch.
CIRCUIT DESCRIPTION
Input
Circuit
Signals to
be counted
are applied
via
front-panel
INPUT
connector J100.
or
via
the
internal
input
at
pin
16A
at
the
rear
interface,
to
the attenuators.
The
attenuators
are
frequency-compensated
voltage dividers consisting
of
resis-
tors
R102-R107
and
capacitors
C102-C107.
Switches
S1(X)A and
S100B
allow front-panel
selection of
XI.
X5.
X10,
or
X50
attenuation of the input
signal.
Cl
10
provides
AC
coupling.
FET
source
follower
Q115
and
emitter follower
Q122
present
a
high
impedance
to the input
signal.
Thediodes
in
the base
circuit
of
E.
F.
Q128
form
a
series-limiter
and
clamping network,
which
reduces the input
signal
to
limits
suitable
for
driving
the shaping
circuits.
The
clamping
diodes
limit
the voltage at the emitter of
Q128
to
a
dynamic
rar>ge
of
about
1.2 volts.
U150B,
an
OR
gate
integrated circuit
with
push-pull
outputs,
is
connected
as a
Schmitt
trigger.
It
shapes the
input
signal
into a
square wave.
Its
"hysteresis
window"
is
a
width
of
about
200
mV.
The
output changes
states
when
the
signal
voltage passes
through the upper
threshold,
then
reverts
to
its
original state
when
the
signal
voltage passes
through the lower
threshold.
For
this reason,
an
input
signal
smaller
in
amplitude than
the
width
of the hysteresis
window
cannot
activate
the counting
circuits.
The
quiescent
level
at
the input of
U150B
can be
adjusted
to
overcome
some
of
the
triggering difficulties
arising
from
various
input-signal
shapes
and
frequencies.
Integrated-circuit
operational amplifier
U
135 and
its
associ-
ated
discrete
components
are
connected
as
a
voltage
follower.
TRIGGER LEVEL
potentiometer
R135
selects
a
voltage
between
ground
arxl
about
-2
volts
and
applies
it
to pin
3
of
U
135.
This
level
is
then
established
at
pin
2.
and
hence, the input
of
U150B,
Through
the action of the
operational
amplifier.
The
output
of
U150B
is
applied
to
U150A, whose
push-pull
outputs
drive
Q160
and
Q162, which
are
con-
rtected
as a
differential
pair.
This
circuit
provides
a
level
shift
to
TTL
level,
and
further
shapes the
signal
to
be
counted.
A
waveform
with
fast rising
and
falling
edges
is
produced
at
The
collector
of
Q160.
CR165
limits
the
amplitude
of the
count
signal
to
5
volts,
clampirtg
the
2-2
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