Clock Rate Multiplier - Quatech QSC-200 User Manual

4.4 Options Register
The Options Register allows software to identify the QSC-200/300 as a Quatech
Enhanced Serial Adapter. It also allows software to set the UART clock rate multiplier. Figure
10 shows the structure of the Options Register.
The powerup default of the Options Register is all bits zero.
7 (MSB)
4.4.1 Enhanced Serial Adapter Identification
The ID bits are used to identify the QSC-200/300 as a Quatech Enhanced Serial Adapter.
Logic operations are performed such that the values read back from these bits will not necessarily
be the values that were written to them. Bit ID1 will return the logical-AND of the values
written to ID[1:0], while bit ID0 will return their exclusive-OR.
Software can thus identify a Quatech Enhanced Serial Adapter by writing the ID bits with
the patterns shown in the "write" column of Figure 11, then reading the bits and comparing the
result with the patterns in the "read" column. Matching read patterns verify the presence of the
Options Register.

4.4.2 Clock Rate Multiplier

Quatech QSC-200/300 Users Manual
Bit Name
ID1
6 ID0
5 -
4 -
3 -
2 -
1 RR1
0 RR0
Figure 10--- Options Register bit definitions
Write
ID1
0
0
1
1
Figure 11 --- ID bit write/read table
Description
ID bit 1
ID bit 0
(reserved, 0)
(reserved, 0)
(reserved, 0)
(reserved, 0)
Clock rate multiplier bit 1
Clock rate multiplier bit 0
Read
ID0 ID1 ID0
0 0 0
1 0 1
0 0 1
1 1 0
16