Teletype SA110 Description And Operation page 9

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or eleventh) has occurred. Another input is from
the bit timer, indicating that the cycle is at 0.3
bit after the tenth clock pulse (10-unit code) or
0.1 bit after the eleventh clock pulse (11-unit
code), depending on the code strapping. A third
input is from NAND gate MLD2-1l, indicating
apparent synchronization between the regener-
ator and the incoming signal. The last input is
from the TC FF to inhibit the output from changing
states at the start of a character. Normally,
when the first, second, and fourth inputs are
high, the regenerator will be in synchronization
and so the third input will be high also. This
makes the output low, resetting the TCFF. If
the third input is low at this time, tile TCFF will
not be reset and the bit timer counter will con-
tinue to run until a marking bit is shifted into the
OFF. Any spacing bits appearing at this time
will not be passed on to the terminal, since the
output amplifier remains locked in the mark
hold state. When the marking bit arrives, the
TCFF and the bit timer counter are reset. The
next spacing pulse to appear on the input data
lead is recognized as the start of the next charac-
ter. Any additional marking bits· appearing
between the marking bit which resets .the TCFF
and the next spacing bit will not be passed on to
the terminal either. Therefore, the SAl 10
restores synchronization by rejecting first
spacing and then marking bits until it detects a
character ,that has either a valid stop pulse or
correct parity. Synchronization will be restored
by this process after from two to fifteen charac-
ters have elapsed. While this is taking place,
the terminal will copy garbled characters at a
speed less than the incoming character rate.
Note: A continuously spacing line {line break)
causes slightly different operation, depending
on whether the SA110 is strapped for even or
odd parity and whether the break occurs in
the middle of a character or after the end· of a
character. For even parity, a single garbled
character will be passed to the terminal if the
break causes the last character to have incor-
rect parity. (This character will also be mis-
sing a stop pulse because of the break, so the
logic will lock in the mark hold state.) Con-
tinuous NULL characters will be passed to
the terminal if the break occurs between
characters or if the last character retains
correct parity. {This is because the NULL
character - all information bits spacing -
has correct even parity. NULL characters
are created by the MH gate adding the mini-
mum stop pulse to the spacing line at the
correct point for each character. ) For odd
parity, only one garbled character or NULL
ISS 1, SECTION 578-200-100
character will be presented to the terminal
before the logic goes to the mark hold state.
(NULL has incorrect odd parity.) In any case,
the terminal is unable to detect the continu-
ously spacing line when the SAl 10 is present,
and so any break detection circuitry or indi-
cator that it may have is disabled. The oper-
ator should be able
to
recognize that a break
has occurred from the interrupted message
or continuous NULL characters {for even
parity), however.
3 .16 As a strap option, the SA110 can check
the incoming characters for significantly
distorted information bits in addition to checking
parity, in order to detect transmission errors
which leave the characters with correct parity.
This circuitry consists of the mark-space flip-
flop (MSFF), the space-mark flip-flop (SMFF),
and the distortion detect flip-flop {DOFF). When
used, the DOFF output is strapped to the input
of NANO gate MLD2-3 to control the output of
the PE gate. Incoming data bits from the input
amplifier are coupled to the clock pulse input of
the MSFFviaan RC networkand, after inversion
by MLC3-10, are coupled to the clock pulse input
of the SMFF via a similar network. Both flip-
flops are set on every clock pulse. When a bit
having a mark-to-space transition is received,
the MSFF is reset, and when a bit having a space-
to-mark transition is r.eceived, the SMFF is
· reset. If another mark-to-space or space-to-
mark transition is received before the next clock
pulse, the affected flip-flop will toggle back to
the set state again. The inverted outputs of these
flip-flops are the inputs of NANO gate MLA4-11,
whose output is inverted by MLA4-8 and con-
nected to the reset prime of the DOFF.
3. 17 The timing for significant qistortion
error detection is shown in Figure 4. A
noise pulse occurring while the signal line input
is idle causes the MSFF and SMFF to be reset.
Both outputs are high at time Tl, but since no
clock pulse is developed the DOFF is not reset.
Additional noise pulses cause the two flip-flops
to toggle back and forth.
If
the last noise pulse
(time T2) leaves them both reset, the mark-to-
space transition occt1rring when the true start
bit arrives sets the MSFF, so the DOFF is no
longer primed whe·n the first clock pulse is
developed. Consequently, the SA110 will not
indicate an error for idle line noise.
3. 18 When undistorted or slightly distorted
data bits appear at the input, the MSFF
is reset on each mark-to-space transition (time
T3) and set on the following clock pulse, and the
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