General Description; Principles Of Operation - Teletype SA110 Description And Operation

SECTION 578-200-100
1. 17 The de current loop output is a switched
transistor stage capable of providing a
current/no-current signal. The maximum volt-
age which may be applied is -48 volts de. Max-
imum current switched (limited externally) is 60
ma.
1. 18 Two outputs are available to drive error
display devices. One is a polar signal
conformingto EIA StandardRS-232B. Thisout-
put is normally negative ( -14 volts) and goes
positive (+14 volts) when a parity error is de-
tected. The second output is a set of Form C
(transfer) relay contacts. Provision has been
made to connect the common terminal of the
contacts to +14 or -14 volts, either directly or
through a current-limiting resistor. Power
applied to these contacts should be limited to 48
volts and 200 ma.
2. GENERAL DESCRIPTION
2. 01 The parity detector contains two circuit
cards and a power supply. It is com-
pletely self-contained except for an optional by-
pass switch or indicator assembly. These
operational assemblies are described in Part 4,
VARIABLE FEATURES.
2. 02 Both SAll0 circuit cards use integrated
circuits as well as discrete components.
They consist of a regenerator and parity detect
logic card (TP322402-404) and an interface am-
plifier and break generator circuitry card
(TP322405). Card TP322402 is used in parity
detectors operating at 110 baud, card TP322403
in those operating at 150 baud, and card TP322404
in those operating at 1050 baud. The only dif-
ference between these cards is in the bit timer
crystal and two associated capacitors_.
2. 03 The regenerator and parity detect logic
card has strap options for 10- or 11-unit
code operation, even or odd parity check, and
enabling or disabling the significant distortion
check. The interface amplifiers and break gen-
erator circuitry card has strap options for oper-
ation with 60 ma de input, with 20 ma de input or
lOlC or 105A data sets, or with EIA input; op-
eration with 20 ma or 60 ma output (current must
be limited externally) or with EIA or simulated
lOlC and 105A data set output; various operate
time and inhibit combinations for the output
pulse; energizing a relay during the output pulse
or replacing it with a resistive load; relay oper-
ation on every error detected; relay latch on
first error and drop-out and pick-up on follow-
ing errors, or permanent relay latch on first
error; and +14 volts or -14 volts output at relay
contacts.
Page 6
3. PRINCIPLES OF OPERATION
3. 01 Schematic wiring diagram 8538WD (fur-
nished with the SAll0) is useful for under-
standing the following discussion. Actual wiring
information is contained on 8539WD (actual wir-
ing diagram for the SAll0), 322402-404 (regen-
erators and parity detect logic card drawing),
and 322405 (interface amplifiers and break gen-
erator circuitry card drawing).
3. 02 A simplified block diagram of the SAll0
parity detector logic is shown in Fig-
ure 3. The explanation of error detection opera-
tion which follows is based on this diagram. A
complete circuit description is included in
8538WD. Refer to sheet CDlO for a logic flow
chart for the SAll0.
3. 03 Input data from the signal line or channel
is amplified by the input amplifier Q12-
Ql3, MC405, and converted to levels compatible
with the parity detection logic ( +6 volts for mark,
0 volt for space). This amplifier accepts a 60
ma current/no-current signal with straps K and
L closed, a 20 ma current/no-current signal or
the output of l0lC and 105A data sets with strap
K open and L closed (factory wiring), and an
EIA signal with strap K open and L open. The
de inputs must be applied between terminals 1
and 2 or 1 and 4, and the EIA input must be ap-
plied between terminals 3 and 2 or 3 and 4. The
output of this amplifier is applied to the input
gating and the clock pulse input of the mark-
space flip-flop (MSFF), both on MC402-404.
3. 04 The input gating consists of inverter
MLC3-10 and NAND gates MLD4-3 and
MLD3-6. The output of MLC3-10
is used to
prime the data flip-flop (DFF) and to provide the
clock pulse for the space-mark flip-flop (SMFF).
A second prime for the DFF is obtained from
MLD4-3. The output of MLD3-6 is used to re-
lease and inhibit the bit timer counter flip-flops
so that no clock pulse is developed if the spacing
start pulse is less than 0. 5 bit in duration.
3. 05 The bit timer consists of a free-running
crystal oscillator and seven binary flip-
flops. The oscillator operates at 128 times the
incoming bit rate and the seven flip-flops form
a counter which divides its frequency down to the
bit rate. Inhibiting these flip-flops controls the
bit timer. The outputs of four of the flip-flops
are used to regenerate
the stop pulse, and the
output of the final flip-flop is used to develop the
clock pulse.