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MiTAC TYAN S8040 Instructions Manual

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S8040
Version 1.0a
Copyright
Copyright © 2024 MiTAC International Corporation. All rights reserved. No part of
this manual may be reproduced or translated without prior written consent from
MiTAC International Corporation.
Trademark
All registered and unregistered trademarks and company names contained in this
manual are property of their respective owners including, but not limited to the
following.
®
TYAN
is a trademark of MiTAC International Corporation.
®
®
AMD
is a trademark of AMD
Corporation.
AMI, AMI BIOS are trademarks of AMI Technologies.
Microsoft
®
, Windows
®
are trademarks of Microsoft Corporation.
®
Winbond
is a trademark of Winbond Electronics Corporation.
Notice
Information contained in this document is furnished by MiTAC International
Corporation and has been reviewed for accuracy and reliability prior to printing.
MiTAC assumes no liability whatsoever, and disclaims any express or implied
®
warranty, relating to sale and/or use of TYAN
products including liability or
warranties relating to fitness for a particular purpose or merchantability. MiTAC
retains the right to make changes to product descriptions and/or specifications at
any time, without notice. In no event will MiTAC be held liable for any direct or
indirect, incidental or consequential damage, loss of use, loss of data or other
malady resulting from errors or inaccuracies of information contained in this
document.
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Summary of Contents for MiTAC TYAN S8040

  • Page 1 In no event will MiTAC be held liable for any direct or indirect, incidental or consequential damage, loss of use, loss of data or other malady resulting from errors or inaccuracies of information contained in this document.
  • Page 2 http://www.tyan.com...

  • Page 3: Table Of Contents

    Contents Before you begin… ..................4   Chapter 1: Instruction ................5   1.1 Congratulations ................. 5   1.2 Hardware Specifications ..............5   1.3 Software Specifications ..............8   Chapter 2: Board Installation ..............9   2.1 Board Image ..................10  ...

  • Page 4: Before You Begin

    Before you begin… Check the box contents! The retail motherboard package should contain the following: S8040 Motherboard x 1 SATA Cable x 2 M.2 Latch x 2 Rear IO shielding x 1 S8040 Quick Installation Guide x 1 IMPORTANT NOTE: Sales samples may not come with any of the accessories listed above.

  • Page 5: Chapter 1: Instruction

    Chapter 1: Instruction 1.1 Congratulations ® You have purchased the powerful TYAN S8040 motherboard, based on the Aspeed ® AST2600 chipset. The S8040 is designed to support AMD EPYC™ 8004 Series Processor, and up to 768GB RDIMM DDR5 4800/3600 memory. Leveraging ®...
  • Page 6 Resolution Up to 1920x1200 Chipset Aspeed AST2600 NVMe (2) MCIO x4 / (2) MCIO x8 (1) USB3.2 Gen.1 header / (1) USB3.2 Gen.1 conn. ( Type-A ) / (2) USB3.2 Gen.1 ports (@rear) (1) COM port header / (1) DB-9 COM Connector (1) VGA port Input /Output RJ-45...
  • Page 7 Motherboard (1) S8040 Motherboard Package Manual (1) Quick Installation Guide Contains Cable SATA (2) SATA signal cables S8040GM4NE-2T Specifications Q'ty / Socket Type (1) AMD Socket SP6 Supported CPU (1) AMD EPYC™ 8004 Series Processor Processor Series Thermal Design Max up to 225W (TDP) Power Wattage Supported DIMM Qty (8) DIMM slots DIMM Type / Speed...

  • Page 8: Software Specifications

    Chipset Aspeed AST2600 Total (5) 4-pin headers Temperature Monitors temperature for CPU, memory & system System environment Monitoring Voltage Monitors voltage for CPU, memory, chipset & power supply Fan fail LED indicator / Over temperature warning indicator / Fan & PSU fail LED indicator Onboard Chipset Onboard Aspeed AST2600 AST2600 iKVM...

  • Page 9: Chapter 2: Board Installation

    Unplug the power from your computer power supply and then touch a safely grounded object to release static charge (i.e. power supply case). For the safest conditions, MiTAC recommends wearing a static safety wrist strap. (2) Hold the motherboard by its edges and do not touch the bottom of the board, or flex the board in any way.

  • Page 10: Board Image

    2.1 Board Image S8040 This picture is representative of the latest board revision available at the time of publishing. The board you receive may not look exactly like the above picture. http://www.tyan.com...

  • Page 11: Block Diagram

    2.2 Block Diagram S8040GM2NE-2T Block Diagram http://www.tyan.com...
  • Page 12 S8040GM2NE Block Diagram http://www.tyan.com...

  • Page 13: Motherboard Mechanical Drawing

    2.3 Motherboard Mechanical Drawing http://www.tyan.com...

  • Page 14: Board Parts, Jumpers And Connectors

    2.4 Board Parts, Jumpers and Connectors This diagram is representative of the latest board revision available at the time of publishing. The board you receive may not look exactly like the above diagram. The DIMM slot numbers shown above can be used as a reference when reviewing the DIMM population guidelines shown later in the manual.
  • Page 15 Jumpers & Connectors Connectors 1. Front Fan Header (FAN_HD1) 24. SATA Connector (J19) 2. Front VGA Header (VGA1) 25. ID Button (IDLED_BTN) 3. COM Port Header (COM2) 26. Intrusion Header (J66) 4. ESPI Port 80 Header (J62) 27. SATA Connector (J15) 28.
  • Page 16 III HDD ACT LED (D39) IX P0_RESET LED (D58) IV ATX_PSU_PWROK LED (D33) X PSU_ALERT LED (D31) V BMC_SYS_FAULT LED (D2) XI SYS_PWROK LED (D4) VI BMC_HW_FAULT LED (D18) Jumper Legend OPEN - Jumper OFF Without jumper cover CLOSED - Jumper ON With jumper cover http://www.tyan.com...
  • Page 17 CPU0_FAN, SYS_FAN_1~5: 4-pin FAN Connector Signal P12V FAN_TACH FAN_PWM Use this header to connect the cooling fan to your motherboard to keep the system stable and reliable. FPIO_2: Front Panel Connector Signal Signal FP_PW_LED_PW VCC_FPB FP_ID_LED_PW FP_PWR_LED_GND FP_ID_LED_N HDD_LED_PW BMC_HW_FAULT_N HDD_ACT_LED_N BMC_SYS_FAULT_N FP_PWR_BTN_N...
  • Page 18 J62: ESPI Port 80 Header Signal Signal VDD_33_DUAL ESPI_CS1 RESET# ALERT FAN_HD1: Front Fan Connector (Reserved for Barebone) Signal Signal TACH1 TACH6 TACH2 TACH7 TACH3 TACH8 TACH4 TACH9 TACH5 TACH10 PWM3 PWM2 TACH11 TACH12 PWM4 TACH13 TACH15 TACH14 TACH16 PWM5 PWM7 PWM0 J5: Front USB 3.0&2.0 Connector...
  • Page 19 SGPIO0: SGPIO Header Signal Signal SGPIO0_CLK SGPIO0_DATA SATA_SGPIO_DATA_OUT SATA_SGPIO_LOAD P_CONN_SGPIO_CLK1 VDD_33_DUAL VGA1: Front Panel VGA Header Signal Signal HD_VGA_R HD_VGA_G HD_VGA_B HD_VGA_DAT HD_VGA_HS HD_VGA_CLK HD_VGA_VS COM2: COM Port Header Signal Signal COM2_DCD COM2_DSR COM2_RXD COM2_RTS COM2_TXD COM2_CTS COM2_DTR COM2_NRI (HDR_1/3/5): HDD BP Smbus Header Signal Signal VCC3_AUX...
  • Page 20 IDLED_BTN1: Rear IO ID LED Button Signal Signal FP_IDLED_BTN_N System Power Button Signal Signal PWR_BTN1 Reset Button Signal Signal FP_RST_BTN_N J66: Intrusion Header Signal SCM_CHASSIS_INTR_L J12: CPLD JTAG Connector (reserved) Signal Signal VDD_33_DUAL http://www.tyan.com...
  • Page 21 CN10/11: MCIOx4 NVME Connector Signal Name Pin Pin Signal Name B1 GND XGMI_G3_C_MCIOX8_RX_H<0> B2 XGMI_G3_TX_C_H<0> XGMI_G3_C_MCIOX8_RX_L<0> B3 XGMI_G3_TX_C_L<0> B4 GND XGMI_G3_C_MCIOX8_RX_H<1> B5 XGMI_G3_TX_C_H<1> XGMI_G3_C_MCIOX8_RX_L<1> B6 XGMI_G3_TX_C_L<1> B7 GND SLIMSAS_BP_TYPE5 B8 NVME_SMB_SCL5_R SGPIO_DATA5_PCIE_WAKE_L B9 NVME_SMB_SDA5_R A10 B10 GND CLK_100M_NVME0_DH A11 B11 NVME_PERST5 CLK_100M_NVME0_DL A12 B12 NVME5_PRSNT_L A13 B13 GND...
  • Page 22 CN3/4: MCIOx8 NVME Connector Signal Name Pin Pin Signal Name A1 B1 GND PCIE_P0_RX_H_R<0> A2 B2 PCIE_P0_TX_C_H<0> PCIE_P0_RX_L_R<0> A3 B3 PCIE_P0_TX_C_L<0> A4 B4 GND PCIE_P0_RX_H_R<1> A5 B5 PCIE_P0_TX_C_H<1> PCIE_P0_RX_L_R<1> A6 B6 PCIE_P0_TX_C_L<1> A7 B7 GND PE4_TYPEA A8 B8 CPU0_PE4_HDD0_SCL0 SGPIO_DATA1_PCIE_WAKE_L A9 B9 CPU0_PE4_HDD0_SDA0 A10 B10 GND CLK_100M_DB2000_CPU0_NVME1_DP A11 B11 RST_NVME0_CPU0_PERST_N...
  • Page 23 CN1/CN2: M.2 Connector Signal Signal VCC3 VCC3 VCC3_AUX M2_LED_N VCC3 VCC3 VCC3 VCC3 PCH_PE1_M2_1_RX_N PCH_PE1_M2_1_RX_P PCH_PE1_M2_1_TX_N PCH_PE1_M2_1_TX_P M2_SMB_CLK_R PCH_PE0_M2_0_RX_N M2_SMB_DAT_R PCH_PE0_M2_0_RX_P PCH_PE0_M2_0_TX_N M2_PERST_N_R PCH_PE0_M2_0_TX_P M2_2_PEWAKE_N CLK_100M_M2_DN CLK_100M_M2_DP PE_M.2_DETECT_N VCC3 VCC3 VCC3 http://www.tyan.com...
  • Page 24 J15/J16/J19: 7-pin SATA 3.0 Connector Name TYPE G3_SATA_TX_DP0 G3_SATA_TX_DN0 G3_SATA_RX_DN0 G3_SATA_RX_DP0 PIN MT1 PIN MT2 J18: SATA DOM Connector Name TYPE G3_SATA_TX_DP2 G3_SATA_TX_DN2 G3_SATA_RX_DN2 G3_SATA_RX_DP2 PIN MT1 PIN MT2 P5V_SATADOM Connects to the Serial ATA ready drives via the Serial ATA cable. J56: SPI TPM Header Signal Signal...
  • Page 25 J4: NCSI Connector (for OEM use) Signal Signal NCSI_HEADER_ NCSI_HEADER_BMC BMC_MAC3_TXD1 _MAC3_CRSDV NCSI_HEADER_ NCSI_HEADER_ BMC_MAC3_TXD0 MAC1_CLKIN50M NCSI_HEADER_ NCSI_HEADER_ BMC_MAC3_RXD0 BMC_MAC3_TXEN NCSI_HEADER_ RMII_HEADER_RX_B_ER BMC_MAC3_RXD1 J75: Clear CMOS Jumper Signal Signal VDD_RTC P0_VDD_RTC (Default) Pin1-2 closed: Normal Mode Pin2-3 closed: Clear CMOS J6/J7: BMC Debug Jumper Signal Signal...

  • Page 26: Led Definitions

    2.5 LED Definitions Signal REAR_ID_LED_L i. D77 ID LED State Description Blue Signal LED_BMC_HB_LED_D_N BMC_HB_LED_L BMC heartbeat ii.D1_BMC State Description BMC not ready Green BMC READY Signal HDD_ACT_LED_ALL_L iii. D39 HDD ACT LED State Description Blue HDD ACT Active http://www.tyan.com...
  • Page 27 Signal LED_A_P12V_ON LED_C_P12V_HSC_ON ATX_PSU_PWRO iv. D33 K LED State Description Green ATX_PSU_POWER OK Signal BMC_SYS_FAULT_L BMC_SYS_FAULT v. D2 State Description Orange BMC_SYS OK Signal BMC_HW_FAULT_L BMC_HW_FAULT vi. D18 State Description Orange BMC_HW OK Signal P0_PWR_GOOD_LED P0_PWR_GOOD vii. D52 State Description POWER OFF Green POWER ON...
  • Page 28 Signal SCM_SYS_PWROK State Description xi. D4 SYS_PWROK LED System power status is normal. System power status is Orange abnormal. http://www.tyan.com...

  • Page 29: Installing The Processor And Heatsink

    AMD ® processors for this specific motherboard. NOTE: MiTAC is not liable for damage as a result of operating an unsupported configuration. ® Processor Installation (Single Socket / for AMD EPYC™ 8004 Series CPU) Follow the steps below to install the processors and heat sinks.
  • Page 30 Remove the external cap from the rail frame. Align and install the carrier frame with package into the slot on the rail frame. NOTE: During installation, observe the following: make sure to push the carrier frame with package towards the end of the rail frame until it clicks in place.
  • Page 31 Carefully close the rail frame with the installed package. Then push both edges of the rail frame firmly until it locks in place. Heat sink Installation After installing the processor, you will need to proceed to install the heat sink. The CPU heat sink will ensure that the processor do not overheat and continue to operate at maximum performance for as long as you own them.
  • Page 32 Use a T30 Torx screwdriver to tighten the heatsink screws. Connect the heatsink power cable to the mainboard connector. http://www.tyan.com...

  • Page 33: Thermal Interface Material

    2.7 Thermal Interface Material There are two types of thermal interface materials designed for use with the processors. The most common material comes as a small pad attached to the heat sink at the time of purchase. There should be a protective cover over the material.

  • Page 34: Tips On Installing Motherboard In Chassis

    2.8 Tips on Installing Motherboard in Chassis Before installing your motherboard, make sure your chassis has the necessary motherboard support studs installed. These studs are usually metal and are gold in color. Usually, the chassis manufacturer will pre-install the support studs. If you are unsure of stud placement, simply lay the motherboard inside the chassis and align the screw holes of the motherboard to the studs inside the case.
  • Page 35 Some chassis include plastic studs instead of metal. Although the plastic studs are usable, MiTAC recommends using metal studs with screws that will fasten the motherboard more securely in place. Below is a chart detailing what the most common motherboard studs look like and how they should be installed.

  • Page 36: Installing The Memory

    2.9 Installing the Memory Before installing memory, ensure that the memory you have is compatible with the motherboard and processor. Check the TYAN Web site at http://www.tyan.com details of the type of memory recommended for your motherboard. http://www.tyan.com...
  • Page 37 DIMM Population/Channel DDR5 Frequency MT/s Siena platforms DIMM Type DIMM 0 DIMM 1 14L 77mil PCB stackup 4800 4000 RDIMM 4800 3600 Recommended Memory Population Table Quantity of memory installed CPU Installed P0_CHA_DIM1 √ √ √ √ √ P0_CHB_DIM1 √ √...
  • Page 38 Memory Installation Procedure Follow these instructions to install memory modules into the S8040. Unlock a DIMM socket by Press the retaining clip outwardly in the following illustration. Align the memory module with the socket，such that the DIMM NOTCH match the KEY SLOT on the socket. Seat the module firmly into the socket by gently pressing down until it sits flush with the socket.

  • Page 39: Installing Add-In Cards

    2.10 Installing Add-In Cards Before installing add-in cards, it’s helpful to know if they are fully compatible with your motherboard. For this reason, we’ve provided the diagrams below, showing the slots that may appear on your motherboard. PCI-E Gen5 x16 slot Simply find the appropriate slot for your add-in card and insert the card firmly.

  • Page 40: Connecting External Devices

    2.11 Connecting External Devices Connecting external devices to the motherboard is an easy task. The motherboard supports a number of different interfaces through connecting peripherals. See the following diagrams for the details. S8040GM4NE-2T S8040GM2NE NOTE: 1. For S8040GM4NE-2T Sku: RJ45 (10GbE) LAN1/LAN2 is from Intel X710 chipset. RJ45 (1GbE) LAN3/LAN4 are from Intel I210 chipset.

  • Page 41: Installing The Power Supply

    Onboard LAN LED Color Definition Five (5) onboard Ethernet ports have green and Amber LEDs to indicate LAN status. The chart below illustrates the different LED states. 10Mbps/100Mbps/1Gbps/10Gbps LAN Link/Activity LED Scheme Left LED Right LED No Link Link Green 10Mbps Active Blinking Green...
  • Page 42 PWR2: 8-PIN Power Connector Signal Signal P12V1 P12V1 P12V1 P12V1 PWR3: 8-PIN Power Connector Signal Signal P12V1 P12V1 P12V1 P12V1 NOTE: You must unplug the power supply before plugging the power cables to motherboard connectors. http://www.tyan.com...

  • Page 43: Finishing Up

    2.13 Finishing Up Congratulations on making it this far! You have finished setting up the hardware aspect of your computer. Before closing up your chassis, make sure that all cables and wires are connected properly, especially SATA cables and most importantly, jumpers.

  • Page 44: Chapter 3: Bios Setup

    Chapter 3: BIOS Setup 3.1 About the BIOS The BIOS is the basic input/output system, the firmware on the motherboard that enables your hardware to interface with your software. The BIOS determines what a computer can do without accessing programs from a disk. The BIOS contains all the code required to control the keyboard, display screen, disk drives, serial communications, and a number of miscellaneous functions.
  • Page 45 Chipset section unless you are absolutely sure of what you are doing. The Chipset defaults have been carefully chosen either by MiTAC or your system manufacturer for best performance and reliability. Even a seemingly small change to the Chipset setup options may cause the system to become unstable or unusable.

  • Page 46: Main Menu

    3.2 Main Menu In this section, you can alter general features such as the date and time. Note that the options listed below are for options that can directly be changed within the Main Setup screen. BIOS Information It displays BIOS related information. Product Name It displays Product information.
  • Page 47 System Date Set the Date. Use Tab to switch between Date elements. Default Ranges: Year: 2005-2099 Months: 1-12 Days: dependent on month System Time Adjust the system clock. HH (24 hours format): MM (Minutes): SS (Seconds) Access Level Administrator http://www.tyan.com...

  • Page 48: Advanced Menu

    3.3 Advanced Menu This section facilitates configuring advanced BIOS options for your system. NOTE: This is a sample screenshot of the Advanced Menu. The HII network drivers displayed here depend on the card(s) you installed and the functions you enabled. Network Stack Configuration Network Stack Settings S5 RTC Wake Settings...
  • Page 49 Onboard Device Configuration Onboard Device and Function Configuration. Super IO Configuration System Super IO Chip Parameters. Hardware Health Configuration Hardware Health Configuration PCI Subsystem Settings PCI, PCI-X and PCI Express Settings CSM Configuration CSM Configuration, Enable/Disable Option ROM execution setting, etc NVMe Configuration NVMe Device Information Trusted Computing...
  • Page 50 MAC: A0423F512A4F-IPv6 Network Configuration Configure network parameters (MAC: A0423F512A4F) http://www.tyan.com...
  • Page 51 3.3.1 Network Stack Configuration Network Stack Enable/Disable UEFI Network Stack Disabled / Enabled NOTE: When Network Stack was set to Enabled, the following item will appear. IPv4 PXE Support Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available.
  • Page 52 IPv6 HTTPs Support Enable/Disable IPv6 HTTPs boot support. If disabled, IPv6 HTTPS boot support will not be available. Disabled / Enabled PXE boot wait time Wait time in seconds to press ESC key to abort the PXE boot. Use either +/- or numeric keys to set the value.
  • Page 53 3.3.2 S5 RTC Wake Settings Wake system from S5 Enable or disable system wake on alarm event. Select Fixed time, system will wake on the hr::min::sec specified. Select dynamic time, system will wake on the current time+ increase minute(s) Disabled / Fixed Time / Dynamic Time http://www.tyan.com...
  • Page 54 3.3.3 Serial Port Console Redirection COM1/COM2 Console Redirection Console redirection enable or disable. Disabled / Enabled Legacy Console Redirection Legacy Console Redirection Settings Serial Port for Out-Of-Band Management/Windows Emergency Services (EMS) Console Redirection Console redirection enable or disable. Disabled / Enabled Console Redirection Settings The settings specify how the host computer (which the user is using) will exchange data.
  • Page 55 3.3.3.1 COM1 Console Redirection Settings Terminal Type Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. VT-UTF8 / VT100 / VT100+ / ANSI Bits per Second Select serial port transmission speed.
  • Page 56 Stop Bits Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit. 1 / 2 Flow Control Flow Control can prevent data loss from buffer overflow.
  • Page 57 3.3.3.2 COM2 Console Redirection Settings Terminal Type Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes. VT-UTF8 / VT100 / VT100+ / ANSI Bits per Second Select serial port transmission speed.
  • Page 58 Stop Bits Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit. 1 / 2 Flow Control Flow Control can prevent data loss from buffer overflow.
  • Page 59 3.3.3.3 Legacy Console Redirection Settings Redirection COM Port Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages COM1 / COM2 Resolution On Legacy OS, the Number of Rows and Columns supported redirection 80x24 / 80x25 Redirect After POST when Bootloader is selected, then Legacy Console Redirection is disabled before booting to legacy OS, when Always Enable is selected, then Legacy Console...
  • Page 60 3.3.3.4 Serial Port for Out-Of-Band Management/Windows Emergency Services (EMS) Console Redirection Settings Out-of Band Mgmt Port Microsoft Windows Emergency Management Services (EMS) allows for remote management of a Windows Server OS through a serial port. COM1 / COM2 Terminal Type VT-UTF8 is the preferred terminal type for out-of-band management.
  • Page 61 Flow Control Flow Control can prevent data loss from buffer overflow. When sending data, if the receiving buffers are full, a ‘stop’ signal can be sent to stop the data flow. Once the buffers are empty, a ‘start’ signal can be sent to restart the flow. Hardware flow control uses two wires to send start/stop signal.
  • Page 62 3.3.4 PCIe Device Configuration Option ROM Dispatch Policy Option ROM Dispatch Policy settings. PCIe Slot Bifurcation PCIe Slot Bifurcation settings. PCIe Slot Speed PCIe Slot Speed settings. http://www.tyan.com...
  • Page 63 3.3.4.1 Option ROM Dispatch Policy LAN1 (X710) Option ROM Enable or Disable LAN1 Option ROM Enabled / Disabled LAN2 (X710) Option ROM Enable or Disable LAN2 Option ROM Enabled / Disabled LAN3 (I210-1) Option ROM Enable or Disable LAN3 Option ROM Enabled / Disabled LAN4 (I210-2) Option ROM Enable or Disable LAN4 Option ROM...
  • Page 64 Enabled / Disabled PCIE#3 Option ROM Enable or Disable Option ROM execution for selected Slot. Enabled / Disabled PCIE#4 Option ROM Enable or Disable Option ROM execution for selected Slot. Enabled / Disabled MCIO0/MCIO1 Option ROM Enable or Disable Option ROM execution for selected Slot. Enabled / Disabled MCIO2/MCIO3 Option ROM Enable or Disable Option ROM execution for selected Slot.
  • Page 65 3.3.4.2 PCIe Slot Bifurcation PCIE#1 Bifurcation Selects PCIE port Bifurcation for PCIE#1 slots. X16 / x8x8 / x4x4x4x4 PCIE#2 Bifurcation Selects PCIE port Bifurcation for PCIE#2 slot. X16 / x8x8 / x4x4x4x4 PCIE#3 Bifurcation Selects PCIE port Bifurcation for PCIE#3 slot. X16 / x8x8 / x4x4x4x4 PCIE#4 Bifurcation Selects PCIE port Bifurcation for PCIE#4 slot.
  • Page 66 MCIO2/MCIO3 Bifurcation Selects PCIE port Bifurcation MCIO CN2/3 slot. X8 / x4x4 http://www.tyan.com...
  • Page 67 3.3.4.3 PCIe Slot Speed PCIE#1 Speed Maximum Link Speed for PCIE#1 slot. Auto / GEN1(2.5 GT/s) / GEN2(5 GT/s) / GEN3(8 GT/s) / GEN4(16 GT/s) / GEN5 (32GT/s) PCIE#2 Speed Maximum Link Speed for PCIE#2 slot. Auto / GEN1(2.5 GT/s) / GEN2(5 GT/s) / GEN3(8 GT/s) / GEN4(16 GT/s) / GEN5 (32GT/s) PCIE#3 Speed Maximum Link Speed for PCIE#3 slot.
  • Page 68 MCIO0/1 Speed Maximum Link Speed for MCIO CN0/1 slot. Auto / GEN1(2.5 GT/s) / GEN2(5 GT/s) / GEN3(8 GT/s) / GEN4(16 GT/s) / GEN5 (32GT/s) MCIO2/3 Speed Maximum Link Speed for MCIO CN2/3 slot. Auto / GEN1(2.5 GT/s) / GEN2(5 GT/s) / GEN3(8 GT/s) / GEN4(16 GT/s) / GEN5 (32GT/s) http://www.tyan.com...
  • Page 69 3.3.5 USB Configuration Legacy USB Support Enables USB legacy support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Enabled / Disabled / Auto XHCI Hand-off This is a workaround for OSes without XHCI hand-off support. The XHCI ownership change should be claimed by XHCI driver.
  • Page 70 USB transfer time-out The time-out value for Control, Bulk and Interrupt transfers. 1 sec / 5 sec / 10 sec / 20 sec Device reset time-out USB mass storage device Start Unit command time-out. 10 sec / 20 sec / 30 sec / 40 sec Device power-up delay Maximum time the device will take before it properly reports itself to the Host Controller.
  • Page 71 3.3.6 Onboard Device Configuration Onboard VGA Enable/Disable ASPEED VGA Disabled / Enabled LAN1/LAN2 (X710) LAN Enable/Disable control function. Disabled / Enabled LAN3 (I210-1) LAN Enable/Disable control function. Disabled / Enabled LAN4 (I210-2) LAN Enable/Disable control function. Disabled / Enabled Primary Display Select active Video type.
  • Page 72 NMI Button Enable or disable NMI button. Disabled / Enabled Chassis Intrusion Detention Enabled: When a chassis open event is detected, the BIOS will display the event. Disabled / Enabled Clock Spread Spectrum Enable/Disable Clock Spread Spectrum Disabled / Enabled http://www.tyan.com...
  • Page 73 3.3.7 Super IO Configuration Serial Port 1 Configuration Set Parameters of serial Port 1 (COMA) Serial Port 1 Configuration Set Parameters of serial Port 2 (COMB) http://www.tyan.com...
  • Page 74 3.3.7.1 Serial Port 1 Configuration Serial Port Enable or Disable Serial Port (COM). Disabled / Enabled NOTE: Serial Port has set to Enabled, the following items will be appear. Change Settings Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.
  • Page 75 3.3.7.2 Serial Port 2 Configuration Serial Port Enable or Disable Serial Port (COM). Disabled / Enabled NOTE: Serial Port has set to Enabled, the following items will be appear. Change Settings Allows the user to change the device resource settings. New settings will be reflected on this setup page after system restarts.
  • Page 76 3.3.8 Hardware Health Configuration Fan Speed Control Fan Speed Control help. Manual / Full Speed NOTE: When Auto Fan Control was set to [Manual] PWM Minimal Duty Cycle Item will appear. PWM Minimal Duty Cycle PWM Minimal Duty Cycle BMC Alert Beep Enable/Disable BMC Alert Beep.
  • Page 77 Number of PSU User can select PSU number for needed 1 / 2 3.3.8.1 Sensor Data Register Monitoring When you enter the Sensor Data Register Monitoring submenu, you will see the following dialog window pop out. Please wait 8~10 seconds. NOTE 1: SDR can not be modified.
  • Page 78 http://www.tyan.com...
  • Page 79 3.3.9 PCI Subsystem Settings Above 4G Decoding Enables or Disables 64bit capable Devices to be decoded in Above 4G Address Space(Only if System supports 64 bit PCI Decoding). Enabled / Disabled SR-IOV Support If system has SR-IOV capable PCIe devices, this option Enables or Disables Single Root IO virtualization Support.
  • Page 80 3.3.9.1 PCI Express Subsystem Maximum Payload Set Maximum Payload of PCI Express Device or allow System BIOS to select the value. Auto / 128 Bytes / 256 Bytes / 512 Bytes / 1024 Bytes / 2048 Bytes / 4096 Bytes http://www.tyan.com...
  • Page 81 3.3.10 CSM Configuration CSM support Enable/Disable CSM Support Enabled / Disabled NOTE: When CSM support was set to Enabled, the following items will appear. Option ROM Messages Set display mode for Option ROM Force BIOS / Keep Current Network Controls the execution of UEFI and legacy Network OpROM UEFI / legacy Storage Controls the execution of UEFI and legacy Storage OpROM...
  • Page 82 3.3.11 NVMe Configuration http://www.tyan.com...
  • Page 83 3.3.12 Trusted Computing Security Device Support Enables or disables BIOS support for security device. O.S. will not show Security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. Enabled / Disabled http://www.tyan.com...
  • Page 84 3.3.13 Redfish Host Interface Settings Redfish Enable/Disable AMI Redfish. Disabled / Enabled http://www.tyan.com...
  • Page 85 3.3.14 Tls Auth Configuration Server CA Configuration Press <Enter> to configure Server CA. http://www.tyan.com...
  • Page 86 3.3.14.1 Tls Auth Configuration Enroll Cert Press <Enter> to enroll cert. Delete Cert Press <Enter> to delete cert. http://www.tyan.com...
  • Page 87 3.3.14.1.1 Enroll Cert Configuration Enroll Cert Using File Enroll Cert Using File Cert GUID Input digit character in 11111111-2222-3333-4444-1234567890ab format. Commit Changes and Exit Commit Changes and Exit Discard Changes and Exit Discard Changes and Exit http://www.tyan.com...
  • Page 88 3.3.14.1.2 Delete Cert Configuration FEXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXX GUID for CERT Disabled / Enabled http://www.tyan.com...
  • Page 89 3.3.15 ISCSI Initiator Configuration Host iSCSI Configuration Host iSCSI Configuration settings http://www.tyan.com...
  • Page 90 3.3.15.1 Host iSCSI Configuration Please follow the instructions to initiate the iSCSI function. Step 1. Select Advanced  CSM Configuration  Network  [UEFI]. Step 2. Select Advanced  Network Stack Configuration  Network Stack  [Enabled] Step 3. Save changes and reboot. iSCSI Initiator Name The worldwide unique name of iSCSI Initiator.
  • Page 91 3.3.15.2 Add an Attempt Read only. http://www.tyan.com...
  • Page 92 3.3.15.2.1 MAC 36:02:0B:83:D7:63 iSCSI Mode Disabled, Enabled, Enabled for MPIO. Disabled / Enabled / Enabled for MPIO Internet Protocol Initiator IP address is system assigned in IP6 mode. In Autoconfigure mode, iSCSI driver will attempt to connect iSCSI target via IPv4 stack, if failed then attempt IPv6 stack.
  • Page 93 Configure ISID OUI-format ISID in 6 bytes, default value is derived from MAC address. Only last 3 bytes are configurable. Example: update 0ABBCCDDEEFF to OABBCCF07901 by input F07901. Enable DHCP Enable DHCP. Disabled / Enabled Initiator IP Address Enter IP address in dotted-decimal notation. Initiator Subnet Mask Enter IP address in dotted-decimal notation.
  • Page 94 3.3.15.2.2 MAC A0:42:3F:37:EA:08 iSCSI Mode Disabled, Enabled, Enabled for MPIO. Disabled / Enabled / Enabled for MPIO Internet Protocol Initiator IP address is system assigned in IP6 mode. In Autoconfigure mode, iSCSI driver will attempt to connect iSCSI target via IPv4 stack, if failed then attempt IPv6 stack.
  • Page 95 Configure ISID OUI-format ISID in 6 bytes, default value is derived from MAC address. Only last 3 bytes are configurable. Example: update 0ABBCCDDEEFF to OABBCCF07901 by input F07901. Enable DHCP Enable DHCP. Disabled / Enabled Initiator IP Address Enter IP address in dotted-decimal notation. Initiator Subnet Mask Enter IP address in dotted-decimal notation.
  • Page 96 3.3.15.3 Delete Attempts Attempt 1 MAC: A0:42:3F:37:EA:08, PFA: Bus 97/ Dev 0 / Func 0, iSCSI mode: Enabled, IP version: IPv4. Disabled / Enabled Attempt 2 MAC: 36:02:0B:83:D7:63, PFA: Bus 35 / Dev 0 / Func 3, iSCSI mode: Disabled, IP version: IPv4.
  • Page 97 3.3.15.4 Change Attempt Order Change Attempt Order Change the order of Attempts using +/- keys. Use arrow keys to select the attempt then press +/- to move the attempt up/down in the attempt order list. Attempt 1 / Attempt 2 / Attempt 3 Commit Changes and Exit Commit Changes and Exit.
  • Page 98 3.3.16 VLAN Configuration Enter Configuration Menu Press ENTER to enter configuration menu for VLAN configuration. http://www.tyan.com...
  • Page 99 3.3.16.1 Enter Configuration VLAN ID VLAN ID of new VLAN or existing VLAN, valid value is 0~4094 Priority 802.1Q Priority, valid value is 0~7 Add VLAN Create a new VLAN or update existing VLAN Remove VLAN Remove selected VLANs http://www.tyan.com...
  • Page 100 3.3.17 MAC: AA488C504715-IPv4 Network Menu Configured Indicate whether network address configured successfully or not. Disabled / Enabled NOTE: When Configured was set to Enabled, the following items will be available to set up. Enable DHCP Indicate whether network address configured successfully or not. Disabled / Enabled Local IP Address Enter IP address in dotted-decimal notation.
  • Page 101 Save Changes and Exit Save Changes and Exit http://www.tyan.com...
  • Page 102 3.3.18 MAC: AA488C504715-IPv6 Network Menu Enter Configuration Menu Press ENTER to enter configuration menu for VLAN configuration. http://www.tyan.com...
  • Page 103 3.3.18.1 Enter Configuration Menu Interface ID The 64 bit alternative interface ID for the device. The string is colon separated. e.g. ff:dd:88:66:cc:1:2:3 DAD Transmit Count The number of consecutive Neighbor Solicitation message sent while performing Duplicate Address Detection on a tentative address. A value of zero indicates that duplicate address detection is not performed.
  • Page 104 3.3.19 Intel® I210 Gigabit Network Connection Menu Firmware Image Properties View device firmware version information. NIC Configuration Click to configure the network device port. iSCSI Configuration Configure general, initiator and target parameters for iSCSI boot. Device Level Configuration View and configuration global device level parameters. Blink LEDs Blink LEDs for a duration up to 15 seconds.
  • Page 105 3.3.19.1 Firmware Image Properties Menu http://www.tyan.com...
  • Page 106 3.3.19.2 NIC Configuration Legacy Boot Protocol Select a non-UEFI network boot protocol. None / PXE / iSCSI Primary / iSCSI Secondary Wake On LAN Enables power on of the system via LAN. Note that configuring Wake on LAN in the operating system does not change the value of this setting, but does override the behavior of Wake on LAN in OS controlled power states.
  • Page 107 3.3.19.3 iSCSI Configuration iSCSI General Parameters Configure general iSCSI parameters. iSCSI Initiator Parameters Configuration of iSCSI initiator parameters (e.g., IP Address, Subnet Mask). iSCSI First Target Parameters Enable connection and configure communication parameters for the iSCSI target. http://www.tyan.com...
  • Page 108 3.3.19.3.1 iSCSI General Configuration TCP/IP Parameters via DHCP This option is specific to IPv4. Controls the source of the initiator IP address, DHCP or static assignment. Disabled / Enabled ISCSI Parameters via DHCP Enables the acquisition of iSCSI target parameters from DHCP. Disabled / Enabled CHAP Authentication Enable the ability of the initiator to use CHAP authentication when connecting to the...
  • Page 109 IP Version Controls whether IPv4 or IPv6 network addressing will be used for iSCSI initiator and targets. Currently only IPv4 is supported. http://www.tyan.com...
  • Page 110 3.3.19.2 iSCSI Initiator Parameters Configuration iSCSI Name Specifies the initiator iSCSI Qualified Name(IQN). CHAP ID iSCSI initiator Challenge- Handshake Authentication Protocol (CHAP) ID. CHAP Secret iSCSI initiator Challenge-Handshake Authentication Protocol (CHAP) secret (password). http://www.tyan.com...
  • Page 111 3.3.19.3 iSCSI First Target Parameters Configuration IP Address Specifies the IP address of the iSCSI target. TCP Port Specifies the TCP Port number of iSCSI target. Boot LUN Specifies the iSCSI storage target boot Logical Unit Number(LUN). iSCSI Name Specifies the iSCSI Qualified Name (IQN) of the iSCSI storage target. http://www.tyan.com...
  • Page 112 3.3.19.4 Device Level Configuration Shared Memory Features Specify which physical functions are enabled. Disabled functions will not be exposed and their associated ports will be completely shut down. Enabled / Disabled Active Physical Functions Specify which physical functions are enabled. Disabled functions will not be exposed and their associated ports will be completely shut down.

  • Page 113: Cpu Configuration

    3.4 CPU Configuration CPU Configuration CPU Configuration Parameters http://www.tyan.com...
  • Page 114 3.4.1 CPU Configuration Submenu SVM Mode Enable/disable CPU Virtualization Enabled / Disabled SMEE Control secure memory encryption enable Enabling both SMEE and SME-Mk is not supported. Results in #GP Enabled / Disabled CPU0 Information View Information related to CPU 0 http://www.tyan.com...
  • Page 115 3.4.1.1 CPU0 Information http://www.tyan.com...

  • Page 116: Chipset Menu

    3.5 Chipset Menu PCIe Compliance Mode PCIe Link Compliance Mode Settings Enabled Disabled North Bridge North Bridge Parameters AMD CBS AMD CBS Setup Page AMD PBS AMD PBS Setup Page http://www.tyan.com...
  • Page 117 3.5.1 North Bridge Configuration North Bridge Configuration Memory Information Total Memory： xxxxx MB CPU 0 Information View Memory Information related to CPU 0 http://www.tyan.com...
  • Page 118 3.5.1.1 CPU 0 Information http://www.tyan.com...
  • Page 119 3.5.2 AMD CBS Menu CPU Common Options CPU Common Parameters DF Common Options DF Common Parameters UMC Common Options UMC Common Parameters NBIO Common Options NBIO Common Parameters FCH Common Options FCH Common Parameters Soc Miscellaneous Control Soc Miscellaneous Control parameters http://www.tyan.com...
  • Page 120 3.5.2.1 CPU Common Options Submenu CCD/Core/Thread Enablement CCD/Core/Thread Enablement settings Prefetcher settings Prefetcher parameters Platform First Error Handling Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts from each bank. Enabled / Disabled / Auto Core Performance Boost Disable CPB Disabled / Auto Global C-state Control Controls IO based C-state generation and DF C-states.
  • Page 121 SEV-ES ASID Space Limit SEV VMs using ASIDs below the SEV-ES ASID Space Limit must enable the SEV- ES feature. ASIDs from SEV-ES ASID Space Limit to (SEV ASID Count +1) can only be used with SEV VMs. If this field is set to (SEV ASID Count +1)， all ASIDs are forced to be SEV-ES ASIDs.
  • Page 122 3.5.2.1.1 CCD/Core/ Thread Enablement Submenu CCD Control Sets the number of CCDs to be used. Once this option has been used to remove any CCDs, a POWER CYCLE is required in order for future selections to take effect. Auto / 2 CCDs Core control Sets the number of Cores to be used.
  • Page 123 3.5.2.1.2 Prefetcher Submenu L1 Stream HW Prefetcher Option to Enable | Disable L1 Stream HW Prefetcher Disabled / Enabled / Auto L2 Stream HW Prefetcher Option to Enable | Disable L2 Stream HW Prefetcher Disabled / Enabled / Auto http://www.tyan.com...
  • Page 124 3.5.2.2 DF Common Options Submenu PSP error injection support Enable EINJ support False / True http://www.tyan.com...
  • Page 125 3.5.2.2.1 Memory Addressing Submenu NUMA nodes per socket Specifies the number of desired NUMA nodes per socket. Zero will attempt to interleave the two sockets together. NPS1 / NPS2 / NPS4 Memory interleaving Allows for disabling memory interleaving. Note that NUMA nodes per socket will be honored regardless of this setting.
  • Page 126 3.5.2.2.2 ACPI Submenu ACPI SRAT L3 Cache As NUMA Domain Enabled: Each CCX in the system will be declared as a separate NUMA domain. Disabled: Memory Addressing \ NUMA nodes per socket will be declared. Disabled / Enabled / Auto http://www.tyan.com...
  • Page 127 3.5.3 UMC Common Options Submenu DDR Addressing Options DDR addressing parameters DDR Timing Configuration DDT Timing parameters DDR RAS DDR RAS parameters DDR Security DDR Security parameters http://www.tyan.com...
  • Page 128 3.5.3.1 DDR Addressing Options Submenu Chipselect Interleaving Interleave memory blocks across the DRAM chip selects for node 0. Disabled / Auto BankSwapMode BankSwapMode value: 0=Disabled, 1= SwapCPU Auto / Disabled / Swap CPU http://www.tyan.com...
  • Page 129 3.5.3.2 DRAM Time Configuration Submenu Active Memory Timing Settings Active Memory Timing Settings Auto / Enabled NOTE: When Active Memory Timing Settings set to Enabled, the following items will appear. Memory Target Speed Specifies the memory target speed in MT/s. Auto / DDR3200 / DDR3600 / DDR4000 / DDR4400 / DDR4800 http://www.tyan.com...
  • Page 130 3.5.3.3 DDR RAS Submenu Data Poisoning Enable poison data creation on uncorrectable DDR DRAM ECC errors and poison propagation to CPU cores and caches. Requires ECC memory. When FALSE, a fatal error event will occur on DDR ECC errors sets UMC_CH::EccCtrl[UcFatalEn] when MC_CH ::EccCtrl[WrEccEn] is set.
  • Page 131 Disable Memory Error Injection 0=Enable. 1=Disable. Specifies UMC error injection configuration writes are disabled. True:: CH:: MiscCfg[DisErrInj]=1 False / True / Auto DRAM Corrected Error Counter Enable Configure DRAM Corrected Error Counter function. Only meaningful when PcdAmdCcxCfgPFEHEnable is TRUE. Disabled / NoLeakMode / LeakMode DRAM Corrected Error Counter Interleaving Enable SMI when DRAM Corrected Error Counter count exceeds the threshold value.
  • Page 132 3.5.3.3.1 DRAM Scrubbers Submenu DRAM ECS Mode 0 = AutoECS Mode, 1=ManualECS mode AutomaticECS / ManualECS / Auto / DisableECS DRAM Redirect Scrubber Enable Enable/Disable Dram Redirect Scrubber Disabled / Enabled / Auto DRAM Scrub Redirection Limit Dram ECC Scrub Redirection Limit: 0=8 scrubs, 1=4 scrubs, 2=2 scrubs, 3=1 scrub 8 Scrubs / 4 Scrubs / 2 Scrubs / 1 Scrubs / Auto DRAM Scrub Time Provide a value that is the number of hours to scrub memory.
  • Page 133 0=ETC_4 / 1=ETC_16 / 2=ETC_64 / 3=ETC_256(default – Auto) / 4 = ETC_1024 / 5 = ETC_4096 / Auto DRAM ECS Count Mode 0: RowCount Mode 1: CodeWord Mode 0xFF: Auto – ABL decides default as CodeWord Mode Row Count Mode / Code Word Count Mode / Auto DRAM AutoEcs during Self Refresh 0: AutoEcs Disabled 1: AutoEcs Enabled...
  • Page 134 3.5.3.3.2 ECC Configuration Submenu DRAM ECC Symbols Size DRAM ECC Symbol Size (x4/x16) UMC_CH::EccCtrl [EccSymbolSize16,EccSymbolSize] x4 / x16 / Auto DRAM ECC Enable Use this option to enable / disable DRAM ECC. Auto will set ECC to enable. Disabled / Enabled / Auto DRAM UECC Retry DRAM UECC Retry.
  • Page 135 3.5.3.4 DDR Security Submenu TSME Transparent Secure Memory Encryption Auto / Disabled / Enabled Data Scramble Data Scrambling Enabled / Disabled http://www.tyan.com...
  • Page 136 3.5.4 NBIO Common Options Submenu IOMMU Enable/Disable IOMMU Disabled / Enabled / Auto ACS Enable AER must be enabled for ACS enable to work Enabled / Disabled / Auto PCIe ARI Support Enables Alternative Routing-ID Interpretation Disabled / Enabled / Auto PCIe Ten Bit Tag Support Enables PCIe ten bit tags for supported devices.
  • Page 137 Enable AER Cap Enable Advanced Error Reporting Capability Disabled / Enabled / Auto NVME Hotplug Mode System would reset when the mode changed. EnterpriseSSD Mode / ServerExpress Mode http://www.tyan.com...
  • Page 138 3.5.4.1 SMU Common Options Submenu TDP Control Auto = Use the fused TDP Manual = User can set customized TDP Manual / Auto TDP (available if TDP Control is set to [Manual]) TDP [W] (in decimal) PPT Control Auto = Use the fused PPT Manual = User can set customized PPT Manual / Auto PPT (available if PPT Control is set to [Manual])
  • Page 139 Manual / Auto Determinism Enable (available if Determinism Control is set to [Manual]) [0 = Power; 1= Performance] Power / Performance APBDIS Algorithm Performance Boost Disable 0 / 1 / Auto Df Pstate DfPstate index to set when APBDIS=1 [0-2] Power Profile Selection DF Pstate selection in the profile policy is overridden by the pstate range BIOS option or the APB_DIS BIOS option if either one is selected.
  • Page 140 3.5.4.2 NBIO RAS Common Options Submenu NBIO RAS Control (0) Disabled, (1) MCA Disabled / MCA / Auto Egress Poison Severity High Each bit set to 1 enables HIGH severity on the associated IOHC egress port. A bit of 0 indicates LOW severity. Egress Poison Severity Low Each bit set to 1 enables HIGH severity on the associated IOHC egress port.
  • Page 141 NBIO SyncFlood Reporting This value may be used to enable SyncFlood reporting to APML. When set to TRUE SyncFlood will be reported to APML. When set to FALSE that reporting well be disabled. Enabled / Disabled / Auto Egress Poison Mask High These set the enable mask for masking of errors logged in EGRESS_ POISN_ STATUS.
  • Page 142 NBIO Poison Consumption Enabled / Disabled / Auto Sync Flood on PCIe Fatal Error When ‘ Sync Flood on PCIe Fatal Error’ is True, PcdAmdPcieSyncFloodOnFatal should be set to True. When ‘Sync Flood on PCIe Fatal Error’ is False, PcdAmdPcieSyncFloodOnFatal should be set to False. When ‘Sync Flood on PCIe Fatal Error’...
  • Page 143 3.5.5 FCH Common Options Submenu Ac Power Loss Options Ac Power Loss Settings FCH RAS Options FCH RAS Settings SATA Configuration SATA Settings http://www.tyan.com...
  • Page 144 3.5.5.1 AC Power LOSS Options Submenu Restore Ac Power Loss Select Restore AC Power Loss Method Power Off / Power On / Last State http://www.tyan.com...
  • Page 145 3.5.5.2 FCH RAS Options Submenu Reset After Sync flood Enable AB to forward downstream sync-flood message to system controller. Disabled / Enabled / Auto http://www.tyan.com...
  • Page 146 3.5.5.3 SATA Devices Options Submenu http://www.tyan.com...
  • Page 147 3.5.6 Soc Miscellaneous Control Submenu ABL Console Out Control Enable: Enable ConsoleOut Function for ABL Disable: Disable ConsoleOut Function for ABL Auto: Keep default behavior Disabled / Enabled / Auto PSP error injection support Enable EINJ support False / True http://www.tyan.com...
  • Page 148 3.5.7 AMD PBS Submenu AMD CPM RAS related settings http://www.tyan.com...
  • Page 149 3.5.7.1 RAS Submenu PCie Root Port UnCorrected Error Sev Re Initialize the PCIe AER Uncorrected Error Severity registers of Root Port Pcie Device Uncorrected Error Sev Reg Initialize the PCIe AER Uncorrected Error Severity registers of PCIe Device DRAM Hard Post Package Repair This feature allows spare DRAM rows to replace malfunctioning rows via an in-field repair mechanism.

  • Page 150: Server Management

    3.6 Server Management FRB-2 Timer Enable or Disable FRB-2 timer (POST timer) Disabled / Enabled NOTE: When [FRB-2 Timer] is set to [Enabled], the following items will be available. FRB-2 Timer timeout Enter value Between 3 to 6 min for FRB-2 Timer Expiration value 3 minutes / 4 minutes / 5 minutes / 6 minutes / 12 minutes FBR-2 Timer Policy Configure how the system should respond if the FRB-2 Timer expires.
  • Page 151 NOTE: When [OS Watchdog Timer] is set to [Enabled], the following items will be available. OS Wtd Timer Timeout Configure the length of the OS Boot Watchdog Timer. Not available if OS Boot Watchdog Timer is disabled. 5 minutes / 10 minutes / 15 minutes / 20 minutes OS Wtd Timer Policy Configure how the system should respond if the OS Boot Watchdog Timer expires.
  • Page 152 3.6.1 System Event Log Submenu SEL Components Change this to enable or disable event logging for error/progress codes during boot. Enabled / Disabled Erase SEL Choose options for erasing SEL. No / Yes, on next reset / Yes, on every reset Log EFI Status Codes Disable the logging of EFI Status Codes or log only error code or only progress code or both.
  • Page 153 3.6.2 BMC Network Configuration Submenu http://www.tyan.com...
  • Page 154 Configure IPV4 support Management Port 1 Configuration Address Source Select the configure LAN channel parameters statically or dynamically (by BIOS or BMC). Unspecified option will not modify any BMC network parameters during BIOS phase. Unspecified / Static / DynamicBmcDhcp / DynamicBmcNonDhcp Management Port 2 Enable/Disable BMC Share NIC Disabled / Enabled...
  • Page 155 3.6.3 BMC User Configuration Submenu Add User Press <Enter> to Add a User. Delete User Press<Enter> to Delete a User. Change User Settings Press<Enter> to Change User Settings. http://www.tyan.com...
  • Page 156 3.6.3.1 BMC User Configuration Submenu http://www.tyan.com...
  • Page 157 3.6.3.2 Delete User Configuration Submenu http://www.tyan.com...
  • Page 158 3.6.3.3 Change User Configuration Submenu http://www.tyan.com...

  • Page 159: Security

    3.7 Security Administrator Password Set Administrator Password. User Password Set User Password. Security Frozen Mode Enable or disable HDD security freeze lock. Disable to support secure erase function. Disabled / Enabled Secure Boot Customizable Secure Boot settings http://www.tyan.com...
  • Page 160 3.7.1 Secure Boot Configuration Submenu Secure Boot Secure boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. The mode change requires platform reset System mode is User/Deployed, and CSM function is disabled Enabled / Disabled Secure Boot Mode Secure Boot mode selector.
  • Page 161 Key Management Enables expert users to modify Secure Boot Policy variables without full authentication http://www.tyan.com...
  • Page 162 3.7.2 Key Management Factory Keys Provision Install factory default Secure Boot Keys after the platform reset and while the System is in Setup Mode. Enabled / Disabled Restore Factory Keys Force System to User Mode. Install Factory Default Secure Boot key databases. Reset To Setup Mode Delete all Secure Boot Key database from NVRAM Enroll Efi Image...
  • Page 163 Platform Key (PK) Enroll Factory Defaults or load certificates from a file: 1. Public Key Certificate: a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER encoded) c) EFI_CERT_RSA2048 (bin) d) EFI_CERT_SHA256,384,512 2. Authenticated UEFI Variable 3. EFI PE/COFF Image(SHA256) Key Source: Default, External, Mixed, Test Set New Key Exchange Keys Enroll Factory Defaults or load certificates from a file:...
  • Page 164 Default, External, Mixed Authorized TimeStamps Enroll Factory Defaults or load certificates from a file: 1. Public Key Certificate: a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER encoded) c) EFI_CERT_RSA2048 (bin) d) EFI_CERT_SHAXXX 2. Authenticated UEFI Variable 3. EFI PE/COFF Image(SHA256) Key Source: Default, External, Mixed OsRecovery Signatures Enroll Factory Defaults or load certificates from a file: 1.

  • Page 165: Boot

    3.8 Boot Setup Prompt Timeout Number of seconds to wait for setup activation key. 65535 (0xFFFF) means indefinite waiting. Bootup NumLock State Select the keyboard NumLock state. Off / On Quiet Boot Enables or disables Quiet Boot option. Disabled / Enabled Wait for “ESC”...
  • Page 166 Boot Option Priorities Boot Option #1 Sets the system boot order. Device Name / Disabled Delete Boot Option Remove an EFI boot option from the boot order http://www.tyan.com...
  • Page 167 3.8.1 Delete Boot Option Configuration Delete Boot Option Remove an EFI boot option from the boot order. Device Name / Select one to Delete http://www.tyan.com...

  • Page 168: Save & Exit

    3.9 Save & Exit Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Save Changes and Reset Reset the system after saving the changes. Discard Changes and Reset Reset system setup without saving any changes.
  • Page 169 http://www.tyan.com...
  • Page 170 Save as User Defaults Save the changes done so far as User Defaults. Restore User Defaults Restore the User Defaults to all the setup options. Boot Override Device Name http://www.tyan.com...

  • Page 171: Chapter 4: Diagnostics

    Chapter 4: Diagnostics NOTE: if you experience problems with setting up your system, always check the following things in the following order: Memory, Video, CPU By checking these items, you will most likely find out what the problem might have been when setting up your system.

  • Page 172: Amibios Post Code (Aptio)

    4.2 AMIBIOS Post Code (Aptio) The POST code checkpoints are the largest set of checkpoints during the BIOS pre- boot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS: Checkpoint Ranges Status Code Range Description 0x01 –...
  • Page 173 SEC Error Codes 0x0C – 0x0D Reserved for future AMI SEC error codes 0x0E Microcode not found 0x0F Microcode not found SEC Phase None PEI Phase Status Code Description Progress Codes 0x10 PCI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13...
  • Page 174 Status Code Description CPU post-memory initialization. Boot Strap Processor (BSP) 0x35 selection CPU post-memory initialization. System Management Mode (SMM) 0x36 initialization 0x37 Post-Memory North Bridge initialization is started. Post-Memory North Bridge initialization (North Bridge module 0x38 specific) Post-Memory North Bridge initialization (North Bridge module 0x39 specific) Post-Memory North Bridge initialization (North Bridge module...
  • Page 175 Status Code Description S3 Resume Error Codes 0xE8 S3 Resume failed 0xE9 S3 Resume PPI not found 0xEA S3 Resume Boot Script error 0xEB S3 OS wake error 0xEC – 0xEF Reserved for future AMI error codes Recovery Progress Codes 0xF0 Recovery condition triggered by firmware (Auto recovery) 0xF1...
  • Page 176 Status Code Description 0x63 CPU DXE initialization is started. 0x64 CPU DXE initialization (CPU module specific) 0x65 CPU DXE initialization (CPU module specific) 0x66 CPU DXE initialization (CPU module specific) 0x67 CPU DXE initialization (CPU module specific) 0x68 PCI host bridge initialization 0x69 North Bridge DXE initialization is started.
  • Page 177 Status Code Description 0x9B USB Reset 0x9C USB Detect 0x9D USB Enable 0x9E -0x9F Reserved for future AMI codes 0xA0 IDE initialization is started 0xA1 IDE Reset 0xA2 IDE Detect 0xA3 IDE Enable 0xA4 SCSI initialization is started. 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7...
  • Page 178 Status Code Description 0xD5 No Space for Legacy Option ROM 0xD6 No Console Output Devices are found. 0xD7 No Console Input Devices are found. 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error). 0xDB Flash update is failed.

  • Page 179: Appendix I: Fan And Temp Sensors

    Appendix I: Fan and Temp Sensors This section aims to help readers identify the locations of some specific FAN and Temp Sensors on the motherboard. A table of BIOS Temp sensor name explanation is also included for readers’ reference. NOTE: The red dot indicates the sensor.
  • Page 180 BIOS Temp Sensor Name Explanation: http://www.tyan.com...
  • Page 181 BIOS Temp Sensor Name Explanation SYS_Air_Inlet Temperature of the System Air Inlet Area SYS_Air_Outlet Temperature of the System Air Outlet Area MB_Air_Inet Temperature of the M/B Air Inlet Area P0_MOSFET_1 Temperature of the P0_MOSFET_1Area P0_MOSFET_2 Temperature of the P0_MOSFET_2Area P0_MOSFET_3 Temperature of the P0_MOSFET_3Area X710_LAN_Temp Temperature of the X710_LAN...

  • Page 182: Appendix Ii: How To Recover Uefi Bios

    Appendix II: How to recover UEFI BIOS Important Notes: The emergency UEFI BIOS Recovery process is only used to rescue a system with a failed or corrupted BIOS image that fails to boot to an OS. It is not intended to be used as a general purpose BIOS flashing procedure and should not be used as such.
  • Page 183 5.The system will boot to BIOS setup. A new menu item will appear at the far right of the screen. Scroll to the 'Recovery' tab, move the curser to “Proceed with flash update” and press the "Enter" key on the keyboard to start the BIOS recovery process.

  • Page 184: Glossary

    Glossary ACPI (Advanced Configuration and Power Interface): a power management specification that allows the operating system to control the amount of power distributed to the computer’s devices. Devices not in use can be turned off, reducing unnecessary power expenditure. AGP (Accelerated Graphics Port): a PCI-based interface which was designed specifically for demands of 3D graphics applications.
  • Page 185 Bus: a data pathway. The term is used especially to refer to the connection between the processor and system memory, and between the processor and PCI or ISA local buses. Bus mastering: allows peripheral devices and IDEs to access the system memory without going through the CPU (similar to DMA channels).
  • Page 186 DRAM (Dynamic RAM): widely available, very affordable form of RAM which looses data if it is not recharged regularly (every few milliseconds). This refresh requirement makes DRAM three to ten times slower than non-recharged RAM such as SRAM. ECC (Error Correction Code or Error Checking and Correcting): allows data to be checked for errors during run-time.
  • Page 187 I/O (Input/Output): the connection between your computer and another piece of hardware (mouse, keyboard, etc.) IRQ (Interrupt Request): an electronic request that runs from a hardware device to the CPU. The interrupt controller assigns priorities to incoming requests and delivers them to the CPU. It is important that there is only one device hooked up to each IRQ line;...
  • Page 188 RAID (Redundant Array of Independent Disks): a way for the same data to be stored in different places on many hard drives. By using this method, the data is stored redundantly and multiple hard drives will appear as a single drive to the operating system.
  • Page 189 Standby mode: in this mode, the video and hard drives shut down; all other devices continue to operate normally. UltraDMA-33/66/100: a fast version of the old DMA channel. UltraDMA is also called UltraATA. Without a proper UltraDMA controller, your system cannot take advantage of higher data transfer rates of the new UltraDMA/UltraATA hard drives.

  • Page 190: Technical Support

    Technical Support If a problem arises with your system, you should first turn to your dealer for direct support. Your system has most likely been configured or designed by them and they should have the best idea of what hardware and software your system contains.
  • Page 191 FCC Declaration ● Notice for the USA Compliance Information Statement (Supplier's Declaration of Conformity, SDoC) This device complies with Part 15 of the FCC Rules. Operation is subject to the following conditions: ‧This device may not cause harmful interference. ‧This device must accept any interference received, including interference that may cause undesired operation.

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