Vertex Standard VX-1700 Series Service Manual page 9

varactor diodes D1047, D1048, D1049, D1050, D1051,
D1052, D1053, and D1054 (all HVU359).
Changes in the DC voltage applied to these varactor
diodes affect the reactance in the tank circuit of VCOs
Q1072 and Q1073 (both 2SK210GR), changing the
oscillating frequency according to the phase differ-
ence between the signals derived from the VCO and
the TCXO reference oscillator. The VCO is thus
phase-locked to the reference frequency standard.
A portion of the output of reference signal from
TCXO X1003 is multiplied by four at Q1070
(2SC2714Y). The resulting 90.5 MHz signal is buff-
ered by Q1075 (2SC2714Y), then applied to a low-
pass filter, consisting of capacitors C1401, C1405,
C1410, C1411, and C1421 and coils L1075 and L1077.
The filtered reference signal is applied to the TX 1st
mixer Q1054 and RX 2nd mixer Q1052 (both
RF2713).
Control Circuit
Major frequency control functions such as channel
selection, display, and PLL divider control are per-
formed by main CPU Q1018 (HD64F2134) on the
MAIN Unit, at the command of the user via the tun-
ing knob and function switches on the front panel.
The programmable divider data for the PLL from
the main CPU is applied directly to DDS IC Q1016
(AD9833BRM) and PLL subsystem IC Q1056
(ADF4001BRU).
The Mode selection data from the main CPU is also
delivered to DSP IC Q1035 (UPD77115) to control
the various circuits required for the selected mode.
The Band selection binary data from the main CPU
is decoded (BCD to Decimal) by Q1011 (TC4028BF).
The resulting decimal outputs are level-shifted by
Q1003 (TD62783AF) to select the active band-pass
filter on the MAIN Unit required for the operating
frequency. Also, the decimal outputs from Q1003
(TD62783AF) are delivered to PA Unit, where they
are used to select the active low-pass filter required
for the operating frequency.
VX-1700 Series (EXP Version) Service Manual
Circuit Description
TX/RX Control
When the PTT switch is pressed, pin 21 of the main
CPU Q1018 (HD64F2134) goes low, which causes
pin 60 of the main CPU Q1018 (HD64F2134) to go
low. This signal disables the receiver 12 V bus at
Q1046 (2SA1602A). At the same time, pin 59 of the
main CPU Q1018 (HD64F2134) goes low to activate
the transmit 12 V bus at Q1048 (2SA1365).
Power Supply & Regulation
The +5 V bus for the main CPU Q1018 (HD64F2134)
is derived from the 13.5 V bus via regulator Q1012
(BA05FP) on the MAIN Unit. The +8 V bus is de-
rived from the 13.5 V bus via regulator Q1007
(KIA7808API) on the MAIN Unit.
A portion of the +8 V bus is regulated by Q1008
(L78M05T) for the +5 V bus, and is regulated by
Q1006 (UPC2926) for the +2.6 V bus required by the
DSP IC Q1035 (UPD77115GK).
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