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Table. Clock Switching Output Clock Rates
Clock Recovery and PLL Filter
Please see "Appendix C: PLL Filter" on page 55 for a general description of the PLL, selection of
recommended PLL filter components, and layout considerations. Figure 5 and Figure 6 shows the
recommended configuration of the two capacitors and one resistor that comprise the PLL filter.
GENERAL PURPOSE OUTPUTS
Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in
configuring the CS8416. Fourteen signals are available to be routed to any of the GPO pins. The
outputs of the GPO pins are set through the GPOxSEL[3:0] bits in the Control2 (02h) and Control3
(03h) registers. All GPO pins default to GND after reset.
GPO pins may be configured to provide the following data:
CONFIDENTIAL
DO NOT COPY
Page 7-43
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File No. SG-0228
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