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Figure B. Typical Connection Diagram - Hardware Mode
S/PDIF RECEIVER
The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes
bi-phase encoded audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ
CP-1201 interface standards. The receiver consists of an analog differential input stage, driven
through analog input pins RXP0 to RXP7 and a common RXN, a PLL based clock recovery circuit,
and a decoder which separates the audio data from the channel status and user data. External
components are used to terminate the incoming data cables and isolate the CS8416. These
components are detailed in "Appendix A: External AES3/SPDIF/IEC60958 Receiver Components"
on page 51. Figure 9 shows the input structure of the receiver.
CONFIDENTIAL
DO NOT COPY
Page 7-40
–
File No. SG-0228
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