Vizio JV50P HDTV10A Service Manual
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Vizio JV50P HDTV10A Service Manual

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Service Manual
Model #: VIZIO JV50P HDTV10A
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
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Summary of Contents for Vizio JV50P HDTV10A

  • Page 1 Service Manual Model #: VIZIO JV50P HDTV10A V, Inc 320A Kalmus Drive Costa Mesa, CA 92626 TEL : +714-668-0588 FAX :+714-668-9099 Top Confidential...

  • Page 2: Table Of Contents

    8. Waveforms 9. Trouble Shooting 10. Block Diagram 10-1 11. Spare parts list 11-1 12. Complete Parts List 12-1 Appendix 1. Main Board Circuit Diagram 2. Main Board PCB Layout 3. Assembly Explosion Drawing Block Diagram VIZIO JV50P HDTV10A Service Manual...
  • Page 3 Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL); Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric Appliance Control Act); or an AC cord that meets the local safety standards. VIZIO JV50P HDTV10A Service Manual...

  • Page 4: Features

    Chapter 1 Features 1. Built in TV channel selector for TV viewing 2. Simulatnueous display of PC and TV images 3. Connectable to PC’s analog RGB port 4. Built in HDTV, composite video, HDMI ,ATV out and DTV out , Audio AUX IN 5.

  • Page 5: Specifications

    Chapter 2 Specification 1. PDP CHARACTERISTICS PDP50X4 (50”WXGA PDP MODULE) Item Specification 50 inch diagonal Active Screen Size 1190(H) × 700(V) × 58(D) ± 1mm Outline Dimension 1106.5(H) × 622.1(V) ± 0.5mm Display Area Pixel Pitch 810 ㎛(H) × 810 ㎛(V) Cell Pitch 270 ㎛...
  • Page 6 5.Speaker Output 10W (max) X3 Wireless Speaker : 10W(max) (1) Rear Right Rear Left 10W(max) Subwoofer 20W(max) 6. ENVIRONMENT 7-1. Operating Temperature: 5c~35c (Ambient) 7-2. Operating Humidity: Ta= 35 °C, 90%RH (Non-condensing) 7-3. Operating Altitude: 0 - 14,000 feet (Non-Operating) 7.
  • Page 7 (5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro-chemical reaction. (6) Do not touch, push or rub the exposed polarizes with glass, tweezers or anything harder than HB pencil lead.
  • Page 8 9-3. HANDLING PRECAUTIONS FOR PROTECTION (1) The protection film is attached to the bezel with a small masking tape. When the protection film is peeled off, static electricity is generated between the film and polarizer. This should be peeled off slowly and carefully by people who are electrically grounded and with well ion-blown equipment or in such a condition, etc.

  • Page 9: On Screen Display

    Chapter 3 On Screen Display Main unit button Power MENU CH ▲ CH ▼ VOL + VOL - Input On Screen Display TV Source A. PICTURE： a. PICTURE MODE (CUSTOM/ STANDARD / MOVIE / GAME) b. BACKLIGHT (0~100) c. BRIGHTNESS (0~100) d.
  • Page 10 B. AUDIO： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h.
  • Page 11 D. SETUP： a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. ANALOG CC (OFF/CC1/CC2/CC3/CC4) d. DIGITAL CC(OFF/SERVICE1/ SERVICE2/ SERVICE3/ SERVICE4/ SERVICE5/ SERVICE6) e. DIGITAL CC STYLE e-1. CAPTION STYLE (AS BROADCASTER/CUSTOM) e-2. FONT SIZE(SMALL/MEDIUM/LARGE) e-3. FONT COLOR (GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE) e-4. FONT OPACITY (SOLID/TRANSLUCENT/TRANSPARENT) e-5.
  • Page 12 RGB Mode A. PICTURE ADJUST： a. AUTO PICTURE (Run) b. BACKLIGHT (0~100) c. BRIGHTNESS (0~100) d. CONTRAST (0~100) e. COLOR TEMPERATURE(CUSTOM, 6500K,9300K) f. H-SIZE (0~255) g. H-POSITION (0~100) h. V-POSITION (0~100) i. FINE TUNE (0~31) B. AUDIO： a. VOLUME (0~100) b.
  • Page 13 C. SETUP： a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. Image Cleaner d. RESET ALL SETTING HDMI MODE A. PICTURE： a. PICTURE MODE (CUSTOM/ STANDARD /MOVIE / GAME) b. BRIGHTNESS (0~100) c. CONTRAST (0~100) d. COLOR (0~100) e. TINT (-32~32) f.
  • Page 14 h-2. TRIM h-2-1. Left(0~100) h-2-2. Right(0~100) h-2-3. Rear Left(0~100) h-2-4. Rear Right(0~100) h-2-5. Center(0~100) h-2-6. Sub Woofer(0~100) h-3. SPEAKER DISTANCE SETUP h-3-1. TV (0~15ft.) h-3-2. Rear Left(0~15ft.) h-3-3. Rear Right(0~15ft.) C. SETUP： a. LANGUAGE (ENGLISH/FRENCH/SPANISH) b. SLEEP TIMER (OFF/30/60/90/120) c. Image Cleaner d.
  • Page 15 B. AUDIO： a. VOLUME (0~100) b. BASS (0~100) c. TREBLE (0~100) d. DCR( Off / 1/4 / 1/2 / 3/4 / Full ) e. SPEAKERS (ON/OFF) f. Wireless SPEAKERS (ON/OFF) g. SPDIF IN( Off / AV1 / AV2 / COMPONENT1 /COMPONENT2 / HDMI1 / HDMI2 / HDMI3 ) h.
  • Page 16 D. PARENTAL： a. PASSWORD a-1. CHANNEL BLOCK a-2. TV RATING a-3. MOVIE RATING a-4. BLOCK TV UNRATED a-5. ACCESS CODE EDIT CONFIDENTIAL DO NOT COPY Page 3-8 – File No. SG-0228...

  • Page 17: Factory Preset Timings

    Chapter4 Factory preset timings This timing chart is already preset for the TFT LCD analog & digital display monitors. Refresh Horizontal Vertical Horizontal Vertical Pixel Resolution rate Frequency Frequency Polarity Polarity Rate 640x480 60Hz 31.5kHz 59.94Hz 25.175MHz 640x480 75Hz 37.5kHz 75.00Hz 31.500 MHz 800X600...

  • Page 18: Pin Assignment

    Chapter5 Pin Assignment The PDP analog display monitors use a 15 Pin Mini D-Sub connector as video input source. Description Green Blue Ground Ground R-Ground G-Ground B-Ground +5V for DDC Ground No Connection (SDA) H-Sync (Composite Sync) V-Sync (SCL) CONFIDENTIAL – DO NOT COPY Page 5-1 File No.
  • Page 19 RGB Signal: a. Sync Type TTL (Separate / Composite) or Sync. On Green b. Sync polarity Positive or Negative c. Video Amplitude RGB: 0.7Vp-p d. Frequency H: support to 30K~70KHz V: support to 50~85Hz e. Pixel Clock: support to 110MHz f.
  • Page 20 HDMI Signal (HDMI): a. Pin Assignment Refer to HDMI Pin Assignment b. Type A c. Polarity Positive or Negative d. Frequency H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i) F-Type TV RF connector NTSC system a.
  • Page 21 AV/Composite Video (CVBS) Connector a. Frequency: H: 15.734KHz V: 60Hz (NTSC) b. Signal level: Video ( Y + C ):1Vp-p Sync (H+V):0.3V below Video (Y+C) c. Impedance: 75Ω d. Connector type: RCA Jack Component video Connector a. Frequency: H: 15.734KHz V: 60Hz (NTSC-480i) H: 31KHz V: 60Hz (NTSC-480p) H: 45KHz V: 60Hz (NTSC-720p) H: 33KHz V: 60Hz (NTSC-1080i)

  • Page 22: Main Board I/O Connections

    Chapter 6 Main Board I/o Connections J10 C PSU) ONNECTION AIN TO ANEL Description VS_ON PDP_12VFAN PDP_12VSC PDP_5VSC PDP_5VSC PDP_5VSC PDP_5VSB RLY_ON J12 C ONNECTION AIN TO UDIO OARD Description AUDIO_CT DACGND AUDIO_OUTR AMP_MUT AUDIO_OUTL DACGND CONFIDENTIAL DO NOT COPY Page 6-1 –...
  • Page 23 J13 C ONNECTION Description J9 C ONNECTION Description AMBER WHITE OIRI 5VSB 5VSB ADIN-1 ADIN-2 DV33SB HPL_IN HPR_IN HPIN_DET CONFIDENTIAL DO NOT COPY Page 6-2 – File No. SG-0228...
  • Page 24 J14 C ONNECTION Description PGND TX_SGND ID_Trigge TX_Mute ACD_mute AO1LRCK AO1SDATA1 AO1BCK AO1MCLK CONFIDENTIAL DO NOT COPY Page 6-3 – File No. SG-0228...
  • Page 25 J7 C ONNECTION Description Description CK1N CK2P CK2N LVDS_ROTATE LVDS_OPTION LVDSVDD LVDSVDD CK1P LVDSVDD BD I/O C UDIO ONNECTIONS OF J1 C →A ONNECTION OARD UDIO OARD Description “CT” “COM” “R” “mute” “L” “SGND” “GND” “AC_detect” CONFIDENTIAL DO NOT COPY Page 6-4 –...
  • Page 26 J2 C →A ONNECTION OWER OARD DUIO OARD Description “+24V” “+24V” “GND” “GND” J3 C →EMI B ONNECTION UDIO OARD OARD Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” AFER INFORMATION Pin1 CONFIDENTIAL DO NOT COPY Page 6-5 – File No. SG-0228...
  • Page 27 EMI BD I/O C ONNECTIONS J1 C →EMI B ONNECTION UDIO OARD OARD Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” J2 C (EMI B →S ONNECTION OARD PEAKERS Description “ROUT+” “GND” “CTOUT+” “GND” “LOUT+” “GND” CONFIDENTIAL DO NOT COPY Page 6-6 –...
  • Page 28 AFER INFORMATION Pin1 Pin1 CONFIDENTIAL DO NOT COPY Page 6-7 – File No. SG-0228...
  • Page 29 BD I/O C UDIO ONNECTIONS OF UBWOOFER J1 C →A ONNECTION MODULE UDIO OARD Audio BD Description Module Description “VCCIO” “VCCIO” “PGND” “PGND” “RS” “-” “PGND” “PGND” “SGND” “UGND” “NC” “TEST” “LS” “-” “NC” “-” “PGND” “-” “NC” “-” “Mute” “Mute”...
  • Page 30 J3 C →I/O B ONNECTION UDIO OARD OARD Description “LOUT+” “LGND” “ROUT+” “RGND” J4 C →S ONNECTION UDIO OARD UBWOOFER Description “SWOUT+” “SWOUT-” J5 C →L ONNECTION UDIO OARD OARD Description “GND” “+5V” J6 C →I/O B ONNECTION UDIO OARD OARD Description “CH/ID”...
  • Page 31 AFER INFORMATION Pin1 Pin1 CONFIDENTIAL DO NOT COPY Page 6-10 – File No. SG-0228...
  • Page 32 Pin1 CONFIDENTIAL DO NOT COPY Page 6-11 – File No. SG-0228...
  • Page 33 BD I/O C ONNECTOR ONNECTIONS J1 C → ONNECTION BOTTOM Description “RS+” “RS-” “LS+” “LS-” “Switch+” “Switch-” “GND” J2 C → ONNECTION BOTTOM Description “LS-” “LS+” “RS-” “RS+” AFER INFORMATION Blue circle : 1s Red circle : 1t Green circle : 2s Brown circle : 2t CONFIDENTIAL DO NOT COPY...
  • Page 34 Pin1 CONFIDENTIAL DO NOT COPY Page 6-13 – File No. SG-0228...

  • Page 35: Theory Of Circuit Operation

    Chapter 7 Theory of Circuit Operation The operation of D-SUB 15pin route The D-SUB 15pin is input analog signal to the MT5372 transfer A/D converter then generates the vertical and horizontal timing signals for display device. The operation of HDMI CON route Then transfer to the MT5372, the MT5372 generates the vertical and horizontal timing signals for display device.
  • Page 36 MT5372 Application MT5372 is a highly integrated video and audio single chip processor for emerging HDTV-Ready LCD TV. It includes one 3D/2D TV Decoder recovering the best image from CVBS, and in addition, its analog input also support popular S-Video, Component, VGA video source.
  • Page 37 CONFIDENTIAL DO NOT COPY Page 7-3 – File No. SG-0228...
  • Page 38 1. Video input a. Input Multiplexing 1.component X2 2.composite X2 3.HDMI X3 4.VGA X1 5.RF&DTV X1 b. Input formats: 1.support HDTV 480i/480p/720p/1080p 2.support Y/C signal 1VP-P/75Ω 3.support 480i/408p/720p/1080i/1080p 4.support VGA input up to 1366x168@60HZ 6.support RF NTSC system Frequency 55~801MHZ;DTV 480i/480p/720p/1080p 2.
  • Page 39 Digital port 1.1 digital port supporting DVI 24-bit RGB or CCIR-656/601 digital video input format 2.1 additional 8 bit digital port for ITU656 video format 1.Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS 2.Supporting external VBI decoder by YPrPb input 3.VBI decoder up to 1000 pages Teletext.
  • Page 40 5. Microprocessor interface When power is supplied and power key is pressed then the rest circuit lets Reset to low state that will reset the MT5372 to initial state. After that the Reset will transits to high state and the MT5372 start to work that microprocessor executes the programs and configures the internal registers.
  • Page 41 3.De-interlacing 2nd generation advanced Motion adaptive de-interlacing Automatic detect film or video source 3:2/2:2 pull down source detection Main/PIP 2 independent de-interlacing processor 4.Scaling 2nd generation high resolution arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X Advanced linear and non-linear Panorama scaling Programmable Zoom viewer Picture-in-Picture (PIP) Picture-Out-Picture (POP)
  • Page 42 2.For single DDR,5372only support 1080i bob mode de-interlacing. (Non-3D de interlace) 3.With single DDR, it is suggested not to support PIP/POP features. Due to DDR Bandwidth limitation on PIP when single DDR. MT8291 Application The MT8291 is highly integrated stereo audio CODEC.The MT8291 performs stereo analog-to-digital and two digital-to-analog conversions with single-ended analog voltage input and output.
  • Page 43 BLOCK DIAGRAM Feature List ● 24-bit Sigma- Delta ADC and DAC ● Allows 2Vrms input swing into ADC part ● ADC up to 96 kHz sampling rates ● 90 dB ADC dynamic range ● Automatic Gain Control (AGC) ● 90 dB DAC dynamic range ●...
  • Page 44 CONTROL INTERFACE TIMING - 2 WIRE PORT Figure. Control Port Timing CONFIDENTIAL DO NOT COPY Page 7-10 – File No. SG-0228...
  • Page 45 AUDIO INTERFACE TIMING1 AVDD=12V,DVDD=3.3V,ADCGND/DACGND=0V, Ta=    2 5 C, fs=48kHz, 　 MCLK=256fs, 24bit data, Master Mode Figure. Master Mode Timing CONFIDENTIAL DO NOT COPY Page 7-11 – File No. SG-0228...
  • Page 46 AUDIO INTERFACE TIMING2 AVDD=12V,DVDD=3.3V,ADCGND/DACGND=0V, Ta= ° + 25 C, fs=48kHz, MCLK=256fs, 24bit data, Slave Mode Figure. Slave Mode Timing CONFIDENTIAL DO NOT COPY Page 7-12 – File No. SG-0228...
  • Page 47 3. HDCP Decryption HDCP decryption contains all necessary logic to decrypt the incoming audio and video data. The decryption process is entirely controlled by the host microprocessor through a set sequence of register reads and wires through the DDC channel. Pre-programmed HDCP keys and key Selection Vector are used in the decryption process.
  • Page 48 5 . 2D Graphics : 1. Support multiple color modes. 2. Point , horizontal/vertical line primitive drawing. 3. Rectangle fill and gradient fill functions. 4. Bitblt with transparent , alpha blending , alpha composition and stretch. 5. Font rendering by color expansion. 6.
  • Page 49 10 . TV Encoder : 1. Support NTSC M/N , PAL M/N/B/D/G/H/I 2. Macrovision Rev 7.1.L1 3. CGMS/WSS. 4. Closed Captioning. 5. Six 12-bit video DACs for CVBS , S-video or RGB/YPbPr output. 11 . Digital Video Interface : 1. Support SAV/EAV. 2.
  • Page 50 15 . Peripherals : 1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control. 2. Two serial interfaces , one is master only the other can be set to master mode or slave mode. 3.
  • Page 51 CONFIDENTIAL DO NOT COPY Page 7-17 – File No. SG-0228...
  • Page 52 BLOCK DIAGRAM CONFIDENTIAL DO NOT COPY Page 7-18 – File No. SG-0228...
  • Page 53 BUS OPERATION--1 Legend: L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 0.5V, V HH=11.5-12.5V, X=Don't Care, 　 AIN=Address IN, DIN=Data IN,DOUT=Data OUT Notes: 1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2.The sector group protect and chip unprotect functions may also be implemented via programming equipment.
  • Page 54 BUS OPERATION--2 Notes: 1.Code=00h means unprotected, or code=01h protected. 2.Code=99 means factory locked, or code=19h not factory locked. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE and CE to VIL, and OE to VIH.An erase operation can erase one sector, multiple sectors , or the entire device.
  • Page 55 TABLE A. MX29LV320AT/B COMMAND DEFINITIONS Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE or CE pulse. PD=Data to be programmed at location PA.
  • Page 56 STANDBY MODE MX29LV320AT/B can be set into Standby mode with two different approaches. One is using both CE and RESET pins and the other one is using RESET pin only. When using both pins of CE and RESET, a CMOS Standby mode is achieved with both pins held at Vcc ±0.3V.
  • Page 57 If RESET is asserted during a program or erase operation, the RY/BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset operation is complete.
  • Page 58 WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY.Table B and the following subsections describe the functions of these bits. Q7, RY/BY, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress.
  • Page 59 Fig C. COMMAND WRITE OPERATION Fig D. READ TIMING WAVEFORMS CONFIDENTIAL DO NOT COPY Page 7-25 – File No. SG-0228...
  • Page 60 Fig E. RESET TIMING WAVEFORM CONFIDENTIAL DO NOT COPY Page 7-26 – File No. SG-0228...
  • Page 61 DDR SDRAM (NT5DS16M16CS-5T) Application: Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
  • Page 62 Pin Configuration - 400mil TSOP II (x4 / x8 / x16) CONFIDENTIAL DO NOT COPY Page 7-28 – File No. SG-0228...
  • Page 63 Mode Register Operation Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values.
  • Page 64 Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition.
  • Page 65 Truth Table a: Commands 1. CKE is high for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects ,Extended Mode Register; other combinations of BA0-BA1 are reserved;...
  • Page 66 Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;...
  • Page 67 Operations: Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied.
  • Page 68 Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) CONFIDENTIAL DO NOT COPY Page 7-34 – File No. SG-0228...
  • Page 69 Read Command Writes Write bursts are initiated with a Write command, as shown in timing figure Write Command on following: The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst.
  • Page 70 The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture).
  • Page 71 Data Output (Read) CONFIDENTIAL DO NOT COPY Page 7-37 – File No. SG-0228...
  • Page 72 Optical Receiver CS8416 Application: The CS8416 is a monolithic CMOS device which receives and decodes audio data according to the AES3,IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8416 utilizes an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416.
  • Page 73 TYPICAL CONNECTION DIAGRAMS Figure A. Typical Connection Diagram - Software Mode CONFIDENTIAL DO NOT COPY Page 7-39 – File No. SG-0228...
  • Page 74 Figure B. Typical Connection Diagram - Hardware Mode S/PDIF RECEIVER The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encoded audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of an analog differential input stage, driven through analog input pins RXP0 to RXP7 and a common RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data.
  • Page 75 If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1. If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2. If RXP[7:0] is not selected at all, N=0 (i.e. high impedance). Figure.
  • Page 76 Software Mode The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. The multiplexer defaults to RXP0. The second output of the input multiplexer is used to provide the selected input as a source to be output on a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h.
  • Page 77 Table. Clock Switching Output Clock Rates Clock Recovery and PLL Filter Please see “Appendix C: PLL Filter” on page 55 for a general description of the PLL, selection of recommended PLL filter components, and layout considerations. Figure 5 and Figure 6 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter.
  • Page 78 Table. GPO Pin Configurations Notes: 16. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ FS = 48 kHz. CS8416 Block Diagram. MP7720/7722 Application In JV50P TV the MP7720 is a mono 10W Class D Audio Amplifier and the MP7722 is a stereo 10W Class D Audio Amplifier.
  • Page 79 TYPICAL APPLICATION for MP7720 TYPICAL APPLICATION for MP7722 CONFIDENTIAL DO NOT COPY Page 7-45 – File No. SG-0228...
  • Page 80 1. DESCRIPTION The MP7722 utilizes a single ended output structure capable of delivering 2 x 20W into 4Ω speakers. MPS Class D Audio Amplifiers exhibit the high fidelity of a Class A/B amplifier at efficiencies greater than 90%. The circuit is based on the MPS’ proprietary variable frequency topology that delivers low distortion, fast response time and operates on a single power supply.
  • Page 81 Mute/Enable Function The MP7722 EN inputs are active high enable controls. To enable the MP7722, drive EN with a 2.0V or greater voltage. To disable the Amplifier, drive it below 0.4V. While the MP7722 is disabled, the VDD operating current is less than 10µA and the output driver MOSFETs are turned off.
  • Page 82 MP7782 Application In JV50P TV the MP7782 is a mono, 50W Class D Audio Amplifier. It has output power of 1 x50 W into 6 ohm with 24V supply. TYPICAL APPLICATION DESCRIPTION The MP7782 utilizes a full bridge output structure capable of delivering 50W into 6Ω speakers. As in all other MPS Class D audio amplifiers, this device exhibits the high fidelity of a Class AB amplifier with an efficiency of 90%.

  • Page 83: Waveforms

    Chapter8 Waveforms PC MODE(1366X768 60HZ) CH1 H-sync (R209); CH2 H-sync (L52) CH1 V-sync (R213); CH2 V-sync (L53) CONFIDENTIAL DO NOT COPY Page 8-1 – File No. SG-0228...
  • Page 84 CH1 R (R203) CH1 R (C95) CH1 B (R199) CH1 B (C92) CONFIDENTIAL DO NOT COPY Page 8-2 – File No. SG-0228...
  • Page 85 CH1 G (R195) CH1 G (C89) AV&TV MODE (AV1/AV2/TV) VIDEO CH1 TV CONFIDENTIAL DO NOT COPY Page 8-3 – File No. SG-0228...
  • Page 86 CH1 AV1 CH1 AV2 CONFIDENTIAL DO NOT COPY Page 8-4 – File No. SG-0228...
  • Page 87 COMPONENT MODE CH1 YPBPR1_Y CH1 YPBPR2_Y CONFIDENTIAL DO NOT COPY Page 8-5 – File No. SG-0228...
  • Page 88 HDMI 1 CH1 RX1; CH2 RX1-B HDMI 2 CH1 RX1; CH2 RX1-B CONFIDENTIAL DO NOT COPY Page 8-6 – File No. SG-0228...
  • Page 89 HDMI 3 CH1 RX1; CH2 RX1-B Audio BD of TV Input Level: 100mV , Frequency: 1KHz (L and R and CT) 1. CH1: C200 + ; CH2: J3 PIN3 CONFIDENTIAL DO NOT COPY Page 8-7 – File No. SG-0228...
  • Page 90 2. CH1: C108 - ; CH2: U1 PIN7 3. CH1: ZD2 PIN2 ; CH2: ZD2 PIN1 [signal on] CONFIDENTIAL DO NOT COPY Page 8-8 – File No. SG-0228...
  • Page 91 [signal off] CH1: C271 + ; CH2: J3 PIN3 CONFIDENTIAL DO NOT COPY Page 8-9 – File No. SG-0228...
  • Page 92 4. CH1: ZD4 PIN2 ; CH2: ZD4 PIN1 [signal on] [signal off] CONFIDENTIAL DO NOT COPY Page 8-10 – File No. SG-0228...
  • Page 93 5. CH1: C192 + ; CH2: EN1 [Power on] [Power off] CONFIDENTIAL DO NOT COPY Page 8-11 – File No. SG-0228...
  • Page 94 Audio BD of Subwoofer Input Level: 100mV , Frequency: 1KHz (LS and RS) 50Hz (Subwoofer) 1. CH1: C200 + ; CH2: J3 PIN3 2. CH1: C108 - ; CH2: U1 PIN7 CONFIDENTIAL DO NOT COPY Page 8-12 – File No. SG-0228...
  • Page 95 3. CH1: ZD2 PIN2 ; CH2: ZD2 PIN1 [signal on] [signal off] CONFIDENTIAL DO NOT COPY Page 8-13 – File No. SG-0228...
  • Page 96 4. CH1: C170 + ; CH2: J4 PIN2 5. CH1: ZD4 PIN2 ; CH2: ZD4 PIN1 [signal on] CONFIDENTIAL DO NOT COPY Page 8-14 – File No. SG-0228...
  • Page 97 [signal off] 6. CH1: C192 + ; CH2: EN1 [Power on] CONFIDENTIAL DO NOT COPY Page 8-15 – File No. SG-0228...
  • Page 98 [Power off] 7. CH1: R154 ; CH2: C142 + [Power on] CONFIDENTIAL DO NOT COPY Page 8-16 – File No. SG-0228...
  • Page 99 [Power off] 8. CH1: R228 ; CH2: EN1 [Power off] CONFIDENTIAL DO NOT COPY Page 8-17 – File No. SG-0228...

  • Page 100: Trouble Shooting

    Chapter 9 Trouble shooting MONITOR DISPLAY NOTHING (PC MODE) Start Is Power board output +5VSB &DV12? LED is lighted Is J10 connector good? Is DC-DC OK? Is U1 (+5V) working ok? It is in power saving Check video cable Is the timing supported? LED is lighting? Check sync input Check VGA SOG rout if analog...
  • Page 101 (TV, COMPOSITE VIDEO ) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check DVD player 1.Check P11(VIDEO) signal 2.Check signal between U14 (IF IN AV mode) U14 input correct? 3.Check Tuner & U13 (IF TV mode) 1. Check U14 :DV33&DV12&AV15&AV12 2.
  • Page 102 (COMPONENT) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check host’s setting 1.Check signal between P1 P1 input correct? 2.Check power 12V& 5v 1.Check signal between U14&P1 2.Check U14 Clock (27MHZ) U14 input correct? 3.Check U14 :DV33&DV12&AV15&AV12 1.Check U14 LVDS output correct ? 2.
  • Page 103 HDMI ) IS NOT DISPLAY CORRECTLY Start 1.Check video Input signal good? 2.Check host’s setting 1.Check p6 & p7& P13 connect U22 input correct? 2.Check U22 signal 1.Check U14 power U14 no data out ? 2.Check between signal U22 and U14 3.Check U14 clock 27MHZ 1.Is J7 connected good? 2.Is panel working ok?
  • Page 104 ROUBLE OF DC-DC CONVERTER Start The voltage is about + 5V 1.Check power board 2.Check power cable connection J10 J10 PIN10,11,12 The voltage is about + 12V while power switch on 1.J10 connection good 2.Check J10 Pin2,3 transform +5V_TUNER J10 PIN 2,3 3.Check power board The voltage is about +5V while power switch on U1 pin 5 6 7 8...
  • Page 105 TROUBLE OF DDC READING Start Support DDC1/2B 1.Analog cable ok? 2.Check signal (U21 to P3) Analog DDC 3.Check U21 Voltage 4.Is compliant protocol? Support DDC1/2B 1.Analog cable ok? 2.Check signal (U23 to P6) HDMIDDC 3.Check signal (U25 to P7) 4.Check signal (U26 to P13) 5.Is compliant protocol? CONFIDENTIAL DO NOT COPY...
  • Page 106 (TV_SIDE, AUDIO) IS NOT DISPLAY CORRECTLY Start 1. Check Audio source Input signal good? 2. Check the player of source 1. Check signal of Main Board 2. Check signal of Audio Board (J1) 3. Check the wire of Main Board to J1 input correct? Audio Board 1.
  • Page 107 (SUBWOOFER_SIDE, AUDIO) IS NOT DISPLAY CORRECTLY Start 1. Check Audio source Input signal good? 2. Check the player of source 1. Check signal of Main Board 2. Check signal of Audio Board (J1) 3. Having TX and RX module or not? J1 input correct? 1.

  • Page 108: Block Diagram

    Chapter 10 Block Diagram System Block Diagram LG50” X4 panel Speaker Digital Video bus AC IN Power Board Audio Board J14 TX Connect Main Board P13 P7 P6 P8 P3 P4 P1 P2 □□□□□ Keypad/IR YPBPRX2 RCAX2 Tuner SPDIF out Board RJ11 AUX IN HDMIX3...
  • Page 109 Main Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-2 File No. SG-0228...
  • Page 110 TV_AMP Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-3 File No. SG-0228...
  • Page 111 RX_AMP Board Block Diagram CONFIDENTIAL – DO NOT COPY Page 10-4 File No. SG-0228...

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