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15 . Peripherals :
1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control.
2. Two serial interfaces , one is master only the other can be set to master mode or slave mode.
3. Two PWMs.
4. IR blaster and receiver.
5. IEEE1394 link controller.
6. IDE bus : ATA/ATAPI7 UDMA mode 5 , 100MB/s.
7. Real-time clock and watchdog controller.
8. Memory card I/F : MS/MS-pro ,SD ,CF ,and MMC
9. PCMCIA/POD/CI interface
16 . IC Outline :
1. 471 Pin BGA Package.
2. 3.3V/1.2V dual Voltage.
MX29LV320BTTC (Flash) Application :
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and
2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable
read/write non-volatile random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard EPROM programmers. The standard
MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B has
separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and
programming. The MX29LV320AT/B uses a command register to manage this functionality. MXIC
Flash technology reliably stores memory contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi
process. Latch-up protection is proved for stresses up to 100 milliamperes on address and
data pin from -1V to VCC + 1V.
CONFIDENTIAL
DO NOT COPY
–
Page 7-16
File No. SG-0228
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