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APPENDICES
MELSEC-A
(4)
AD61 ( S l ) high-speed counter module
I
Channel 1
I
Channel
2
1
C H I
I
CH2
Buffer Memory Contents
Current value write
flower bits)
I
82"
(
C2H
I
I
Address Set b y Computer
Unused area (unavailable)
Address Set w i t h FROMITO
Instruction
80H
COH
1
I
33
I
I
Current value write
(higher bits)
84H
85H
Mode register
86H
Current value
read
lhiaher bits)
I
8AH
1
CAH
I
_
Current value write
(middle bits)
-
Current value read
(lower bits)
Current value read
(middle bits)
.
-
I
I
3
\
8BH
CBH
C4 H
C5H
C6H
Set value readlwrite
(lower bits)
/
8CH
I
CCH
I
81 H
83H
88H
89H
6
Set value readlwrite
(middle bits)
8DH
CDH
0
C i H
C3H
2
Set value readlwrite
(higher bits)
8EH
CEH
7
32
34
C8 H
C9 H
\
I
8FH
/
CFH
I
I
APP- 15
4
-
36
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