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SE
RV
IC
E SHEE
T 2 (Cont'd)
Second Amplifier
A4U2 and U3 and associated components are operational ampli-
fiers with voltage gains of
a
bout 25 each. Gain for A4U2 is deter-
mined by
M
R22 and R23;
f
or A4U3 by A4R27 and R28. Bias
current is provided for A4U3 by
M
R25.
The tuned amplifiers upper bandpass
l
imit (240 Hz) is set by
t
he
p arallel RC networks of Α4C11 and R22, A4C14 and R27 and
parallel RC network in the First Amplifier.
Th
ird Amplifier
A4U4A and its associated components form an operational
a mplifier' stage with variable voltage gain from 1.3 to 3.4. The
front panel CAL ADJ gain control is set to compensate for differ-
ences in sensitivity
o
f individual power sensors. The gain is
determined by
M
R24, R21 and
t
he CAL ADJ control R1 .
Sync
h
ronous Detector
The phase shift ofthe 220 Hz
s
ignal through the tuned amplifiers
is approximately zero . Because the phase shift
i
s minimal, error
introduced into the system is also minimal. This ensures that the
detector output is proportional to the RF power input level.
The Synchronous Detector, like the sampling gate circuit in the
power sensor,
i
s driven by the 220 Hz Multivibrator drive signal .
W
hen A4Q6 is biased on, the equivalent sampling gate FET
(which is connected to ground) is also on. Therefore, α n egative
going signal is coupled to the ac amplifiers. B ecause there i s no
phase inversion of the signal throughout the ac amplifiers, the
output ofthe Third Amplifier is also the negative going portion
o
f
t
he distorted
s
inusoidal waveform. During this h alf
c
ycle current
flows from
g
round through A4Q6 and R26to change C12 a nd C13.
Α positive voltage is stored on the positive terminal ofC13.
W
hen
the 220 Hz drive signal turns A4Q6 off and Q7 on, the Third
Amplifier output is the positive going p ortion of the distorted
s
inusoidal waveform. This positive going signal is superimposed
on the voltage across C12 and C13
s
uch that the p eak voltage
i
s
about twice the peak voltage of the Third Amplifier output. This
voltage charges MC 16 through R26 and Q7. The do output vol-
tage is coupled across α d o pass filter to the DC Amplifier.
T
R
O
UBLE
S
H
OOTI
N
G
General
Before attempting to troubleshoot the circuits represented by this
schematic, verify that the p ower
s
upply is operating properly.
The voltage on ΤΡ9 should be +12 Vdc; on ΤΡ10, -12 Vdc.
The important characteristics of the waveforms shown on this
schematic are the frequency a nd peak-to-peak voltage. If
t
he
shape of the waveform varies slightly, the
p
erformance of the
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